coreboot/src/soc
Amanda Huang d925ca70d9 util: Add new memory part to LP4x list
Add memory part MT53E2G32D4NQ-046 to LP4x global list. Attributes
are derived from data sheets.Also, regenerate the SPD files for ADL
SoC using the newly added parts.

BUG=b:181378727
TEST=Compared generated SPD with data sheets and checked in SPD

Change-Id: Ic06e9d672a2d3db2b4ea12d15b462843c90db8f6
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03 15:50:47 +00:00
..
amd soc/amd/cezanne: Disable legacy DMA IO ports 2021-03-02 22:17:20 +00:00
cavium cbfs: Simplify load/map API names, remove type arguments 2020-12-02 22:13:17 +00:00
example arch/x86: Move prologue to .init section 2021-01-07 11:02:03 +00:00
intel util: Add new memory part to LP4x list 2021-03-03 15:50:47 +00:00
mediatek mb/google/asurada: Enable RTC for event log 2021-02-25 08:18:17 +00:00
nvidia src: Remove useless comments in "includes" lines 2021-02-04 10:18:49 +00:00
qualcomm memlayout: Store region sizes as separate symbols 2021-02-19 08:39:26 +00:00
rockchip rk3399: clock: Fix style for rkclk_ddr_reset() 2021-02-26 08:18:28 +00:00
samsung src: Remove unused <boot_device.h> 2021-02-10 07:22:08 +00:00
sifive memlayout: Store region sizes as separate symbols 2021-02-19 08:39:26 +00:00
ti soc/ti/am335x/header.c: Add missing include 2021-02-03 08:55:15 +00:00
ucb soc/ucb/riscv: Add chip_operations stub 2020-05-28 09:30:35 +00:00