When installing the packages, apt-get returns an error about holding
broken packages. It occurs the diffutils depends on libcurl4t64
which breaks the libcurl4.
As a solution, remove the libcurl4 from the list, and let the package
manager resolve the dependencies.
TEST=Build coreboot-sdk
Change-Id: Iabc4f74619d4462317d8adb4068e50135d89d80e
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This is a minimal framework that allows the build to compile.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ief4b5c75471a2ef5bedaaee9b4737510c2826b6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
If the TPM is not detected in the system it may mean it is inactive
due to enabled ME with active PTT. In such case, the chipset will route
the TPM traffic to PTT CRB TPM on Intel systems.
If TPM is not probed, disable the PC80 TPM device driver, so that
coreboot will not generate improper SSDT ACPI table.
Change-Id: I05972ad74a36abaafa2f17a16f09710550a3a3f3
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
If CRB TPM is not detected in the system it may mean it is inactive
due to disabled or neutered ME. In such case, the chipset will route
the TPM traffic to LPC/SPI on Intel systems.
If CRB TPM is not probed, disable the CRB TPM device driver, so that
coreboot will not generate improper SMBIOS/SSDT ACPI tables.
Change-Id: Ie0928536d9042b1f680d585e1ca9ad2cadf0c8ef
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Remove duplicate config entry CHROMEOS_WIFI_SAR as it is
used at the baseboard.
BUG=None
TEST=emerge-rex coreboot
Change-Id: Iabf0e490103c2097f3f033036839b77b5a0bb1b3
Signed-off-by: YH Lin <yueherngl@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81226
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use better alignment attribute macro and add missing identifier names
for function definition arguments.
Change-Id: I1c5c33fc9210f068ff88c8d981f1a1c739890c9c
Signed-off-by: Integral <integral@member.fsf.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82050
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
RAMOOPS memory region was being overwritten by coreboot bmp_load_logo()
function. The CBMEM_ID_FSP_LOGO region created during bmp_load_logo()
was overlapping with RAMOOPS space created earlier. This resulted in
memory corruption of RAMOOPS buffer.
To prevent this, the RAMOOPS region allocation is moved to
BS_DEV_INIT_CHIPS phase from earlier BS_WRITE_TABLES phase of boot.
BUG=b:332910298
TEST=build and boot coreboot image on google/rex HW. Check RAMOOPS
CBMEM region creation using cbmem -l command
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: Ibae06362cd80eacb16f6cf0eed8c9aa1fbfb2535
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82042
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eran Mitrani <mitrani@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch adds support for the new command-line option `-c` to
the ifdtool, which is able to check GPR0 (Global Protected Range)
status.
This patch also add helper function get_enabled_gprd() to get enabled
GPR0 settings. It used in enable_gpr0() and is_gpr0_protected().
Developers can use ifdtool with '-c' option to check whether GPR0 is
set to enabled or disabled in the binary file.
BUG=none
TEST=(1) > ifdtool -p mtl -E image-unlocked.bin -O image-lock.bin
...
Value at GPRD offset (64) is 0x83220004
--------- GPR0 Protected Range --------------
Start address = 0x00004000
End address = 0x00322fff
...
GPR0 protection is now enabled
(2) > ifdtool -p mtl -c image-unlocked.bin
GPR0 status: Disabled
Value at GPRD offset (64) is 0x00000000
--------- GPR0 Protected Range --------------
Start address = 0x00000000
End address = 0x00000fff
(3) > ifdtool -p mtl -c image-lock.bin
GPR0 status: Enabled
Value at GPRD offset (64) is 0x83220004
--------- GPR0 Protected Range --------------
Start address = 0x00004000
End address = 0x00322fff
Change-Id: I6b3af973be784200b965a68e5f6b7737cba03ed7
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
1.Enable CHROMEOS_WIFI_SAR flag to load a SAR table for Intel module.
2.Describe the FW_CONFIG probe for the settings on glassway.
- WIFI_SAR_0 for Intel Wi-Fi module AX211
BUG=336051631
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I9e43081c93ef17291c5d55cf262a0f4d1497447b
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81781
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
We can assume that platforms, which select HAVE_INTEL_PTT, will not
have any other CRB TPM than PTT. Check whether PTT is available before
forcefully initializing the TPM and selecting the CRB interface in the
TPM configuration registers.
Change-Id: If0ec6217b0e321b7d7a9410b70defde3c3195fc3
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80453
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Add STA panel STA_ER88577 serializable data to CBFS.
Datasheet: 2081101BH8028073-50E_Pre Spec_240424.pdf
About the init code, we communicated with the vendor through the
datasheet to confirm the writing method of each register value.
BUG=b:331870701
TEST=build and check the CBFS includes the panel
BRANCH=None
Change-Id: I210b23b67fbc102c9926171f1c78f6824820e4b7
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82054
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Explicitly assign a value of 0 to the first value of the
pcie_swizzle_pin enum. This won't change the behavior, but clarifies
that the actual values of the enum elements matter.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I21850e21f859f2079f804d4344a1a11856b27d90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Rename the 'irq' element of the pci_routing_info struct to 'bridge_irq'
to better describe what it's doing. This struct element contains the
number of the northbridge IOAPIC IRQ input the bridge IRQ is connected
to signal power management or error reporting IRQs. Right now, coreboot
doesn't put this information into the ACPI bytecode.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6410be673d15d6f9b5eb4c80b51fb705fec5b155
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
This patch extends the cpu_get_cache_info function, so that
additional information like size of cache lines can be retrieved.
Patch was tested against the qemu-sbsa mainboard.
Change-Id: If6fe731dc67ffeaff9344d2bd2627f45185c27de
Signed-off-by: David Milosevic <David.Milosevic@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79106
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
There are 4 different chassis types specified by vendor firmware, each
with a slightly different HWM configuration.
The chassis type to use is determined at runtime by reading a set of
4 PCH GPIOs: 70, 38, 17, and 1.
Additionally vendor firmware also provides an option to run the fans at
full speed. This is substituted with a coreboot nvram option in this
implementation.
This was tested to make fan control work on my OptiPlex 7020 SFF.
NOTE: This is superficially similar to the OptiPlex 9010's SCH5545
however the OptiPlex 9020's SCH5555 does not use externally
programmed EC firmware.
Change-Id: Ibdccd3fc7364e03e84ca606592928410624eed43
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81529
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a new GPIO port cbj-sleeve for kernel driver to call. At the same
time, a new rt5645 driver is added to replace the generic driver to
parse gpio. After entering the system, it is pulled high by the kernel
to enable the MIC function.
BUG=None
TEST=MIC function is normal
Change-Id: I093be6a3e357aae389fcbe8291a9701c40b62e15
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81774
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
RT5663 is very old and it was used the hard code like RT53 or 10EC5663,
which is the different series from RT5645/5650, it may caused some
ambiguity. Because I2C generic driver dose not support dsd gpio
setting, we declared the new rt5645 series driver for expansion.
Add RT5645 AMP support. The kernel driver of 5650 is written
in rt5645.c. Add acpi name cbj-sleeve-gpios for power gate GPIO.
ALC5650 DataSheet Rev 0.93
Realtek upstream link:
https://lore.kernel.org/all/20240404035747.118064-1-derek.fang@realtek.com/
Hide the device because of Microsoft Windows.
BUG=None
TEST=verified in anraggar and probe device rt5650 succeed
```
\_SB.PCI0.I2C3.RT58: Realtek RT5650
```
Change-Id: I602fcc4dd8576043943f6e20884edc4703350320
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81773
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
FSP 2.4 brings FSP 64-bits support which requires some adjustments in
coreboot:
FSP/UEFI uses the Microsoft x64 calling convention. Appropriate
attribute has to be set to all functions calling or called by
the FSP.
BUG=b:329034258
TEST=verified on Lunar Lake RVP board (lnlrvp)
Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec99
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
In the non-stub openSIL coreboot glue code, this can be used to add the
ALIB SSDT.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3ccd2e81211417ad4ac94f208572e0fa4e1cf97c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82012
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allow to set board specific CPU voltage regulator settings.
The VR12 compatible voltage regulator for the CPU can be configured
by two MSRs. Currently a default value is applied, which mimics the
Intel reference code and is what the BWG suggest. However most board
vendors fill in the actual VR parameters to support OC or ULV board
variants.
When the mainboard design is too different from the Intel reference
design, not updating the VR settings might result in:
- unstable system behaviour
- limited turbo performance
- excessive battery drain
- no over-clocking capability
This patch adds support to set the board specific current limit for
Icc and Igfx.
It also allows to adjust PSI1, PSI2 and PSI3, which are powerstates
used by the VR, that consume less energy when the system is idle.
Test on Lenovo X220 with full CPU load after 1 minute, compared to
previous code with default settings:
- Limiting PP0 max current below Iccmax results in less CPU performance.
RAPL readings show that less power is drawn over time.
- Limiting PP0 max current to Iccmax results in equal CPU performance.
RAPL readings show that the same power is drawn over time.
- Setting the PP0 max current to a value >> Iccmax results in equal CPU
performance. RAPL readings show that the same power is drawn over
time.
- Updating the MSR at runtime has no effect.
Change-Id: I59edab47fc4fbe0240e1dd7d25647f7549b4def2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch introduces fsp print helper macros to print
`efi_return_status_t' with the appropriate format. These macros
are now used for fsp debug prints with return status
efi_return_status_t is defined as UINT64 or UNIT32 based on the
selected architecture
BUG=b:329034258
TEST=Verified on Meteor Lake board (Rex)
Change-Id: If6342c4d40c76b702351070e424797c21138a4a9
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81630
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If the ChromiumOS EC indicates that the device has an assistant key,
we should also add it to the generated linux,keymap binding. This
commit simply does so by examining the keyboard capabilities reported by
the EC.
BUG=b:333088656
TEST=With a device that has an assistant key, flash AP FW and verify
that the key is mapped to `KEY_ASSISTANT` in the Linux kernel using
`evtest`.
Change-Id: I217220e89bce88e3045a4fc3b124954696276442
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81996
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
When the input device pointer pointing to a domain device,
dev_get_domain returns the input device itself.
TEST=Build and boot on intel/archercity CRB
Change-Id: I3a278a8f573de95406ee256fba17767def4ad75d
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Do not fill the ACPI table entry associated with the cros_ec_typec
driver once we switch to the UCSI kernel driver. Skip the ACPI entry if
EC implements the UCSI_PPM feature, and the CBI flag to enable UCSI is
set.
BUG=b:333078787
TEST=emerge-brox coreboot chromeos-bootimage
Cq-Depend: chromium:5416841
Change-Id: I67dff6445aa7ba3ba48a04d1df3541f880d09d0a
Signed-off-by: Pavan Holla <pholla@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The DPTF parameters were defined by the thermal team.
Based on thermal table in 330817690#comment33.
Set 6w "tcc_offset" to "15" by fw_config.
BUG=b:330817690, b:290705146
BRUNCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I19100d960919dc3087fd067c24659de467eea276
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81997
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Currently, arch/arm64 requires coreboot to run on EL3 due
to EL3 register access. This might be an issue when, for example,
one boots into TF-A first and drops into EL2 for coreboot afterwards.
This patch aims at making arch/arm64 more versatile by removing the
current EL3 constraint and allowing arm64 coreboot to run on EL1,
EL2 and EL3.
The strategy here, is to add a Kconfig option (ARM64_CURRENT_EL) which
lets us specify coreboot's EL upon entry. Based on that, we access the
appropriate ELx registers. So, for example, when running coreboot on
EL1, we would not access vbar_el3 or vbar_el2 but instead vbar_el1.
This way, we don't generate faults when accessing higher-EL registers.
Currently only tested on the qemu-aarch64 target. Exceptions were
tested by enabling FATAL_ASSERTS.
Signed-off-by: David Milosevic <David.Milosevic@9elements.com>
Change-Id: Iae1c57f0846c8d0585384f7e54102a837e701e7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74798
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This should keep new makefiles from being named Makefile.inc.
Change-Id: I4a47998e1c997b82b8a15319eae96cdc0de64e77
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81857
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Core 2 platforms have issues with HPET. Enable support to use the LAPIC
driver so those machines actually boot and don't hang.
The LAPIC is actually closer to the CPU than the HPET (on the PCH),
which reduces access latency, leading to higher resolution of the timer.
Tested on a Lenovo X200 with a Core 2 Duo.
Change-Id: I33144d6c1c120e7faa47b99e8262b0997c45c9b9
Signed-off-by: Jean Lucas <jean@4ray.co>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82000
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Generated using update_ec_headers.sh [EC-DIR].
The original include/ec_commands.h version in the EC repo is:
b3b35d6433 PPM: Rename ucsi_disabled to ucsi_enabled
The original include/ec_cmd_api.h version in the EC repo is:
562316a71e include: Add fingerprint host commands to ec_cmd_api.h
BUG=b:333078787
TEST=cros build-packages --board brox \
chromeos-bootimage depthcharge coreboot
TEST=cros build-packages --board brya \
chromeos-bootimage depthcharge coreboot
BRANCH=none
Change-Id: I94b509cd6ad8f24bfc3b44ef02633d06320f1e22
Signed-off-by: Pavan Holla <pholla@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81965
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Commit 00b40090ae ("mb/google/brox: Move hda verb to variant dir")
introduces a variant-specific file for the HDA verb tables, which
commit 1bf0c3f189 ("mb/google/brox: Create lotso variant") was missing
which caused the build to fail when both patches were submitted. To fix
the tree, add this file to the newly created lotso variant.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8a85115a204d9d9447a58da71eb65b1de963023d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82014
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Create the lotso variant of the brox reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:333494257
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brox -x -a
make sure the build includes GOOGLE_LOTSO
Change-Id: I5939127f9e6abe5b792c0627d9d67e739b27083b
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Some devices may generate scancodes for the Fn key if they have one.
If they do, we should add them to the linux,keymap binding.
BUG=b:333096023
TEST=Flash DUT that emits a scancode for the Fn key, verify that it is
mapped to KEY_FN in the Linux kernel using `evtest` when pressing the Fn
key.
Change-Id: Ie4daa64bc6b619392276d0b5f16e2d195d5bd68c
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
One can argue whether or not this is desirable, but disabling this means
you cannot use power from the USB ports when the board shuts down, which
is better controlled from an option, but at the very least disabled so
as to replicate default vendor firmware behaviour.
Disable deep sleep like it is disabled on all other variants.
Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Change-Id: I660f2efebf197df055ee7b9c349e4c2b64bda6cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75139
Reviewed-by: Keith Hui <buurin@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Copied this bit from asus/p8z77-m_pro, without it a GRUB2 payload will
get stuck in an endless loop showing
Unknown key 0xff detected
whenever there is an USB device (such as a keyboard) connected.
In this mode GRUB2 is so busy showing this message repeatedly that no
other keypress ever gets handled, and thus no other remedy is possible
than a reset via mb pins and unplugging the USB device.
Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Change-Id: Iebd433e2762a69241257e1b4f859319536a8d8f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75138
Reviewed-by: Keith Hui <buurin@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add STORAGE_UNKNOWN, STORAGE_UFS, STORAGE_NVME for storage fw_config
field to prevent depthcharge build break.
BUG=b:333325006
TEST=emerge-brox coreboot depthcharge with no errors
Change-Id: I0e220787d6ac73ec8fa2469ed958981d0801920e
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Make sure it can be used for other driver.
At present, i2c_generic_write_gpio() is not suitable for being called
by other drivers, so delete it, add acpi_device_write_dsd_gpio() to
replace it, and make it public.
BUG=None
TEST= Build BIOS FW pass and it can be use for other driver.
Change-Id: Ifb2e60690711b39743afd455c6776c5ace863378
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Update the A0 and B0 stepping IDs in CPU table per
the PPR document 57254 Rev 1.56 and 1.69
Change-Id: I0072f25f981ac7d5df2522594c8788bfabcbf24c
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Change `inl()` return type from `unsigned long` to `unsigned int` to
match the function definition and ensure consistency across platforms.
BUG=b:242829490
TEST=Compiled successfully in 32-bit and 64-bit modes.
Change-Id: I681935665c8de9ee472ab72fe1ac2f5dcc0f2534
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Michał Żygowski