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mb/asrock/h110m: disable unused serial buses 

Disable spi0, i2c0 and i2c1 in the “SerialIoDevMode” register for the
following reasons:

1. when the AMI BIOS is used, these pci devices are disabled in
   lspci.log;
2. there are no pads in the inteltool.log that use the functions of
   these buses

Change-Id: I01ab10eb3fd41e81a1726805247c2b472d72287c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35070
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Maxim Polyakov 2019-08-21 16:29:07 +03:00 committed by Patrick Georgi
parent 21353baa16
commit a433da754a
1 changed files with 3 additions and 3 deletions
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6
src/mainboard/asrock/h110m/devicetree.cb
View File

@ -190,13 +190,13 @@ chip soc/intel/skylake
# PCH UART, SPI, I2C
register "SerialIoDevMode" = "{ \
[PchSerialIoIndexI2C0] = PchSerialIoPci, \
[PchSerialIoIndexI2C1] = PchSerialIoPci, \
[PchSerialIoIndexI2C0] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C1] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C4] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
[PchSerialIoIndexSpi0] = PchSerialIoPci, \
[PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
[PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
[PchSerialIoIndexUart0] = PchSerialIoDisabled, \
[PchSerialIoIndexUart1] = PchSerialIoDisabled, \