arch/x86: Remove NO_FIXED_XIP_ROM_SIZE

The variable SETUP_XIP_CACHE provides us a working
alternative.

Change-Id: I6e3befedbbc7967b71409640dc81a0c2a9b3e511
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Makefile.inc

@@ -1177,9 +1177,10 @@ $(CONFIG_CBFS_PREFIX)/romstage-options := -S ".car.data"
 ifneq ($(CONFIG_NO_XIP_EARLY_STAGES),y)
 $(CONFIG_CBFS_PREFIX)/romstage-options += --xip
 
-ifneq ($(CONFIG_NO_FIXED_XIP_ROM_SIZE),y)
+# For efficient MTRR utilisation use natural alignment for romstage.
+ifeq ($(CONFIG_SETUP_XIP_CACHE),y)
 $(CONFIG_CBFS_PREFIX)/romstage-options += --pow2page
-endif    # CONFIG_NO_FIXED_XIP_ROM_SIZE
+endif    # CONFIG_SETUP_XIP_CACHE
 
 endif   # CONFIG_NO_XIP_EARLY_STAGES
 endif   # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64

src/cpu/amd/agesa/Kconfig

@@ -16,7 +16,6 @@ config CPU_AMD_AGESA
 	select LAPIC_MONOTONIC_TIMER
 	select SPI_FLASH if HAVE_ACPI_RESUME
 	select SMM_ASEG
-	select NO_FIXED_XIP_ROM_SIZE
 	select SSE2
 
 if CPU_AMD_AGESA

src/cpu/amd/pi/Kconfig

@@ -16,7 +16,6 @@ config CPU_AMD_PI
 	select LAPIC_MONOTONIC_TIMER
 	select SPI_FLASH if HAVE_ACPI_RESUME
 	select SMM_ASEG
-	select NO_FIXED_XIP_ROM_SIZE
 	select SSE2
 
 if CPU_AMD_PI

src/cpu/intel/haswell/Kconfig

@@ -22,7 +22,6 @@ config CPU_SPECIFIC_OPTIONS
 	select PARALLEL_MP
 	select CPU_INTEL_COMMON
 	select CPU_INTEL_COMMON_TIMEBASE
-	select NO_FIXED_XIP_ROM_SIZE
 
 config SMM_TSEG_SIZE
 	hex

src/cpu/intel/model_2065x/Kconfig

@@ -19,7 +19,6 @@ config CPU_SPECIFIC_OPTIONS
 	select TSC_SYNC_MFENCE
 	select CPU_INTEL_COMMON
 	select CPU_INTEL_COMMON_TIMEBASE
-	select NO_FIXED_XIP_ROM_SIZE
 	select PARALLEL_MP
 
 config SMM_TSEG_SIZE

src/cpu/intel/model_206ax/Kconfig

@@ -20,7 +20,6 @@ config CPU_SPECIFIC_OPTIONS
 	select CPU_INTEL_COMMON
 	select CPU_INTEL_COMMON_TIMEBASE
 	select PARALLEL_MP
-	select NO_FIXED_XIP_ROM_SIZE
 
 config SMM_TSEG_SIZE
 	hex

src/cpu/intel/socket_FCBGA559/Kconfig

@@ -11,7 +11,6 @@ config SOCKET_SPECIFIC_OPTIONS
 	select MMX
 	select SSE
 	select CPU_HAS_L2_ENABLE_MSR
-	select NO_FIXED_XIP_ROM_SIZE
 
 config DCACHE_RAM_BASE
 	hex

src/cpu/x86/Kconfig

@@ -60,16 +60,6 @@ config TSC_SYNC_MFENCE
 	  to execute an mfence instruction in order to synchronize
 	  rdtsc. This is true for all modern Intel CPUs.
 
-config NO_FIXED_XIP_ROM_SIZE
-	bool
-	default n
-	help
-	  The XIP_ROM_SIZE Kconfig variable is used globally on x86
-	  with the assumption that all chipsets utilize this value.
-	  For the chipsets which do not use the variable it can lead
-	  to unnecessary alignment constraints in cbfs for romstage.
-	  Therefore, allow those chipsets a path to not be burdened.
-
 config SETUP_XIP_CACHE
 	bool
 	depends on !NO_XIP_EARLY_STAGES

src/soc/intel/baytrail/Kconfig

@@ -20,7 +20,6 @@ config CPU_SPECIFIC_OPTIONS
 	select SOUTHBRIDGE_INTEL_COMMON_RESET
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
 	select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT
-	select NO_FIXED_XIP_ROM_SIZE
 	select PARALLEL_MP
 	select PCIEXP_ASPM
 	select PCIEXP_COMMON_CLOCK

src/soc/intel/braswell/Kconfig

@@ -17,7 +17,6 @@ config CPU_SPECIFIC_OPTIONS
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
 	select HAVE_SMI_HANDLER
-	select NO_FIXED_XIP_ROM_SIZE
 	select PARALLEL_MP
 	select PCIEXP_ASPM
 	select PCIEXP_CLK_PM

src/soc/intel/broadwell/Kconfig

@@ -44,7 +44,6 @@ config CPU_SPECIFIC_OPTIONS
 	select INTEL_GMA_ACPI
 	select HAVE_POWER_STATE_AFTER_FAILURE
 	select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
-	select NO_FIXED_XIP_ROM_SIZE
 
 config PCIEXP_ASPM
 	bool

src/soc/intel/common/block/cpu/Kconfig

@@ -21,7 +21,6 @@ config SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
 config SOC_INTEL_COMMON_BLOCK_CAR
 	bool
 	default n
-	select NO_FIXED_XIP_ROM_SIZE
 	help
 	  This option allows you to select how cache-as-ram (CAR) is set up.