coreboot-mirror
/
coreboot
mirror of https://review.coreboot.org/coreboot.git
1
0
Fork 0
Code Issues Releases Wiki Activity

arch/x86: Remove XIP_ROM_SIZE 

When adding XIP stages on x86, the -P parameter was used to
pass a page size that covers the entire file to add. The same
can now be achieved with --pow2page and we no longer need to
define a static Konfig for the purpose.

TEST: Build asus/p2b and lenovo/x60 with "--pow2page -v -v" and
inspect the generated make.log files. The effective pagesize is
reduced from 64kB to 16kB for asus/p2b giving more freedom
for the stage placement inside CBFS. Pagesize remained at 64kB
for lenovo/x60.

Change-Id: I5891fa2c2bb2d44077f745619162b143d083a6d1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Keith Hui <buurin@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2020-05-25 08:52:07 +03:00 committed by Nico Huber
parent c36469e0b1
commit 49c44cdccb
3 changed files with 1 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Makefile.inc
View File

@ -1177,10 +1177,8 @@ $(CONFIG_CBFS_PREFIX)/romstage-options := -S ".car.data"
ifneq ($(CONFIG_NO_XIP_EARLY_STAGES),y)
$(CONFIG_CBFS_PREFIX)/romstage-options += --xip
# If XIP_ROM_SIZE isn't being used don't overly constrain romstage by passing
# -P with a default value.
ifneq ($(CONFIG_NO_FIXED_XIP_ROM_SIZE),y)
$(CONFIG_CBFS_PREFIX)/romstage-options += -P $(CONFIG_XIP_ROM_SIZE)
$(CONFIG_CBFS_PREFIX)/romstage-options += --pow2page
endif # CONFIG_NO_FIXED_XIP_ROM_SIZE
endif # CONFIG_NO_XIP_EARLY_STAGES

5
src/cpu/x86/Kconfig
View File

@ -70,11 +70,6 @@ config NO_FIXED_XIP_ROM_SIZE
to unnecessary alignment constraints in cbfs for romstage.
Therefore, allow those chipsets a path to not be burdened.
config XIP_ROM_SIZE
hex
depends on !NO_FIXED_XIP_ROM_SIZE
default 0x10000
config SETUP_XIP_CACHE
bool
depends on !NO_XIP_EARLY_STAGES

4
src/include/cpu/x86/mtrr.h
View File

@ -190,10 +190,6 @@ static inline unsigned int fls(unsigned int x)
*/
#define CACHE_TMP_RAMTOP (16<<20)
#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0)
# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
#endif
/* For ROM caching, generally, try to use the next power of 2. */
#define OPTIMAL_CACHE_ROM_SIZE _ALIGN_UP_POW2(CONFIG_ROM_SIZE)
#define OPTIMAL_CACHE_ROM_BASE _FROM_4G_TOP(OPTIMAL_CACHE_ROM_SIZE)