2009-10-23 20:22:27 +02:00
|
|
|
/*
|
2008-10-03 17:17:47 +02:00
|
|
|
* This file is part of the coreboot project.
|
2009-10-23 20:22:27 +02:00
|
|
|
*
|
2008-10-03 17:17:47 +02:00
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
* it under the terms of the GNU General Public License as published by
|
|
|
|
* the Free Software Foundation; version 2 of the License.
|
2009-10-23 20:22:27 +02:00
|
|
|
*
|
2008-10-03 17:17:47 +02:00
|
|
|
* This program is distributed in the hope that it will be useful,
|
|
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
|
* GNU General Public License for more details.
|
|
|
|
*/
|
|
|
|
|
2009-10-23 20:22:27 +02:00
|
|
|
#include <cpu/x86/mtrr.h>
|
2012-03-31 12:52:21 +02:00
|
|
|
#include <cpu/x86/cache.h>
|
2011-04-11 22:17:22 +02:00
|
|
|
#include <console/post_codes.h>
|
2008-10-03 17:17:47 +02:00
|
|
|
|
2010-10-01 01:15:36 +02:00
|
|
|
#define CacheSize CONFIG_DCACHE_RAM_SIZE
|
|
|
|
#define CacheBase CONFIG_DCACHE_RAM_BASE
|
|
|
|
|
2011-01-19 07:54:42 +01:00
|
|
|
/* Save the BIST result. */
|
|
|
|
movl %eax, %ebp
|
2008-10-03 17:17:47 +02:00
|
|
|
|
|
|
|
CacheAsRam:
|
|
|
|
|
2011-01-19 07:54:42 +01:00
|
|
|
/* Disable cache. */
|
|
|
|
movl %cr0, %eax
|
2012-03-31 12:52:21 +02:00
|
|
|
orl $CR0_CacheDisable, %eax
|
2011-01-19 07:54:42 +01:00
|
|
|
movl %eax, %cr0
|
2008-10-03 17:17:47 +02:00
|
|
|
invd
|
|
|
|
|
2010-10-01 01:15:36 +02:00
|
|
|
/* Set the default memory type and enable fixed and variable MTRRs. */
|
2015-10-01 05:23:09 +02:00
|
|
|
movl $MTRR_DEF_TYPE_MSR, %ecx
|
2009-10-23 20:22:27 +02:00
|
|
|
xorl %edx, %edx
|
2015-10-01 05:23:09 +02:00
|
|
|
movl $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax
|
2008-10-03 17:17:47 +02:00
|
|
|
wrmsr
|
|
|
|
|
2010-10-01 01:15:36 +02:00
|
|
|
/* Clear all MTRRs. */
|
2009-10-23 20:22:27 +02:00
|
|
|
xorl %edx, %edx
|
2010-10-12 08:13:40 +02:00
|
|
|
movl $all_mtrr_msrs, %esi
|
2009-10-23 20:22:27 +02:00
|
|
|
|
2008-10-03 17:17:47 +02:00
|
|
|
clear_fixed_var_mtrr:
|
2009-10-23 20:22:27 +02:00
|
|
|
lodsl (%esi), %eax
|
|
|
|
testl %eax, %eax
|
|
|
|
jz clear_fixed_var_mtrr_out
|
2008-10-03 17:17:47 +02:00
|
|
|
|
2009-10-23 20:22:27 +02:00
|
|
|
movl %eax, %ecx
|
|
|
|
xorl %eax, %eax
|
2008-10-03 17:17:47 +02:00
|
|
|
wrmsr
|
|
|
|
|
2009-10-23 20:22:27 +02:00
|
|
|
jmp clear_fixed_var_mtrr
|
2010-04-09 22:36:29 +02:00
|
|
|
|
2010-10-12 08:13:40 +02:00
|
|
|
all_mtrr_msrs:
|
|
|
|
/* fixed MTRR MSRs */
|
2015-10-01 05:23:09 +02:00
|
|
|
.long MTRR_FIX_64K_00000
|
|
|
|
.long MTRR_FIX_16K_80000
|
|
|
|
.long MTRR_FIX_16K_A0000
|
|
|
|
.long MTRR_FIX_4K_C0000
|
|
|
|
.long MTRR_FIX_4K_C8000
|
|
|
|
.long MTRR_FIX_4K_D0000
|
|
|
|
.long MTRR_FIX_4K_D8000
|
|
|
|
.long MTRR_FIX_4K_E0000
|
|
|
|
.long MTRR_FIX_4K_E8000
|
|
|
|
.long MTRR_FIX_4K_F0000
|
|
|
|
.long MTRR_FIX_4K_F8000
|
2010-10-12 08:13:40 +02:00
|
|
|
|
|
|
|
/* var MTRR MSRs */
|
2015-10-01 05:23:09 +02:00
|
|
|
.long MTRR_PHYS_BASE(0)
|
|
|
|
.long MTRR_PHYS_MASK(0)
|
|
|
|
.long MTRR_PHYS_BASE(1)
|
|
|
|
.long MTRR_PHYS_MASK(1)
|
|
|
|
.long MTRR_PHYS_BASE(2)
|
|
|
|
.long MTRR_PHYS_MASK(2)
|
|
|
|
.long MTRR_PHYS_BASE(3)
|
|
|
|
.long MTRR_PHYS_MASK(3)
|
|
|
|
.long MTRR_PHYS_BASE(4)
|
|
|
|
.long MTRR_PHYS_MASK(4)
|
|
|
|
.long MTRR_PHYS_BASE(5)
|
|
|
|
.long MTRR_PHYS_MASK(5)
|
|
|
|
.long MTRR_PHYS_BASE(6)
|
|
|
|
.long MTRR_PHYS_MASK(6)
|
|
|
|
.long MTRR_PHYS_BASE(7)
|
|
|
|
.long MTRR_PHYS_MASK(7)
|
2010-04-09 22:36:29 +02:00
|
|
|
|
|
|
|
.long 0x000 /* NULL, end of table */
|
|
|
|
|
2008-10-03 17:17:47 +02:00
|
|
|
clear_fixed_var_mtrr_out:
|
2015-10-01 05:23:09 +02:00
|
|
|
movl $MTRR_PHYS_BASE(0), %ecx
|
2009-10-23 20:22:27 +02:00
|
|
|
xorl %edx, %edx
|
2010-10-01 01:15:36 +02:00
|
|
|
movl $(CacheBase | MTRR_TYPE_WRBACK), %eax
|
2008-10-03 17:17:47 +02:00
|
|
|
wrmsr
|
|
|
|
|
2015-10-01 05:23:09 +02:00
|
|
|
movl $MTRR_PHYS_MASK(0), %ecx
|
2008-10-03 17:17:47 +02:00
|
|
|
/* This assumes we never access addresses above 2^36 in CAR. */
|
2010-10-01 01:15:36 +02:00
|
|
|
movl $0x0000000f, %edx
|
2015-10-01 05:23:09 +02:00
|
|
|
movl $(~(CacheSize - 1) | MTRR_PHYS_MASK_VALID), %eax
|
2008-10-03 17:17:47 +02:00
|
|
|
wrmsr
|
|
|
|
|
2010-10-01 01:15:36 +02:00
|
|
|
/*
|
|
|
|
* Enable write base caching so we can do execute in place (XIP)
|
|
|
|
* on the flash ROM.
|
2010-09-30 23:22:40 +02:00
|
|
|
*/
|
2015-10-01 05:23:09 +02:00
|
|
|
movl $MTRR_PHYS_BASE(1), %ecx
|
2010-09-30 23:22:40 +02:00
|
|
|
xorl %edx, %edx
|
2010-10-02 22:51:29 +02:00
|
|
|
/*
|
2011-10-28 20:28:03 +02:00
|
|
|
* IMPORTANT: The following calculation _must_ be done at runtime. See
|
2018-08-19 20:02:05 +02:00
|
|
|
* https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html
|
2010-10-02 22:51:29 +02:00
|
|
|
*/
|
2018-06-25 17:53:36 +02:00
|
|
|
movl $_program, %eax
|
2011-10-28 20:28:03 +02:00
|
|
|
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
|
2010-10-01 14:24:57 +02:00
|
|
|
orl $MTRR_TYPE_WRBACK, %eax
|
2008-10-03 17:17:47 +02:00
|
|
|
wrmsr
|
|
|
|
|
2015-10-01 05:23:09 +02:00
|
|
|
movl $MTRR_PHYS_MASK(1), %ecx
|
2009-10-23 20:22:27 +02:00
|
|
|
movl $0x0000000f, %edx
|
2015-10-01 05:23:09 +02:00
|
|
|
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
|
2008-10-03 17:17:47 +02:00
|
|
|
wrmsr
|
|
|
|
|
2010-10-01 09:27:51 +02:00
|
|
|
/* Set the default memory type and enable fixed and variable MTRRs. */
|
|
|
|
/* TODO: Or also enable fixed MTRRs? Bug in the code? */
|
2015-10-01 05:23:09 +02:00
|
|
|
movl $MTRR_DEF_TYPE_MSR, %ecx
|
2009-10-23 20:22:27 +02:00
|
|
|
xorl %edx, %edx
|
2015-10-01 05:23:09 +02:00
|
|
|
movl $(MTRR_DEF_TYPE_EN), %eax
|
2008-10-03 17:17:47 +02:00
|
|
|
wrmsr
|
|
|
|
|
2011-01-19 07:54:42 +01:00
|
|
|
/* Enable cache. */
|
|
|
|
movl %cr0, %eax
|
2012-03-31 12:52:21 +02:00
|
|
|
andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
|
2011-01-19 07:54:42 +01:00
|
|
|
movl %eax, %cr0
|
2008-10-03 17:17:47 +02:00
|
|
|
|
2010-10-01 01:15:36 +02:00
|
|
|
/* Read the range with lodsl. */
|
2008-10-03 17:17:47 +02:00
|
|
|
cld
|
2009-10-23 20:22:27 +02:00
|
|
|
movl $CacheBase, %esi
|
|
|
|
movl %esi, %edi
|
2010-10-01 01:15:36 +02:00
|
|
|
movl $(CacheSize >> 2), %ecx
|
2009-10-23 20:22:27 +02:00
|
|
|
rep lodsl
|
2008-10-03 17:17:47 +02:00
|
|
|
|
2009-10-23 20:22:27 +02:00
|
|
|
movl $CacheBase, %esi
|
|
|
|
movl %esi, %edi
|
|
|
|
movl $(CacheSize >> 2), %ecx
|
2008-10-03 17:17:47 +02:00
|
|
|
|
2018-01-01 14:36:49 +01:00
|
|
|
/* Zero out the cache-as-ram area. */
|
|
|
|
xorl %eax, %eax
|
2009-10-23 20:22:27 +02:00
|
|
|
rep stosl
|
2008-10-03 17:17:47 +02:00
|
|
|
|
2010-10-01 01:15:36 +02:00
|
|
|
/*
|
|
|
|
* The key point of this CAR code is C7 cache does not turn into
|
2008-10-03 17:17:47 +02:00
|
|
|
* "no fill" mode, which is not compatible with general CAR code.
|
|
|
|
*/
|
|
|
|
|
2009-10-23 20:22:27 +02:00
|
|
|
movl $(CacheBase + CacheSize - 4), %eax
|
|
|
|
movl %eax, %esp
|
2008-10-03 17:17:47 +02:00
|
|
|
|
2011-01-19 07:54:42 +01:00
|
|
|
/* Restore the BIST result. */
|
|
|
|
movl %ebp, %eax
|
2009-10-23 20:22:27 +02:00
|
|
|
|
2010-10-01 01:15:36 +02:00
|
|
|
/* We need to set EBP? No need. */
|
2008-10-03 17:17:47 +02:00
|
|
|
movl %esp, %ebp
|
2010-10-01 01:15:36 +02:00
|
|
|
pushl %eax /* BIST */
|
2010-04-09 22:36:29 +02:00
|
|
|
call main
|
|
|
|
|
2010-04-27 08:56:47 +02:00
|
|
|
/*
|
2010-04-09 22:36:29 +02:00
|
|
|
* TODO: Backup stack in CACHE_AS_RAM into MMX and SSE and after we
|
|
|
|
* get STACK up, we restore that. It is only needed if we
|
|
|
|
* want to go back.
|
|
|
|
*/
|
2010-04-27 08:56:47 +02:00
|
|
|
|
2010-10-01 09:27:51 +02:00
|
|
|
/* We don't need CAR from now on. */
|
2010-04-09 22:36:29 +02:00
|
|
|
|
2011-01-19 07:54:42 +01:00
|
|
|
/* Disable cache. */
|
|
|
|
movl %cr0, %eax
|
2012-03-31 12:52:21 +02:00
|
|
|
orl $CR0_CacheDisable, %eax
|
2011-01-19 07:54:42 +01:00
|
|
|
movl %eax, %cr0
|
2010-04-09 22:36:29 +02:00
|
|
|
|
2010-10-01 09:27:51 +02:00
|
|
|
/* Set the default memory type and enable variable MTRRs. */
|
|
|
|
/* TODO: Or also enable fixed MTRRs? Bug in the code? */
|
2015-10-01 05:23:09 +02:00
|
|
|
movl $MTRR_DEF_TYPE_MSR, %ecx
|
2010-10-01 01:15:36 +02:00
|
|
|
xorl %edx, %edx
|
2015-10-01 05:23:09 +02:00
|
|
|
movl $(MTRR_DEF_TYPE_EN), %eax
|
2010-04-09 22:36:29 +02:00
|
|
|
wrmsr
|
|
|
|
|
2016-06-19 19:38:41 +02:00
|
|
|
/* Enable caching for 0..CACHE_TMP_RAMTOP. */
|
2015-10-01 05:23:09 +02:00
|
|
|
movl $MTRR_PHYS_BASE(0), %ecx
|
2010-10-01 01:15:36 +02:00
|
|
|
xorl %edx, %edx
|
2016-06-16 20:14:25 +02:00
|
|
|
movl $(0x0 | MTRR_TYPE_WRBACK), %eax
|
2010-04-09 22:36:29 +02:00
|
|
|
wrmsr
|
2010-04-27 08:56:47 +02:00
|
|
|
|
2015-10-01 05:23:09 +02:00
|
|
|
movl $MTRR_PHYS_MASK(0), %ecx
|
2010-10-01 01:15:36 +02:00
|
|
|
movl $0x0000000f, %edx /* AMD 40 bit 0xff */
|
2016-06-19 19:38:41 +02:00
|
|
|
movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
|
2010-04-27 08:56:47 +02:00
|
|
|
wrmsr
|
|
|
|
|
2011-10-31 17:07:52 +01:00
|
|
|
/* Cache XIP_ROM area to speedup coreboot code. */
|
2015-10-01 05:23:09 +02:00
|
|
|
movl $MTRR_PHYS_BASE(1), %ecx
|
2010-10-01 01:15:36 +02:00
|
|
|
xorl %edx, %edx
|
2011-10-28 20:28:03 +02:00
|
|
|
/*
|
|
|
|
* IMPORTANT: The following calculation _must_ be done at runtime. See
|
2018-08-19 20:02:05 +02:00
|
|
|
* https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html
|
2011-10-28 20:28:03 +02:00
|
|
|
*/
|
2018-06-25 17:53:36 +02:00
|
|
|
movl $_program, %eax
|
2011-10-28 20:28:03 +02:00
|
|
|
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
|
2010-10-01 14:24:57 +02:00
|
|
|
orl $MTRR_TYPE_WRBACK, %eax
|
2010-04-09 22:36:29 +02:00
|
|
|
wrmsr
|
|
|
|
|
2015-10-01 05:23:09 +02:00
|
|
|
movl $MTRR_PHYS_MASK(1), %ecx
|
2010-10-01 01:15:36 +02:00
|
|
|
xorl %edx, %edx
|
2015-10-01 05:23:09 +02:00
|
|
|
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
|
2010-04-09 22:36:29 +02:00
|
|
|
wrmsr
|
|
|
|
|
2011-01-19 07:54:42 +01:00
|
|
|
/* Enable cache. */
|
|
|
|
movl %cr0, %eax
|
2012-03-31 12:52:21 +02:00
|
|
|
andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
|
2011-01-19 07:54:42 +01:00
|
|
|
movl %eax, %cr0
|
2010-04-09 22:36:29 +02:00
|
|
|
invd
|
|
|
|
|
|
|
|
__main:
|
2011-04-11 22:17:22 +02:00
|
|
|
post_code(POST_PREPARE_RAMSTAGE)
|
2010-10-01 01:15:36 +02:00
|
|
|
cld /* Clear direction flag. */
|
2010-04-27 08:56:47 +02:00
|
|
|
|
2014-10-16 11:47:25 +02:00
|
|
|
movl $CONFIG_RAMTOP, %esp
|
2010-04-09 22:36:29 +02:00
|
|
|
movl %esp, %ebp
|
2010-10-01 01:15:36 +02:00
|
|
|
call copy_and_run
|
2010-04-09 22:36:29 +02:00
|
|
|
|
2010-04-27 08:56:47 +02:00
|
|
|
.Lhlt:
|
2011-04-11 22:17:22 +02:00
|
|
|
post_code(POST_DEAD_CODE)
|
2010-04-09 22:36:29 +02:00
|
|
|
hlt
|
|
|
|
jmp .Lhlt
|