Update PSP binaries from version 0.11.0.68 to 0.11.E.75.
Update release notes.
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Built from cros branch firmware-guybrush-14500.B,
commit 9aa904cfd5ba587d20cbc82e8194aab6e72a56fb
(AmdCezannePkg: Add a HOB to retrieve/return CPPC values)
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Update the firmware version to 64.62.0
64.62.0
- [PMFW-9633] add gpio2 to s0i3 save/restore list based on rev ID
- [PMFW-9245] add gpio67 to s0i3 save/restore list based on rev ID
- [PMFW-9245] add rev ID check
- [PLAT-97359] Save and restore controllers value for Modern Standby
- [PMFW-9243] Broke AllCorePsm Adder
64.61.0
- DXIO v55.775
- PMFW Kernel v22
- [PMFW-8203] [OPT] DC BTC: PSMs not tracking aging
- [PMFW-8935] Change Makefile to include missing source files for Cezanne
tar.gz package
Signed-off-by: Jason Glenesk <jason.glenesk@amd.com>
Change-Id: I89e0c125be979ad16f5985c72ab12a0ef8c39036
The name change needs to correspond to a source change in coreboot.
Signed-off-by: Marshall Dawson <marshall.dawson@amd.com>
Change-Id: I40cb8b715702d56177e7ebd0e88a7c0022f91640
BUG=b:197216826
TEST=boot to ChromeOS and suspend with powerd_dbus_suspend 5 times each.
Cq-Depend: chrome-internal:4073788
Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Change-Id: I1fec10b1bcde4a2c92be9a783f53513d8654b3fc
Fix the release notes due to the intent for public consumption.
Signed-off-by: Marshall Dawson <marshall.dawson@amd.com>
Change-Id: Ic63e80ff1d89d4e9e5d2c0702eae3781d3c46b72
Cezanne generic Baseline VBIOS 018
1. WA for DCN block Pstate change @SMU when set mode
2. Update rlc_gpu_timer_refclk to correct SW delay timer
Cezanne generic Baseline VBIOS 017
1. Add display connector caps record for driver to tell if external DFPx
monitor set as "INTERNAL" display.
Signed-off-by: Marshall Dawson <marshall.dawson@amd.com>
Change-Id: Iabdc69267d7f2b01300625f53d9aca7037789150
Avoid a Secure OS Abort. This prevents coreboot timing out on C2P
mailbox commands and allows HDT unlocking.
Change-Id: I0196d0326b5931f8d99de874401ad31f07695a7c
Signed-off-by: Marshall Dawson <marshall.dawson@amd.com>
This is an initial release out of CezannePI-FP6 1.0.0.1 for
beginning development. Full coreboot compatibility will be
added in a subsequent update.
Signed-off-by: Marshall Dawson <marshall.dawson@amd.com>
Change-Id: I3bc8d10f33cdd439899f7ff7c9f8fb69e8096552
Matt DeVillier