mirror of https://review.coreboot.org/STM.git
enable 1G paging for test FRM.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
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@ -14,6 +14,31 @@
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#include <Base.h>
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#include "FrmInit.h"
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/**
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Check if 1-GByte pages is supported by processor or not.
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@retval TRUE 1-GByte pages is supported.
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@retval FALSE 1-GByte pages is not supported.
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**/
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BOOLEAN
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Is1GPageSupport (
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VOID
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)
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{
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UINT32 RegEax;
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UINT32 RegEdx;
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AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
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if (RegEax >= 0x80000001) {
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AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
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if ((RegEdx & BIT26) != 0) {
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return TRUE;
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}
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}
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return FALSE;
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}
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/**
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This function create >4G paging for X64 mode.
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@ -58,13 +83,21 @@ CreateAbove4GPaging (
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Pde = (UINT64 *)(UINTN)(Pml4[0] & 0xFFFFF000);
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Index = 4;
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}
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for (; Index < NumberOfPdpEntriesNeeded; Index++) {
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Pte = (UINT64 *)AllocatePages (1);
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Pde[Index] = (UINT64)(UINTN)Pte | IA32_PG_P;
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for (SubIndex = 0; SubIndex < SIZE_4KB / sizeof(*Pte); SubIndex++) {
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Pte[SubIndex] = BaseAddress | IA32_PG_PS | IA32_PG_RW | IA32_PG_P;
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BaseAddress += SIZE_2MB;
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if (Is1GPageSupport()) {
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for (; Index < NumberOfPdpEntriesNeeded; Index++) {
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Pde[Index] = (UINT64)(UINTN)BaseAddress | IA32_PG_PS | IA32_PG_RW | IA32_PG_P;
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BaseAddress += SIZE_1GB;
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}
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} else {
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for (; Index < NumberOfPdpEntriesNeeded; Index++) {
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Pte = (UINT64 *)AllocatePages (1);
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Pde[Index] = (UINT64)(UINTN)Pte | IA32_PG_P;
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for (SubIndex = 0; SubIndex < SIZE_4KB / sizeof(*Pte); SubIndex++) {
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Pte[SubIndex] = BaseAddress | IA32_PG_PS | IA32_PG_RW | IA32_PG_P;
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BaseAddress += SIZE_2MB;
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}
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}
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}
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}
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