563 lines
15 KiB
C
563 lines
15 KiB
C
/*
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* Copyright (c) 2015 Wind River Systems, Inc.
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* Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_CACHE_H_
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#define ZEPHYR_INCLUDE_CACHE_H_
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/**
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* @file
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* @brief cache API interface
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/debug/sparse.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(CONFIG_EXTERNAL_CACHE)
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#include <zephyr/drivers/cache.h>
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#elif defined(CONFIG_ARCH_CACHE)
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#include <zephyr/arch/cache.h>
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#endif
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/**
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* @defgroup cache_interface Cache Interface
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* @ingroup os_services
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* @{
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*/
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/**
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* @cond INTERNAL_HIDDEN
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*
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*/
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#define _CPU DT_PATH(cpus, cpu_0)
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/** @endcond */
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/**
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* @brief Enable the d-cache
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*
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* Enable the data cache
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*
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*/
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static ALWAYS_INLINE void sys_cache_data_enable(void)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
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cache_data_enable();
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#endif
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}
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/**
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* @brief Disable the d-cache
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*
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* Disable the data cache
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*
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*/
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static ALWAYS_INLINE void sys_cache_data_disable(void)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
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cache_data_disable();
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#endif
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}
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/**
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* @brief Enable the i-cache
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*
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* Enable the instruction cache
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*
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*/
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static ALWAYS_INLINE void sys_cache_instr_enable(void)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
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cache_instr_enable();
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#endif
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}
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/**
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* @brief Disable the i-cache
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*
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* Disable the instruction cache
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*
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*/
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static ALWAYS_INLINE void sys_cache_instr_disable(void)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
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cache_instr_disable();
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#endif
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}
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/**
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* @brief Flush the d-cache
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*
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* Flush the whole data cache.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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static ALWAYS_INLINE int sys_cache_data_flush_all(void)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
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return cache_data_flush_all();
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#endif
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return -ENOTSUP;
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}
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/**
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* @brief Flush the i-cache
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*
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* Flush the whole instruction cache.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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static ALWAYS_INLINE int sys_cache_instr_flush_all(void)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
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return cache_instr_flush_all();
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#endif
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return -ENOTSUP;
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}
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/**
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* @brief Invalidate the d-cache
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*
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* Invalidate the whole data cache.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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static ALWAYS_INLINE int sys_cache_data_invd_all(void)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
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return cache_data_invd_all();
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#endif
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return -ENOTSUP;
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}
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/**
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* @brief Invalidate the i-cache
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*
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* Invalidate the whole instruction cache.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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static ALWAYS_INLINE int sys_cache_instr_invd_all(void)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
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return cache_instr_invd_all();
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#endif
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return -ENOTSUP;
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}
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/**
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* @brief Flush and Invalidate the d-cache
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*
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* Flush and Invalidate the whole data cache.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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static ALWAYS_INLINE int sys_cache_data_flush_and_invd_all(void)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
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return cache_data_flush_and_invd_all();
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#endif
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return -ENOTSUP;
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}
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/**
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* @brief Flush and Invalidate the i-cache
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*
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* Flush and Invalidate the whole instruction cache.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_all(void)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
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return cache_instr_flush_and_invd_all();
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#endif
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return -ENOTSUP;
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}
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/**
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* @brief Flush an address range in the d-cache
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*
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* Flush the specified address range of the data cache.
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*
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* @note the cache operations act on cache line. When multiple data structures
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* share the same cache line being flushed, all the portions of the
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* data structures sharing the same line will be flushed. This is usually
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* not a problem because writing back is a non-destructive process that
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* could be triggered by hardware at any time, so having an aligned
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* @p addr or a padded @p size is not strictly necessary.
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*
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* @param addr Starting address to flush.
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* @param size Range size.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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__syscall_always_inline int sys_cache_data_flush_range(void *addr, size_t size);
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static ALWAYS_INLINE int z_impl_sys_cache_data_flush_range(void *addr, size_t size)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
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return cache_data_flush_range(addr, size);
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#endif
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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/**
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* @brief Flush an address range in the i-cache
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*
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* Flush the specified address range of the instruction cache.
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*
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* @note the cache operations act on cache line. When multiple data structures
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* share the same cache line being flushed, all the portions of the
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* data structures sharing the same line will be flushed. This is usually
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* not a problem because writing back is a non-destructive process that
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* could be triggered by hardware at any time, so having an aligned
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* @p addr or a padded @p size is not strictly necessary.
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*
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* @param addr Starting address to flush.
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* @param size Range size.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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static ALWAYS_INLINE int sys_cache_instr_flush_range(void *addr, size_t size)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
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return cache_instr_flush_range(addr, size);
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#endif
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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/**
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* @brief Invalidate an address range in the d-cache
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*
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* Invalidate the specified address range of the data cache.
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*
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* @note the cache operations act on cache line. When multiple data structures
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* share the same cache line being invalidated, all the portions of the
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* non-read-only data structures sharing the same line will be
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* invalidated as well. This is a destructive process that could lead to
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* data loss and/or corruption. When @p addr is not aligned to the cache
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* line and/or @p size is not a multiple of the cache line size the
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* behaviour is undefined.
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*
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* @param addr Starting address to invalidate.
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* @param size Range size.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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__syscall_always_inline int sys_cache_data_invd_range(void *addr, size_t size);
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static ALWAYS_INLINE int z_impl_sys_cache_data_invd_range(void *addr, size_t size)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
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return cache_data_invd_range(addr, size);
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#endif
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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/**
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* @brief Invalidate an address range in the i-cache
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*
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* Invalidate the specified address range of the instruction cache.
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*
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* @note the cache operations act on cache line. When multiple data structures
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* share the same cache line being invalidated, all the portions of the
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* non-read-only data structures sharing the same line will be
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* invalidated as well. This is a destructive process that could lead to
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* data loss and/or corruption. When @p addr is not aligned to the cache
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* line and/or @p size is not a multiple of the cache line size the
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* behaviour is undefined.
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*
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* @param addr Starting address to invalidate.
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* @param size Range size.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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static ALWAYS_INLINE int sys_cache_instr_invd_range(void *addr, size_t size)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
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return cache_instr_invd_range(addr, size);
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#endif
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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/**
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* @brief Flush and Invalidate an address range in the d-cache
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*
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* Flush and Invalidate the specified address range of the data cache.
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*
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* @note the cache operations act on cache line. When multiple data structures
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* share the same cache line being flushed, all the portions of the
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* data structures sharing the same line will be flushed before being
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* invalidated. This is usually not a problem because writing back is a
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* non-destructive process that could be triggered by hardware at any
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* time, so having an aligned @p addr or a padded @p size is not strictly
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* necessary.
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*
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* @param addr Starting address to flush and invalidate.
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* @param size Range size.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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__syscall_always_inline int sys_cache_data_flush_and_invd_range(void *addr, size_t size);
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static ALWAYS_INLINE int z_impl_sys_cache_data_flush_and_invd_range(void *addr, size_t size)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
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return cache_data_flush_and_invd_range(addr, size);
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#endif
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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/**
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* @brief Flush and Invalidate an address range in the i-cache
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*
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* Flush and Invalidate the specified address range of the instruction cache.
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*
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* @note the cache operations act on cache line. When multiple data structures
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* share the same cache line being flushed, all the portions of the
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* data structures sharing the same line will be flushed before being
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* invalidated. This is usually not a problem because writing back is a
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* non-destructive process that could be triggered by hardware at any
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* time, so having an aligned @p addr or a padded @p size is not strictly
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* necessary.
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*
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* @param addr Starting address to flush and invalidate.
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* @param size Range size.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_range(void *addr, size_t size)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
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return cache_instr_flush_and_invd_range(addr, size);
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#endif
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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/**
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*
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* @brief Get the the d-cache line size.
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*
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* The API is provided to get the data cache line.
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*
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* The cache line size is calculated (in order of priority):
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*
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* - At run-time when @kconfig{CONFIG_DCACHE_LINE_SIZE_DETECT} is set.
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* - At compile time using the value set in @kconfig{CONFIG_DCACHE_LINE_SIZE}.
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* - At compile time using the `d-cache-line-size` CPU0 property of the DT.
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* - 0 otherwise
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*
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* @retval size Size of the d-cache line.
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* @retval 0 If the d-cache is not enabled.
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*/
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static ALWAYS_INLINE size_t sys_cache_data_line_size_get(void)
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{
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#ifdef CONFIG_DCACHE_LINE_SIZE_DETECT
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return cache_data_line_size_get();
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#elif (CONFIG_DCACHE_LINE_SIZE != 0)
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return CONFIG_DCACHE_LINE_SIZE;
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#else
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return DT_PROP_OR(_CPU, d_cache_line_size, 0);
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#endif
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}
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/**
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*
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* @brief Get the the i-cache line size.
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*
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* The API is provided to get the instruction cache line.
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*
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* The cache line size is calculated (in order of priority):
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*
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* - At run-time when @kconfig{CONFIG_ICACHE_LINE_SIZE_DETECT} is set.
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* - At compile time using the value set in @kconfig{CONFIG_ICACHE_LINE_SIZE}.
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* - At compile time using the `i-cache-line-size` CPU0 property of the DT.
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* - 0 otherwise
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*
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* @retval size Size of the d-cache line.
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* @retval 0 If the d-cache is not enabled.
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*/
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static ALWAYS_INLINE size_t sys_cache_instr_line_size_get(void)
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{
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#ifdef CONFIG_ICACHE_LINE_SIZE_DETECT
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return cache_instr_line_size_get();
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#elif (CONFIG_ICACHE_LINE_SIZE != 0)
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return CONFIG_ICACHE_LINE_SIZE;
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#else
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return DT_PROP_OR(_CPU, i_cache_line_size, 0);
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#endif
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}
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/**
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* @brief Test if a pointer is in cached region.
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*
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* Some hardware may map the same physical memory twice
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* so that it can be seen in both (incoherent) cached mappings
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* and a coherent "shared" area. This tests if a particular
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* pointer is within the cached, coherent area.
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*
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* @param ptr Pointer
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*
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* @retval True if pointer is in cached region.
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* @retval False if pointer is not in cached region.
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*/
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static ALWAYS_INLINE bool sys_cache_is_ptr_cached(void *ptr)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_CACHE_DOUBLEMAP)
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return cache_is_ptr_cached(ptr);
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#else
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ARG_UNUSED(ptr);
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return false;
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#endif
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}
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/**
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* @brief Test if a pointer is in un-cached region.
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*
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* Some hardware may map the same physical memory twice
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* so that it can be seen in both (incoherent) cached mappings
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* and a coherent "shared" area. This tests if a particular
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* pointer is within the un-cached, incoherent area.
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*
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* @param ptr Pointer
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*
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* @retval True if pointer is not in cached region.
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* @retval False if pointer is in cached region.
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*/
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static ALWAYS_INLINE bool sys_cache_is_ptr_uncached(void *ptr)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_CACHE_DOUBLEMAP)
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return cache_is_ptr_uncached(ptr);
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#else
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ARG_UNUSED(ptr);
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return false;
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#endif
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}
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/**
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* @brief Return cached pointer to a RAM address
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*
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* This function takes a pointer to any addressable object (either in
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* cacheable memory or not) and returns a pointer that can be used to
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* refer to the same memory through the L1 data cache. Data read
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* through the resulting pointer will reflect locally cached values on
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* the current CPU if they exist, and writes will go first into the
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* cache and be written back later.
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*
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* @note This API returns the same pointer if CONFIG_CACHE_DOUBLEMAP is not
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* enabled.
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*
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* @see arch_uncached_ptr()
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*
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* @param ptr A pointer to a valid C object
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* @return A pointer to the same object via the L1 dcache
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*/
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static ALWAYS_INLINE void __sparse_cache *sys_cache_cached_ptr_get(void *ptr)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_CACHE_DOUBLEMAP)
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return cache_cached_ptr(ptr);
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#else
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return (__sparse_force void __sparse_cache *)ptr;
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#endif
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}
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/**
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* @brief Return uncached pointer to a RAM address
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*
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* This function takes a pointer to any addressable object (either in
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* cacheable memory or not) and returns a pointer that can be used to
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* refer to the same memory while bypassing the L1 data cache. Data
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* in the L1 cache will not be inspected nor modified by the access.
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*
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* @note This API returns the same pointer if CONFIG_CACHE_DOUBLEMAP is not
|
|
* enabled.
|
|
*
|
|
* @see arch_cached_ptr()
|
|
*
|
|
* @param ptr A pointer to a valid C object
|
|
* @return A pointer to the same object bypassing the L1 dcache
|
|
*/
|
|
static ALWAYS_INLINE void *sys_cache_uncached_ptr_get(void __sparse_cache *ptr)
|
|
{
|
|
#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_CACHE_DOUBLEMAP)
|
|
return cache_uncached_ptr(ptr);
|
|
#else
|
|
return (__sparse_force void *)ptr;
|
|
#endif
|
|
}
|
|
|
|
|
|
#ifdef CONFIG_LIBMETAL
|
|
static ALWAYS_INLINE void sys_cache_flush(void *addr, size_t size)
|
|
{
|
|
sys_cache_data_flush_range(addr, size);
|
|
}
|
|
#endif
|
|
|
|
#include <syscalls/cache.h>
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* ZEPHYR_INCLUDE_CACHE_H_ */
|