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arch: arm: core: aarch32: Use cmsis functions 

These functions help the code to be more self-documenting.  Use them to
make the code's intent clearer.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
This commit is contained in:
Bradley Bolen 2021-12-22 20:11:21 -05:00 committed by Anas Nashif
parent 4704f598b8
commit 643084de0b
2 changed files with 12 additions and 12 deletions
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20
arch/arm/core/aarch32/mpu/arm_mpu.c
View File

@ -146,12 +146,12 @@ void arm_core_mpu_enable(void)
{
uint32_t val;
__asm__ volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val) ::);
val |= SCTRL_MPU_ENABLE;
val = __get_SCTLR();
val |= SCTLR_MPU_ENABLE;
/* Make sure that all the registers are set before proceeding */
__asm__ volatile ("dsb");
__asm__ volatile ("mcr p15, 0, %0, c1, c0, 0" :: "r" (val) :);
__asm__ volatile ("isb");
__DSB();
__set_SCTLR(val);
__ISB();
}
/**
@ -161,12 +161,12 @@ void arm_core_mpu_disable(void)
{
uint32_t val;
__asm__ volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val) ::);
val &= ~SCTRL_MPU_ENABLE;
val = __get_SCTLR();
val &= ~SCTLR_MPU_ENABLE;
/* Force any outstanding transfers to complete before disabling MPU */
__asm__ volatile ("dsb");
__asm__ volatile ("mcr p15, 0, %0, c1, c0, 0" :: "r" (val) :);
__asm__ volatile ("isb");
__DSB();
__set_SCTLR(val);
__ISB();
}
#else
/**

4
include/arch/arm/aarch32/cortex_a_r/cpu.h
View File

@ -12,9 +12,9 @@
#endif
/*
* SCTRL register bit assignments
* SCTLR register bit assignments
*/
#define SCTRL_MPU_ENABLE (1 << 0)
#define SCTLR_MPU_ENABLE (1 << 0)
#define MODE_USR 0x10
#define MODE_FIQ 0x11