xtensa: add intel_tgl_adsp
This adds the config and overlay to build the toolchain for the audio DSP on Intel Tiger Lake SoC, which is used by the intel_adsp_cavs25 board in Zephyr main. The overlay archive is from branch sof-gcc10.2, commit 726dd0c8786c2e41c109b3d4bc3ce8edfd6e1b6b at https://github.com/thesofproject/xtensa-overlay, file xtensa_lx7hifi4.tar.gz. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung
Stephanos Ioannidis
parent
de76a4a218
commit
9c9fb89a01
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@ -55,6 +55,7 @@ on:
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- xtensa-espressif_esp32s3_zephyr-elf
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- xtensa-intel_ace15_mtpm_zephyr-elf
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- xtensa-intel_s1000_zephyr-elf
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- xtensa-intel_tgl_adsp_zephyr-elf
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- xtensa-nxp_imx_adsp_zephyr-elf
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- xtensa-nxp_imx8m_adsp_zephyr-elf
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- xtensa-sample_controller_zephyr-elf
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@ -163,6 +164,7 @@ jobs:
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xtensa-espressif_esp32s3_zephyr-elf) build_target_xtensa_espressif_esp32s3_zephyr_elf="y";;
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xtensa-intel_ace15_mtpm_zephyr-elf) build_target_xtensa_intel_ace15_mtpm_zephyr_elf="y";;
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xtensa-intel_s1000_zephyr-elf) build_target_xtensa_intel_s1000_zephyr_elf="y";;
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xtensa-intel_tgl_adsp_zephyr-elf) build_target_xtensa_intel_tgl_adsp_zephyr_elf="y";;
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xtensa-nxp_imx_adsp_zephyr-elf) build_target_xtensa_nxp_imx_adsp_zephyr_elf="y";;
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xtensa-nxp_imx8m_adsp_zephyr-elf) build_target_xtensa_nxp_imx8m_adsp_zephyr_elf="y";;
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xtensa-sample_controller_zephyr-elf) build_target_xtensa_sample_controller_zephyr_elf="y";;
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@ -199,6 +201,7 @@ jobs:
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build_target_xtensa_espressif_esp32s3_zephyr_elf="y"
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build_target_xtensa_intel_ace15_mtpm_zephyr_elf="y"
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build_target_xtensa_intel_s1000_zephyr_elf="y"
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build_target_xtensa_intel_tgl_adsp_zephyr_elf="y"
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build_target_xtensa_nxp_imx_adsp_zephyr_elf="y"
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build_target_xtensa_nxp_imx8m_adsp_zephyr_elf="y"
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build_target_xtensa_sample_controller_zephyr_elf="y"
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@ -275,6 +278,7 @@ jobs:
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[ "${build_target_xtensa_espressif_esp32s3_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-espressif_esp32s3_zephyr-elf",'
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[ "${build_target_xtensa_intel_ace15_mtpm_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-intel_ace15_mtpm_zephyr-elf",'
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[ "${build_target_xtensa_intel_s1000_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-intel_s1000_zephyr-elf",'
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[ "${build_target_xtensa_intel_tgl_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-intel_tgl_adsp_zephyr-elf",'
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[ "${build_target_xtensa_nxp_imx_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-nxp_imx_adsp_zephyr-elf",'
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[ "${build_target_xtensa_nxp_imx8m_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-nxp_imx8m_adsp_zephyr-elf",'
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[ "${build_target_xtensa_sample_controller_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-sample_controller_zephyr-elf",'
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@ -1534,6 +1538,9 @@ jobs:
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# board that uses this toolchain.
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# PLATFORM_ARGS+="-p intel_adsp_cavs18 "
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;;
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xtensa-intel_tgl_adsp_zephyr-elf)
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PLATFORM_ARGS+="-p intel_adsp_cavs25 "
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;;
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xtensa-nxp_imx_adsp_zephyr-elf)
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PLATFORM_ARGS+="-p nxp_adsp_imx8 "
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;;
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@ -0,0 +1,10 @@
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CT_CONFIG_VERSION="3"
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CT_EXPERIMENTAL=y
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CT_OVERLAY_LOCATION="overlays"
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CT_OVERLAY_NAME="intel_tgl_adsp"
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CT_ARCH_XTENSA=y
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CT_XTENSA_CUSTOM=y
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CT_TARGET_VENDOR="intel_tgl_adsp_zephyr"
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CT_TARGET_CFLAGS="-ftls-model=local-exec"
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CT_CC_GCC_CONFIG_TLS=n
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CT_GDB_CROSS_EXTRA_CONFIG_ARRAY="--enable-xtensa-use-target-regnum --disable-xtensa-remote-g-packet"
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,189 @@
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/* Xtensa configuration settings.
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Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
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Free Software Foundation, Inc.
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Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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#ifndef XTENSA_CONFIG_H
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#define XTENSA_CONFIG_H
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/* The macros defined here match those with the same names in the Xtensa
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compile-time HAL (Hardware Abstraction Layer). Please refer to the
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Xtensa System Software Reference Manual for documentation of these
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macros. */
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#undef XCHAL_HAVE_BE
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#define XCHAL_HAVE_BE 0
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#undef XCHAL_HAVE_DENSITY
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#define XCHAL_HAVE_DENSITY 1
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#undef XCHAL_HAVE_CONST16
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#define XCHAL_HAVE_CONST16 0
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#undef XCHAL_HAVE_ABS
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#define XCHAL_HAVE_ABS 1
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#undef XCHAL_HAVE_ADDX
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#define XCHAL_HAVE_ADDX 1
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#undef XCHAL_HAVE_L32R
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#define XCHAL_HAVE_L32R 1
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#undef XSHAL_USE_ABSOLUTE_LITERALS
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#define XSHAL_USE_ABSOLUTE_LITERALS 0
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#undef XSHAL_HAVE_TEXT_SECTION_LITERALS
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#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
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#undef XCHAL_HAVE_MAC16
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#define XCHAL_HAVE_MAC16 0
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#undef XCHAL_HAVE_MUL16
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#define XCHAL_HAVE_MUL16 1
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#undef XCHAL_HAVE_MUL32
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#define XCHAL_HAVE_MUL32 1
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#undef XCHAL_HAVE_MUL32_HIGH
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#define XCHAL_HAVE_MUL32_HIGH 1
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#undef XCHAL_HAVE_DIV32
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#define XCHAL_HAVE_DIV32 1
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#undef XCHAL_HAVE_NSA
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#define XCHAL_HAVE_NSA 1
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#undef XCHAL_HAVE_MINMAX
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#define XCHAL_HAVE_MINMAX 1
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#undef XCHAL_HAVE_SEXT
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#define XCHAL_HAVE_SEXT 1
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#undef XCHAL_HAVE_LOOPS
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#define XCHAL_HAVE_LOOPS 1
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#undef XCHAL_HAVE_THREADPTR
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#define XCHAL_HAVE_THREADPTR 1
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#undef XCHAL_HAVE_RELEASE_SYNC
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#define XCHAL_HAVE_RELEASE_SYNC 1
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#undef XCHAL_HAVE_S32C1I
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#define XCHAL_HAVE_S32C1I 1
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#undef XCHAL_HAVE_BOOLEANS
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#define XCHAL_HAVE_BOOLEANS 1
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#undef XCHAL_HAVE_FP
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#define XCHAL_HAVE_FP 0
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#undef XCHAL_HAVE_FP_DIV
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#define XCHAL_HAVE_FP_DIV 0
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#undef XCHAL_HAVE_FP_RECIP
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#define XCHAL_HAVE_FP_RECIP 0
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#undef XCHAL_HAVE_FP_SQRT
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#define XCHAL_HAVE_FP_SQRT 0
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#undef XCHAL_HAVE_FP_RSQRT
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#define XCHAL_HAVE_FP_RSQRT 0
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#undef XCHAL_HAVE_DFP_ACCEL
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#define XCHAL_HAVE_DFP_ACCEL 0
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/* For backward compatibility */
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#undef XCHAL_HAVE_DFP_accel
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#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL
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#undef XCHAL_HAVE_WINDOWED
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#define XCHAL_HAVE_WINDOWED 1
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#undef XCHAL_NUM_AREGS
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#define XCHAL_NUM_AREGS 64
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#undef XCHAL_HAVE_WIDE_BRANCHES
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#define XCHAL_HAVE_WIDE_BRANCHES 0
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#undef XCHAL_HAVE_PREDICTED_BRANCHES
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#define XCHAL_HAVE_PREDICTED_BRANCHES 0
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#undef XCHAL_ICACHE_SIZE
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#define XCHAL_ICACHE_SIZE 16384
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#undef XCHAL_DCACHE_SIZE
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#define XCHAL_DCACHE_SIZE 49152
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#undef XCHAL_ICACHE_LINESIZE
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#define XCHAL_ICACHE_LINESIZE 64
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#undef XCHAL_DCACHE_LINESIZE
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#define XCHAL_DCACHE_LINESIZE 64
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#undef XCHAL_ICACHE_LINEWIDTH
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#define XCHAL_ICACHE_LINEWIDTH 6
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#undef XCHAL_DCACHE_LINEWIDTH
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#define XCHAL_DCACHE_LINEWIDTH 6
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#undef XCHAL_DCACHE_IS_WRITEBACK
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#define XCHAL_DCACHE_IS_WRITEBACK 1
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#undef XCHAL_HAVE_MMU
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#define XCHAL_HAVE_MMU 0
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#undef XCHAL_HAVE_DEBUG
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#define XCHAL_HAVE_DEBUG 1
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#undef XCHAL_NUM_IBREAK
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#define XCHAL_NUM_IBREAK 2
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#undef XCHAL_NUM_DBREAK
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#define XCHAL_NUM_DBREAK 2
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#undef XCHAL_DEBUGLEVEL
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#define XCHAL_DEBUGLEVEL 6
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#undef XCHAL_MAX_INSTRUCTION_SIZE
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#define XCHAL_MAX_INSTRUCTION_SIZE 8
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#undef XCHAL_INST_FETCH_WIDTH
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#define XCHAL_INST_FETCH_WIDTH 8
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#undef XSHAL_ABI
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#undef XTHAL_ABI_WINDOWED
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#undef XTHAL_ABI_CALL0
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#define XSHAL_ABI XTHAL_ABI_WINDOWED
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#define XTHAL_ABI_WINDOWED 0
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#define XTHAL_ABI_CALL0 1
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#undef XCHAL_M_STAGE
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#define XCHAL_M_STAGE 3
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#undef XTENSA_MARCH_LATEST
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#define XTENSA_MARCH_LATEST 260003
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#undef XTENSA_MARCH_EARLIEST
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#define XTENSA_MARCH_EARLIEST 260003
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#endif /* !XTENSA_CONFIG_H */
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@ -0,0 +1,189 @@
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/* Xtensa configuration settings.
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Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
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Free Software Foundation, Inc.
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Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
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General Public License for more details.
|
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|
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You should have received a copy of the GNU General Public License
|
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along with this program; if not, write to the Free Software
|
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Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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#ifndef XTENSA_CONFIG_H
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#define XTENSA_CONFIG_H
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/* The macros defined here match those with the same names in the Xtensa
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compile-time HAL (Hardware Abstraction Layer). Please refer to the
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Xtensa System Software Reference Manual for documentation of these
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macros. */
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#undef XCHAL_HAVE_BE
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#define XCHAL_HAVE_BE 0
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#undef XCHAL_HAVE_DENSITY
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#define XCHAL_HAVE_DENSITY 1
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#undef XCHAL_HAVE_CONST16
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#define XCHAL_HAVE_CONST16 0
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#undef XCHAL_HAVE_ABS
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#define XCHAL_HAVE_ABS 1
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#undef XCHAL_HAVE_ADDX
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#define XCHAL_HAVE_ADDX 1
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#undef XCHAL_HAVE_L32R
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#define XCHAL_HAVE_L32R 1
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#undef XSHAL_USE_ABSOLUTE_LITERALS
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#define XSHAL_USE_ABSOLUTE_LITERALS 0
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#undef XSHAL_HAVE_TEXT_SECTION_LITERALS
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#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
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#undef XCHAL_HAVE_MAC16
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#define XCHAL_HAVE_MAC16 0
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#undef XCHAL_HAVE_MUL16
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#define XCHAL_HAVE_MUL16 1
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#undef XCHAL_HAVE_MUL32
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#define XCHAL_HAVE_MUL32 1
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#undef XCHAL_HAVE_MUL32_HIGH
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#define XCHAL_HAVE_MUL32_HIGH 1
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#undef XCHAL_HAVE_DIV32
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#define XCHAL_HAVE_DIV32 1
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#undef XCHAL_HAVE_NSA
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#define XCHAL_HAVE_NSA 1
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#undef XCHAL_HAVE_MINMAX
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#define XCHAL_HAVE_MINMAX 1
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#undef XCHAL_HAVE_SEXT
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#define XCHAL_HAVE_SEXT 1
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#undef XCHAL_HAVE_LOOPS
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#define XCHAL_HAVE_LOOPS 1
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#undef XCHAL_HAVE_THREADPTR
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#define XCHAL_HAVE_THREADPTR 1
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#undef XCHAL_HAVE_RELEASE_SYNC
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#define XCHAL_HAVE_RELEASE_SYNC 1
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#undef XCHAL_HAVE_S32C1I
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#define XCHAL_HAVE_S32C1I 1
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#undef XCHAL_HAVE_BOOLEANS
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#define XCHAL_HAVE_BOOLEANS 1
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#undef XCHAL_HAVE_FP
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#define XCHAL_HAVE_FP 0
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#undef XCHAL_HAVE_FP_DIV
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#define XCHAL_HAVE_FP_DIV 0
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#undef XCHAL_HAVE_FP_RECIP
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#define XCHAL_HAVE_FP_RECIP 0
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#undef XCHAL_HAVE_FP_SQRT
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#define XCHAL_HAVE_FP_SQRT 0
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#undef XCHAL_HAVE_FP_RSQRT
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#define XCHAL_HAVE_FP_RSQRT 0
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#undef XCHAL_HAVE_DFP_ACCEL
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#define XCHAL_HAVE_DFP_ACCEL 0
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/* For backward compatibility */
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#undef XCHAL_HAVE_DFP_accel
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#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL
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#undef XCHAL_HAVE_WINDOWED
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#define XCHAL_HAVE_WINDOWED 1
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#undef XCHAL_NUM_AREGS
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#define XCHAL_NUM_AREGS 64
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#undef XCHAL_HAVE_WIDE_BRANCHES
|
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#define XCHAL_HAVE_WIDE_BRANCHES 0
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#undef XCHAL_HAVE_PREDICTED_BRANCHES
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#define XCHAL_HAVE_PREDICTED_BRANCHES 0
|
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|
||||
|
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#undef XCHAL_ICACHE_SIZE
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#define XCHAL_ICACHE_SIZE 16384
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#undef XCHAL_DCACHE_SIZE
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#define XCHAL_DCACHE_SIZE 49152
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|
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#undef XCHAL_ICACHE_LINESIZE
|
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#define XCHAL_ICACHE_LINESIZE 64
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|
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#undef XCHAL_DCACHE_LINESIZE
|
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#define XCHAL_DCACHE_LINESIZE 64
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|
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#undef XCHAL_ICACHE_LINEWIDTH
|
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#define XCHAL_ICACHE_LINEWIDTH 6
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#undef XCHAL_DCACHE_LINEWIDTH
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#define XCHAL_DCACHE_LINEWIDTH 6
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|
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#undef XCHAL_DCACHE_IS_WRITEBACK
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#define XCHAL_DCACHE_IS_WRITEBACK 1
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|
||||
|
||||
#undef XCHAL_HAVE_MMU
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#define XCHAL_HAVE_MMU 0
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||||
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#undef XCHAL_HAVE_DEBUG
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#define XCHAL_HAVE_DEBUG 1
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#undef XCHAL_NUM_IBREAK
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#define XCHAL_NUM_IBREAK 2
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|
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#undef XCHAL_NUM_DBREAK
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#define XCHAL_NUM_DBREAK 2
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#undef XCHAL_DEBUGLEVEL
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#define XCHAL_DEBUGLEVEL 6
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#undef XCHAL_MAX_INSTRUCTION_SIZE
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#define XCHAL_MAX_INSTRUCTION_SIZE 8
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|
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#undef XCHAL_INST_FETCH_WIDTH
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#define XCHAL_INST_FETCH_WIDTH 8
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#undef XSHAL_ABI
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#undef XTHAL_ABI_WINDOWED
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#undef XTHAL_ABI_CALL0
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#define XSHAL_ABI XTHAL_ABI_WINDOWED
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#define XTHAL_ABI_WINDOWED 0
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#define XTHAL_ABI_CALL0 1
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|
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#undef XCHAL_M_STAGE
|
||||
#define XCHAL_M_STAGE 3
|
||||
|
||||
#undef XTENSA_MARCH_LATEST
|
||||
#define XTENSA_MARCH_LATEST 260003
|
||||
|
||||
#undef XTENSA_MARCH_EARLIEST
|
||||
#define XTENSA_MARCH_EARLIEST 260003
|
||||
|
||||
|
||||
#endif /* !XTENSA_CONFIG_H */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,124 @@
|
|||
name:xtensa
|
||||
expedite:pc,windowbase,windowstart
|
||||
32:pc
|
||||
32:ar0
|
||||
32:ar1
|
||||
32:ar2
|
||||
32:ar3
|
||||
32:ar4
|
||||
32:ar5
|
||||
32:ar6
|
||||
32:ar7
|
||||
32:ar8
|
||||
32:ar9
|
||||
32:ar10
|
||||
32:ar11
|
||||
32:ar12
|
||||
32:ar13
|
||||
32:ar14
|
||||
32:ar15
|
||||
32:ar16
|
||||
32:ar17
|
||||
32:ar18
|
||||
32:ar19
|
||||
32:ar20
|
||||
32:ar21
|
||||
32:ar22
|
||||
32:ar23
|
||||
32:ar24
|
||||
32:ar25
|
||||
32:ar26
|
||||
32:ar27
|
||||
32:ar28
|
||||
32:ar29
|
||||
32:ar30
|
||||
32:ar31
|
||||
32:ar32
|
||||
32:ar33
|
||||
32:ar34
|
||||
32:ar35
|
||||
32:ar36
|
||||
32:ar37
|
||||
32:ar38
|
||||
32:ar39
|
||||
32:ar40
|
||||
32:ar41
|
||||
32:ar42
|
||||
32:ar43
|
||||
32:ar44
|
||||
32:ar45
|
||||
32:ar46
|
||||
32:ar47
|
||||
32:ar48
|
||||
32:ar49
|
||||
32:ar50
|
||||
32:ar51
|
||||
32:ar52
|
||||
32:ar53
|
||||
32:ar54
|
||||
32:ar55
|
||||
32:ar56
|
||||
32:ar57
|
||||
32:ar58
|
||||
32:ar59
|
||||
32:ar60
|
||||
32:ar61
|
||||
32:ar62
|
||||
32:ar63
|
||||
32:lbeg
|
||||
32:lend
|
||||
32:lcount
|
||||
32:sar
|
||||
32:prefctl
|
||||
32:windowbase
|
||||
32:windowstart
|
||||
32:configid0
|
||||
32:configid1
|
||||
32:ps
|
||||
32:threadptr
|
||||
32:br
|
||||
32:scompare1
|
||||
32:f0
|
||||
32:f1
|
||||
32:f2
|
||||
32:f3
|
||||
32:f4
|
||||
32:f5
|
||||
32:f6
|
||||
32:f7
|
||||
32:f8
|
||||
32:f9
|
||||
32:f10
|
||||
32:f11
|
||||
32:f12
|
||||
32:f13
|
||||
32:f14
|
||||
32:f15
|
||||
32:fcr
|
||||
32:fsr
|
||||
32:ae_ovf_sar
|
||||
32:ae_bithead
|
||||
32:ae_ts_fts_bu_bp
|
||||
32:ae_cw_sd_no
|
||||
32:ae_cbegin0
|
||||
32:ae_cend0
|
||||
64:aed0
|
||||
64:aed1
|
||||
64:aed2
|
||||
64:aed3
|
||||
64:aed4
|
||||
64:aed5
|
||||
64:aed6
|
||||
64:aed7
|
||||
64:aed8
|
||||
64:aed9
|
||||
64:aed10
|
||||
64:aed11
|
||||
64:aed12
|
||||
64:aed13
|
||||
64:aed14
|
||||
64:aed15
|
||||
64:u0
|
||||
64:u1
|
||||
64:u2
|
||||
64:u3
|
||||
|
|
@ -0,0 +1,514 @@
|
|||
/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
|
||||
|
||||
Copyright (c) 2003-2019 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#define XTENSA_CONFIG_VERSION 0x60
|
||||
|
||||
#include "defs.h"
|
||||
#include "xtensa-config.h"
|
||||
#include "xtensa-tdep.h"
|
||||
|
||||
|
||||
|
||||
/* Masked registers. */
|
||||
xtensa_reg_mask_t xtensa_submask0[] = { { 76, 0, 1 } };
|
||||
const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 };
|
||||
xtensa_reg_mask_t xtensa_submask1[] = { { 76, 1, 1 } };
|
||||
const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 };
|
||||
xtensa_reg_mask_t xtensa_submask2[] = { { 76, 2, 1 } };
|
||||
const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 };
|
||||
xtensa_reg_mask_t xtensa_submask3[] = { { 76, 3, 1 } };
|
||||
const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 };
|
||||
xtensa_reg_mask_t xtensa_submask4[] = { { 76, 4, 1 } };
|
||||
const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 };
|
||||
xtensa_reg_mask_t xtensa_submask5[] = { { 76, 5, 1 } };
|
||||
const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 };
|
||||
xtensa_reg_mask_t xtensa_submask6[] = { { 76, 6, 1 } };
|
||||
const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 };
|
||||
xtensa_reg_mask_t xtensa_submask7[] = { { 76, 7, 1 } };
|
||||
const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 };
|
||||
xtensa_reg_mask_t xtensa_submask8[] = { { 76, 8, 1 } };
|
||||
const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 };
|
||||
xtensa_reg_mask_t xtensa_submask9[] = { { 76, 9, 1 } };
|
||||
const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 };
|
||||
xtensa_reg_mask_t xtensa_submask10[] = { { 76, 10, 1 } };
|
||||
const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 };
|
||||
xtensa_reg_mask_t xtensa_submask11[] = { { 76, 11, 1 } };
|
||||
const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 };
|
||||
xtensa_reg_mask_t xtensa_submask12[] = { { 76, 12, 1 } };
|
||||
const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 };
|
||||
xtensa_reg_mask_t xtensa_submask13[] = { { 76, 13, 1 } };
|
||||
const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 };
|
||||
xtensa_reg_mask_t xtensa_submask14[] = { { 76, 14, 1 } };
|
||||
const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 };
|
||||
xtensa_reg_mask_t xtensa_submask15[] = { { 76, 15, 1 } };
|
||||
const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 };
|
||||
xtensa_reg_mask_t xtensa_submask16[] = { { 74, 0, 4 } };
|
||||
const xtensa_mask_t xtensa_mask16 = { 1, xtensa_submask16 };
|
||||
xtensa_reg_mask_t xtensa_submask17[] = { { 74, 5, 1 } };
|
||||
const xtensa_mask_t xtensa_mask17 = { 1, xtensa_submask17 };
|
||||
xtensa_reg_mask_t xtensa_submask18[] = { { 74, 18, 1 } };
|
||||
const xtensa_mask_t xtensa_mask18 = { 1, xtensa_submask18 };
|
||||
xtensa_reg_mask_t xtensa_submask19[] = { { 74, 4, 1 } };
|
||||
const xtensa_mask_t xtensa_mask19 = { 1, xtensa_submask19 };
|
||||
xtensa_reg_mask_t xtensa_submask20[] = { { 74, 16, 2 } };
|
||||
const xtensa_mask_t xtensa_mask20 = { 1, xtensa_submask20 };
|
||||
xtensa_reg_mask_t xtensa_submask21[] = { { 74, 8, 4 } };
|
||||
const xtensa_mask_t xtensa_mask21 = { 1, xtensa_submask21 };
|
||||
xtensa_reg_mask_t xtensa_submask22[] = { { 130, 8, 1 } };
|
||||
const xtensa_mask_t xtensa_mask22 = { 1, xtensa_submask22 };
|
||||
xtensa_reg_mask_t xtensa_submask23[] = { { 130, 9, 1 } };
|
||||
const xtensa_mask_t xtensa_mask23 = { 1, xtensa_submask23 };
|
||||
xtensa_reg_mask_t xtensa_submask24[] = { { 130, 0, 1 } };
|
||||
const xtensa_mask_t xtensa_mask24 = { 1, xtensa_submask24 };
|
||||
xtensa_reg_mask_t xtensa_submask25[] = { { 130, 1, 1 } };
|
||||
const xtensa_mask_t xtensa_mask25 = { 1, xtensa_submask25 };
|
||||
xtensa_reg_mask_t xtensa_submask26[] = { { 130, 24, 4 } };
|
||||
const xtensa_mask_t xtensa_mask26 = { 1, xtensa_submask26 };
|
||||
xtensa_reg_mask_t xtensa_submask27[] = { { 130, 20, 2 } };
|
||||
const xtensa_mask_t xtensa_mask27 = { 1, xtensa_submask27 };
|
||||
xtensa_reg_mask_t xtensa_submask28[] = { { 130, 30, 2 } };
|
||||
const xtensa_mask_t xtensa_mask28 = { 1, xtensa_submask28 };
|
||||
xtensa_reg_mask_t xtensa_submask29[] = { { 130, 16, 2 } };
|
||||
const xtensa_mask_t xtensa_mask29 = { 1, xtensa_submask29 };
|
||||
xtensa_reg_mask_t xtensa_submask30[] = { { 130, 10, 1 } };
|
||||
const xtensa_mask_t xtensa_mask30 = { 1, xtensa_submask30 };
|
||||
xtensa_reg_mask_t xtensa_submask31[] = { { 130, 11, 1 } };
|
||||
const xtensa_mask_t xtensa_mask31 = { 1, xtensa_submask31 };
|
||||
xtensa_reg_mask_t xtensa_submask32[] = { { 130, 4, 1 } };
|
||||
const xtensa_mask_t xtensa_mask32 = { 1, xtensa_submask32 };
|
||||
xtensa_reg_mask_t xtensa_submask33[] = { { 130, 5, 1 } };
|
||||
const xtensa_mask_t xtensa_mask33 = { 1, xtensa_submask33 };
|
||||
xtensa_reg_mask_t xtensa_submask34[] = { { 130, 6, 1 } };
|
||||
const xtensa_mask_t xtensa_mask34 = { 1, xtensa_submask34 };
|
||||
xtensa_reg_mask_t xtensa_submask35[] = { { 167, 8, 4 } };
|
||||
const xtensa_mask_t xtensa_mask35 = { 1, xtensa_submask35 };
|
||||
xtensa_reg_mask_t xtensa_submask36[] = { { 96, 7, 1 } };
|
||||
const xtensa_mask_t xtensa_mask36 = { 1, xtensa_submask36 };
|
||||
xtensa_reg_mask_t xtensa_submask37[] = { { 96, 0, 7 } };
|
||||
const xtensa_mask_t xtensa_mask37 = { 1, xtensa_submask37 };
|
||||
xtensa_reg_mask_t xtensa_submask38[] = { { 99, 28, 1 } };
|
||||
const xtensa_mask_t xtensa_mask38 = { 1, xtensa_submask38 };
|
||||
xtensa_reg_mask_t xtensa_submask39[] = { { 98, 0, 4 } };
|
||||
const xtensa_mask_t xtensa_mask39 = { 1, xtensa_submask39 };
|
||||
xtensa_reg_mask_t xtensa_submask40[] = { { 98, 4, 4 } };
|
||||
const xtensa_mask_t xtensa_mask40 = { 1, xtensa_submask40 };
|
||||
xtensa_reg_mask_t xtensa_submask41[] = { { 98, 12, 4 } };
|
||||
const xtensa_mask_t xtensa_mask41 = { 1, xtensa_submask41 };
|
||||
xtensa_reg_mask_t xtensa_submask42[] = { { 98, 8, 4 } };
|
||||
const xtensa_mask_t xtensa_mask42 = { 1, xtensa_submask42 };
|
||||
xtensa_reg_mask_t xtensa_submask43[] = { { 99, 0, 27 } };
|
||||
const xtensa_mask_t xtensa_mask43 = { 1, xtensa_submask43 };
|
||||
xtensa_reg_mask_t xtensa_submask44[] = { { 99, 27, 1 } };
|
||||
const xtensa_mask_t xtensa_mask44 = { 1, xtensa_submask44 };
|
||||
xtensa_reg_mask_t xtensa_submask45[] = { { 94, 0, 2 } };
|
||||
const xtensa_mask_t xtensa_mask45 = { 1, xtensa_submask45 };
|
||||
xtensa_reg_mask_t xtensa_submask46[] = { { 94, 6, 1 } };
|
||||
const xtensa_mask_t xtensa_mask46 = { 1, xtensa_submask46 };
|
||||
xtensa_reg_mask_t xtensa_submask47[] = { { 94, 5, 1 } };
|
||||
const xtensa_mask_t xtensa_mask47 = { 1, xtensa_submask47 };
|
||||
xtensa_reg_mask_t xtensa_submask48[] = { { 94, 4, 1 } };
|
||||
const xtensa_mask_t xtensa_mask48 = { 1, xtensa_submask48 };
|
||||
xtensa_reg_mask_t xtensa_submask49[] = { { 94, 3, 1 } };
|
||||
const xtensa_mask_t xtensa_mask49 = { 1, xtensa_submask49 };
|
||||
xtensa_reg_mask_t xtensa_submask50[] = { { 94, 2, 1 } };
|
||||
const xtensa_mask_t xtensa_mask50 = { 1, xtensa_submask50 };
|
||||
xtensa_reg_mask_t xtensa_submask51[] = { { 95, 11, 1 } };
|
||||
const xtensa_mask_t xtensa_mask51 = { 1, xtensa_submask51 };
|
||||
xtensa_reg_mask_t xtensa_submask52[] = { { 95, 10, 1 } };
|
||||
const xtensa_mask_t xtensa_mask52 = { 1, xtensa_submask52 };
|
||||
xtensa_reg_mask_t xtensa_submask53[] = { { 95, 9, 1 } };
|
||||
const xtensa_mask_t xtensa_mask53 = { 1, xtensa_submask53 };
|
||||
xtensa_reg_mask_t xtensa_submask54[] = { { 95, 8, 1 } };
|
||||
const xtensa_mask_t xtensa_mask54 = { 1, xtensa_submask54 };
|
||||
xtensa_reg_mask_t xtensa_submask55[] = { { 95, 7, 1 } };
|
||||
const xtensa_mask_t xtensa_mask55 = { 1, xtensa_submask55 };
|
||||
xtensa_reg_mask_t xtensa_submask56[] = { { 94, 12, 20 } };
|
||||
const xtensa_mask_t xtensa_mask56 = { 1, xtensa_submask56 };
|
||||
xtensa_reg_mask_t xtensa_submask57[] = { { 95, 12, 20 } };
|
||||
const xtensa_mask_t xtensa_mask57 = { 1, xtensa_submask57 };
|
||||
xtensa_reg_mask_t xtensa_submask58[] = { { 94, 7, 5 } };
|
||||
const xtensa_mask_t xtensa_mask58 = { 1, xtensa_submask58 };
|
||||
xtensa_reg_mask_t xtensa_submask59[] = { { 95, 0, 7 } };
|
||||
const xtensa_mask_t xtensa_mask59 = { 1, xtensa_submask59 };
|
||||
|
||||
|
||||
/* Register map. */
|
||||
xtensa_register_t rmap[] =
|
||||
{
|
||||
/* idx ofs bi sz al targno flags cp typ group name */
|
||||
XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
|
||||
XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
|
||||
XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
|
||||
XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
|
||||
XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
|
||||
XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
|
||||
XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
|
||||
XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
|
||||
XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
|
||||
XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
|
||||
XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0)
|
||||
XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0)
|
||||
XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0)
|
||||
XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0)
|
||||
XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0)
|
||||
XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0)
|
||||
XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0)
|
||||
XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0)
|
||||
XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0)
|
||||
XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0)
|
||||
XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0)
|
||||
XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0)
|
||||
XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0)
|
||||
XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0)
|
||||
XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0)
|
||||
XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0)
|
||||
XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0)
|
||||
XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0)
|
||||
XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0)
|
||||
XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0)
|
||||
XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
|
||||
XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
|
||||
XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
|
||||
XTREG( 33,132,32, 4, 4,0x0120,0x0006,-2, 1,0x0002,ar32, 0,0,0,0,0,0)
|
||||
XTREG( 34,136,32, 4, 4,0x0121,0x0006,-2, 1,0x0002,ar33, 0,0,0,0,0,0)
|
||||
XTREG( 35,140,32, 4, 4,0x0122,0x0006,-2, 1,0x0002,ar34, 0,0,0,0,0,0)
|
||||
XTREG( 36,144,32, 4, 4,0x0123,0x0006,-2, 1,0x0002,ar35, 0,0,0,0,0,0)
|
||||
XTREG( 37,148,32, 4, 4,0x0124,0x0006,-2, 1,0x0002,ar36, 0,0,0,0,0,0)
|
||||
XTREG( 38,152,32, 4, 4,0x0125,0x0006,-2, 1,0x0002,ar37, 0,0,0,0,0,0)
|
||||
XTREG( 39,156,32, 4, 4,0x0126,0x0006,-2, 1,0x0002,ar38, 0,0,0,0,0,0)
|
||||
XTREG( 40,160,32, 4, 4,0x0127,0x0006,-2, 1,0x0002,ar39, 0,0,0,0,0,0)
|
||||
XTREG( 41,164,32, 4, 4,0x0128,0x0006,-2, 1,0x0002,ar40, 0,0,0,0,0,0)
|
||||
XTREG( 42,168,32, 4, 4,0x0129,0x0006,-2, 1,0x0002,ar41, 0,0,0,0,0,0)
|
||||
XTREG( 43,172,32, 4, 4,0x012a,0x0006,-2, 1,0x0002,ar42, 0,0,0,0,0,0)
|
||||
XTREG( 44,176,32, 4, 4,0x012b,0x0006,-2, 1,0x0002,ar43, 0,0,0,0,0,0)
|
||||
XTREG( 45,180,32, 4, 4,0x012c,0x0006,-2, 1,0x0002,ar44, 0,0,0,0,0,0)
|
||||
XTREG( 46,184,32, 4, 4,0x012d,0x0006,-2, 1,0x0002,ar45, 0,0,0,0,0,0)
|
||||
XTREG( 47,188,32, 4, 4,0x012e,0x0006,-2, 1,0x0002,ar46, 0,0,0,0,0,0)
|
||||
XTREG( 48,192,32, 4, 4,0x012f,0x0006,-2, 1,0x0002,ar47, 0,0,0,0,0,0)
|
||||
XTREG( 49,196,32, 4, 4,0x0130,0x0006,-2, 1,0x0002,ar48, 0,0,0,0,0,0)
|
||||
XTREG( 50,200,32, 4, 4,0x0131,0x0006,-2, 1,0x0002,ar49, 0,0,0,0,0,0)
|
||||
XTREG( 51,204,32, 4, 4,0x0132,0x0006,-2, 1,0x0002,ar50, 0,0,0,0,0,0)
|
||||
XTREG( 52,208,32, 4, 4,0x0133,0x0006,-2, 1,0x0002,ar51, 0,0,0,0,0,0)
|
||||
XTREG( 53,212,32, 4, 4,0x0134,0x0006,-2, 1,0x0002,ar52, 0,0,0,0,0,0)
|
||||
XTREG( 54,216,32, 4, 4,0x0135,0x0006,-2, 1,0x0002,ar53, 0,0,0,0,0,0)
|
||||
XTREG( 55,220,32, 4, 4,0x0136,0x0006,-2, 1,0x0002,ar54, 0,0,0,0,0,0)
|
||||
XTREG( 56,224,32, 4, 4,0x0137,0x0006,-2, 1,0x0002,ar55, 0,0,0,0,0,0)
|
||||
XTREG( 57,228,32, 4, 4,0x0138,0x0006,-2, 1,0x0002,ar56, 0,0,0,0,0,0)
|
||||
XTREG( 58,232,32, 4, 4,0x0139,0x0006,-2, 1,0x0002,ar57, 0,0,0,0,0,0)
|
||||
XTREG( 59,236,32, 4, 4,0x013a,0x0006,-2, 1,0x0002,ar58, 0,0,0,0,0,0)
|
||||
XTREG( 60,240,32, 4, 4,0x013b,0x0006,-2, 1,0x0002,ar59, 0,0,0,0,0,0)
|
||||
XTREG( 61,244,32, 4, 4,0x013c,0x0006,-2, 1,0x0002,ar60, 0,0,0,0,0,0)
|
||||
XTREG( 62,248,32, 4, 4,0x013d,0x0006,-2, 1,0x0002,ar61, 0,0,0,0,0,0)
|
||||
XTREG( 63,252,32, 4, 4,0x013e,0x0006,-2, 1,0x0002,ar62, 0,0,0,0,0,0)
|
||||
XTREG( 64,256,32, 4, 4,0x013f,0x0006,-2, 1,0x0002,ar63, 0,0,0,0,0,0)
|
||||
XTREG( 65,260,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0)
|
||||
XTREG( 66,264,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0)
|
||||
XTREG( 67,268,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0)
|
||||
XTREG( 68,272, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
|
||||
XTREG( 69,276,13, 4, 4,0x0228,0x0006,-2, 2,0x1100,prefctl, 0,0,0,0,0,0)
|
||||
XTREG( 70,280, 4, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
|
||||
XTREG( 71,284,16, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
|
||||
XTREG( 72,288,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0)
|
||||
XTREG( 73,292,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0)
|
||||
XTREG( 74,296,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
|
||||
XTREG( 75,300,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0)
|
||||
XTREG( 76,304,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0)
|
||||
XTREG( 77,308,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
|
||||
XTREG( 78,312,32, 4, 4,0x0030,0x0006, 0, 4,0x0401,f0,
|
||||
"03:03:44:00","03:03:04:00",0,0,0,0)
|
||||
XTREG( 79,316,32, 4, 4,0x0031,0x0006, 0, 4,0x0401,f1,
|
||||
"03:13:44:00","03:13:04:00",0,0,0,0)
|
||||
XTREG( 80,320,32, 4, 4,0x0032,0x0006, 0, 4,0x0401,f2,
|
||||
"03:23:44:00","03:23:04:00",0,0,0,0)
|
||||
XTREG( 81,324,32, 4, 4,0x0033,0x0006, 0, 4,0x0401,f3,
|
||||
"03:33:44:00","03:33:04:00",0,0,0,0)
|
||||
XTREG( 82,328,32, 4, 4,0x0034,0x0006, 0, 4,0x0401,f4,
|
||||
"03:43:44:00","03:43:04:00",0,0,0,0)
|
||||
XTREG( 83,332,32, 4, 4,0x0035,0x0006, 0, 4,0x0401,f5,
|
||||
"03:53:44:00","03:53:04:00",0,0,0,0)
|
||||
XTREG( 84,336,32, 4, 4,0x0036,0x0006, 0, 4,0x0401,f6,
|
||||
"03:63:44:00","03:63:04:00",0,0,0,0)
|
||||
XTREG( 85,340,32, 4, 4,0x0037,0x0006, 0, 4,0x0401,f7,
|
||||
"03:73:44:00","03:73:04:00",0,0,0,0)
|
||||
XTREG( 86,344,32, 4, 4,0x0038,0x0006, 0, 4,0x0401,f8,
|
||||
"03:83:44:00","03:83:04:00",0,0,0,0)
|
||||
XTREG( 87,348,32, 4, 4,0x0039,0x0006, 0, 4,0x0401,f9,
|
||||
"03:93:44:00","03:93:04:00",0,0,0,0)
|
||||
XTREG( 88,352,32, 4, 4,0x003a,0x0006, 0, 4,0x0401,f10,
|
||||
"03:a3:44:00","03:a3:04:00",0,0,0,0)
|
||||
XTREG( 89,356,32, 4, 4,0x003b,0x0006, 0, 4,0x0401,f11,
|
||||
"03:b3:44:00","03:b3:04:00",0,0,0,0)
|
||||
XTREG( 90,360,32, 4, 4,0x003c,0x0006, 0, 4,0x0401,f12,
|
||||
"03:c3:44:00","03:c3:04:00",0,0,0,0)
|
||||
XTREG( 91,364,32, 4, 4,0x003d,0x0006, 0, 4,0x0401,f13,
|
||||
"03:d3:44:00","03:d3:04:00",0,0,0,0)
|
||||
XTREG( 92,368,32, 4, 4,0x003e,0x0006, 0, 4,0x0401,f14,
|
||||
"03:e3:44:00","03:e3:04:00",0,0,0,0)
|
||||
XTREG( 93,372,32, 4, 4,0x003f,0x0006, 0, 4,0x0401,f15,
|
||||
"03:f3:44:00","03:f3:04:00",0,0,0,0)
|
||||
XTREG( 94,376,32, 4, 4,0x03e8,0x0006, 0, 3,0x0100,fcr, 0,0,0,0,0,0)
|
||||
XTREG( 95,380,32, 4, 4,0x03e9,0x0006, 0, 3,0x0100,fsr, 0,0,0,0,0,0)
|
||||
XTREG( 96,384, 8, 4, 4,0x03f0,0x0006, 1, 3,0x0100,ae_ovf_sar, 0,0,0,0,0,0)
|
||||
XTREG( 97,388,32, 4, 4,0x03f1,0x0006, 1, 3,0x0110,ae_bithead, 0,0,0,0,0,0)
|
||||
XTREG( 98,392,16, 4, 4,0x03f2,0x0006, 1, 3,0x0100,ae_ts_fts_bu_bp,0,0,0,0,0,0)
|
||||
XTREG( 99,396,29, 4, 4,0x03f3,0x0006, 1, 3,0x0100,ae_cw_sd_no, 0,0,0,0,0,0)
|
||||
XTREG(100,400,32, 4, 4,0x03f6,0x0006, 1, 3,0x0110,ae_cbegin0, 0,0,0,0,0,0)
|
||||
XTREG(101,404,32, 4, 4,0x03f7,0x0006, 1, 3,0x0110,ae_cend0, 0,0,0,0,0,0)
|
||||
XTREG(102,408,64, 8, 8,0x1000,0x0006, 1, 4,0x0101,aed0,
|
||||
"03:04:04:01","03:04:04:cf",0,0,0,0)
|
||||
XTREG(103,416,64, 8, 8,0x1001,0x0006, 1, 4,0x0101,aed1,
|
||||
"03:04:14:01","03:04:14:cf",0,0,0,0)
|
||||
XTREG(104,424,64, 8, 8,0x1002,0x0006, 1, 4,0x0101,aed2,
|
||||
"03:04:24:01","03:04:24:cf",0,0,0,0)
|
||||
XTREG(105,432,64, 8, 8,0x1003,0x0006, 1, 4,0x0101,aed3,
|
||||
"03:04:34:01","03:04:34:cf",0,0,0,0)
|
||||
XTREG(106,440,64, 8, 8,0x1004,0x0006, 1, 4,0x0101,aed4,
|
||||
"03:04:44:01","03:04:44:cf",0,0,0,0)
|
||||
XTREG(107,448,64, 8, 8,0x1005,0x0006, 1, 4,0x0101,aed5,
|
||||
"03:04:54:01","03:04:54:cf",0,0,0,0)
|
||||
XTREG(108,456,64, 8, 8,0x1006,0x0006, 1, 4,0x0101,aed6,
|
||||
"03:04:64:01","03:04:64:cf",0,0,0,0)
|
||||
XTREG(109,464,64, 8, 8,0x1007,0x0006, 1, 4,0x0101,aed7,
|
||||
"03:04:74:01","03:04:74:cf",0,0,0,0)
|
||||
XTREG(110,472,64, 8, 8,0x1008,0x0006, 1, 4,0x0101,aed8,
|
||||
"03:04:84:01","03:04:84:cf",0,0,0,0)
|
||||
XTREG(111,480,64, 8, 8,0x1009,0x0006, 1, 4,0x0101,aed9,
|
||||
"03:04:94:01","03:04:94:cf",0,0,0,0)
|
||||
XTREG(112,488,64, 8, 8,0x100a,0x0006, 1, 4,0x0101,aed10,
|
||||
"03:04:a4:01","03:04:a4:cf",0,0,0,0)
|
||||
XTREG(113,496,64, 8, 8,0x100b,0x0006, 1, 4,0x0101,aed11,
|
||||
"03:04:b4:01","03:04:b4:cf",0,0,0,0)
|
||||
XTREG(114,504,64, 8, 8,0x100c,0x0006, 1, 4,0x0101,aed12,
|
||||
"03:04:c4:01","03:04:c4:cf",0,0,0,0)
|
||||
XTREG(115,512,64, 8, 8,0x100d,0x0006, 1, 4,0x0101,aed13,
|
||||
"03:04:d4:01","03:04:d4:cf",0,0,0,0)
|
||||
XTREG(116,520,64, 8, 8,0x100e,0x0006, 1, 4,0x0101,aed14,
|
||||
"03:04:e4:01","03:04:e4:cf",0,0,0,0)
|
||||
XTREG(117,528,64, 8, 8,0x100f,0x0006, 1, 4,0x0101,aed15,
|
||||
"03:04:f4:01","03:04:f4:cf",0,0,0,0)
|
||||
XTREG(118,536,64, 8, 8,0x1010,0x0006, 1, 4,0x0101,u0,
|
||||
"08:0f:14:00:0f:00:dc:fb:eb","08:0f:04:00:0f:00:dc:fb:eb",0,0,0,0)
|
||||
XTREG(119,544,64, 8, 8,0x1011,0x0006, 1, 4,0x0101,u1,
|
||||
"08:2f:14:00:0f:00:dc:fb:eb","08:2f:04:00:0f:00:dc:fb:eb",0,0,0,0)
|
||||
XTREG(120,552,64, 8, 8,0x1012,0x0006, 1, 4,0x0101,u2,
|
||||
"08:4f:14:00:0f:00:dc:fb:eb","08:4f:04:00:0f:00:dc:fb:eb",0,0,0,0)
|
||||
XTREG(121,560,64, 8, 8,0x1013,0x0006, 1, 4,0x0101,u3,
|
||||
"08:6f:14:00:0f:00:dc:fb:eb","08:6f:04:00:0f:00:dc:fb:eb",0,0,0,0)
|
||||
XTREG(122,568,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0)
|
||||
XTREG(123,572, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
|
||||
XTREG(124,576,24, 4, 4,0x0261,0x0007,-2, 2,0x1000,memctl, 0,0,0,0,0,0)
|
||||
XTREG(125,580, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0)
|
||||
XTREG(126,584,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
|
||||
XTREG(127,588,32, 4, 4,0x026a,0x0007,-2, 2,0x1000,mepc, 0,0,0,0,0,0)
|
||||
XTREG(128,592,19, 4, 4,0x026b,0x0007,-2, 2,0x1000,meps, 0,0,0,0,0,0)
|
||||
XTREG(129,596,32, 4, 4,0x026c,0x0007,-2, 2,0x1000,mesave, 0,0,0,0,0,0)
|
||||
XTREG(130,600,32, 4, 4,0x026d,0x0007,-2, 2,0x1000,mesr, 0,0,0,0,0,0)
|
||||
XTREG(131,604, 7, 4, 4,0x026e,0x0007,-2, 2,0x1000,mecr, 0,0,0,0,0,0)
|
||||
XTREG(132,608,32, 4, 4,0x026f,0x0007,-2, 2,0x1000,mevaddr, 0,0,0,0,0,0)
|
||||
XTREG(133,612,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
|
||||
XTREG(134,616,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0)
|
||||
XTREG(135,620,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
|
||||
XTREG(136,624,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0)
|
||||
XTREG(137,628,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
|
||||
XTREG(138,632,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0)
|
||||
XTREG(139,636,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
|
||||
XTREG(140,640,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
|
||||
XTREG(141,644,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
|
||||
XTREG(142,648,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0)
|
||||
XTREG(143,652,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
|
||||
XTREG(144,656,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0)
|
||||
XTREG(145,660,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0)
|
||||
XTREG(146,664,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
|
||||
XTREG(147,668,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
|
||||
XTREG(148,672,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0)
|
||||
XTREG(149,676,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0)
|
||||
XTREG(150,680,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0)
|
||||
XTREG(151,684,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0)
|
||||
XTREG(152,688,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0)
|
||||
XTREG(153,692,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
|
||||
XTREG(154,696,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
|
||||
XTREG(155,700,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0)
|
||||
XTREG(156,704,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0)
|
||||
XTREG(157,708,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0)
|
||||
XTREG(158,712,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0)
|
||||
XTREG(159,716,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0)
|
||||
XTREG(160,720, 2, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0)
|
||||
XTREG(161,724,21, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
|
||||
XTREG(162,728,21, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
|
||||
XTREG(163,732,21, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
|
||||
XTREG(164,736,21, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
|
||||
XTREG(165,740,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
|
||||
XTREG(166,744, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
|
||||
XTREG(167,748,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
|
||||
XTREG(168,752,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
|
||||
XTREG(169,756,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
|
||||
XTREG(170,760,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
|
||||
XTREG(171,764, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
|
||||
XTREG(172,768,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
|
||||
XTREG(173,772,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
|
||||
XTREG(174,776,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
|
||||
XTREG(175,780,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0)
|
||||
XTREG(176,784,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
|
||||
XTREG(177,788,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
|
||||
XTREG(178,792,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
|
||||
XTREG(179,796,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
|
||||
XTREG(180,800,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
|
||||
XTREG(181,804,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
|
||||
XTREG(182,808,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
|
||||
XTREG(183,812,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
|
||||
XTREG(184,816,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
|
||||
XTREG(185,820,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
|
||||
XTREG(186,824,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0)
|
||||
XTREG(187,828,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0)
|
||||
XTREG(188,832,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0)
|
||||
XTREG(189,836,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
|
||||
XTREG(190,840,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
|
||||
XTREG(191,844,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
|
||||
XTREG(192,848, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,
|
||||
0,0,&xtensa_mask0,0,0,0)
|
||||
XTREG(193,849, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,
|
||||
0,0,&xtensa_mask1,0,0,0)
|
||||
XTREG(194,850, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,
|
||||
0,0,&xtensa_mask2,0,0,0)
|
||||
XTREG(195,851, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,
|
||||
0,0,&xtensa_mask3,0,0,0)
|
||||
XTREG(196,852, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,
|
||||
0,0,&xtensa_mask4,0,0,0)
|
||||
XTREG(197,853, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,
|
||||
0,0,&xtensa_mask5,0,0,0)
|
||||
XTREG(198,854, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,
|
||||
0,0,&xtensa_mask6,0,0,0)
|
||||
XTREG(199,855, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,
|
||||
0,0,&xtensa_mask7,0,0,0)
|
||||
XTREG(200,856, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,
|
||||
0,0,&xtensa_mask8,0,0,0)
|
||||
XTREG(201,857, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,
|
||||
0,0,&xtensa_mask9,0,0,0)
|
||||
XTREG(202,858, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
|
||||
0,0,&xtensa_mask10,0,0,0)
|
||||
XTREG(203,859, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,
|
||||
0,0,&xtensa_mask11,0,0,0)
|
||||
XTREG(204,860, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,
|
||||
0,0,&xtensa_mask12,0,0,0)
|
||||
XTREG(205,861, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,
|
||||
0,0,&xtensa_mask13,0,0,0)
|
||||
XTREG(206,862, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,
|
||||
0,0,&xtensa_mask14,0,0,0)
|
||||
XTREG(207,863, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,
|
||||
0,0,&xtensa_mask15,0,0,0)
|
||||
XTREG(208,864, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,
|
||||
0,0,&xtensa_mask16,0,0,0)
|
||||
XTREG(209,868, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,
|
||||
0,0,&xtensa_mask17,0,0,0)
|
||||
XTREG(210,872, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,
|
||||
0,0,&xtensa_mask18,0,0,0)
|
||||
XTREG(211,876, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,psexcm,
|
||||
0,0,&xtensa_mask19,0,0,0)
|
||||
XTREG(212,880, 2, 4, 4,0x200c,0x0006,-2, 6,0x1010,pscallinc,
|
||||
0,0,&xtensa_mask20,0,0,0)
|
||||
XTREG(213,884, 4, 4, 4,0x200d,0x0006,-2, 6,0x1010,psowb,
|
||||
0,0,&xtensa_mask21,0,0,0)
|
||||
XTREG(214,888, 1, 4, 4,0x200f,0x0006,-2, 6,0x1010,mesrerrenab,
|
||||
0,0,&xtensa_mask22,0,0,0)
|
||||
XTREG(215,892, 1, 4, 4,0x2010,0x0006,-2, 6,0x1010,mesrerrtest,
|
||||
0,0,&xtensa_mask23,0,0,0)
|
||||
XTREG(216,896, 1, 4, 4,0x2011,0x0006,-2, 6,0x1010,mesrmeme,
|
||||
0,0,&xtensa_mask24,0,0,0)
|
||||
XTREG(217,900, 1, 4, 4,0x2012,0x0006,-2, 6,0x1010,mesrdme,
|
||||
0,0,&xtensa_mask25,0,0,0)
|
||||
XTREG(218,904, 4, 4, 4,0x2013,0x0006,-2, 6,0x1010,mesrmemtype,
|
||||
0,0,&xtensa_mask26,0,0,0)
|
||||
XTREG(219,908, 2, 4, 4,0x2014,0x0006,-2, 6,0x1010,mesracctype,
|
||||
0,0,&xtensa_mask27,0,0,0)
|
||||
XTREG(220,912, 2, 4, 4,0x2015,0x0006,-2, 6,0x1010,mesrerrtype,
|
||||
0,0,&xtensa_mask28,0,0,0)
|
||||
XTREG(221,916, 2, 4, 4,0x2016,0x0006,-2, 6,0x1010,mesrway,
|
||||
0,0,&xtensa_mask29,0,0,0)
|
||||
XTREG(222,920, 1, 4, 4,0x2017,0x0006,-2, 6,0x1010,mesrdataexc,
|
||||
0,0,&xtensa_mask30,0,0,0)
|
||||
XTREG(223,924, 1, 4, 4,0x2018,0x0006,-2, 6,0x1010,mesrinstexc,
|
||||
0,0,&xtensa_mask31,0,0,0)
|
||||
XTREG(224,928, 1, 4, 4,0x2019,0x0006,-2, 6,0x1010,mesrrce,
|
||||
0,0,&xtensa_mask32,0,0,0)
|
||||
XTREG(225,932, 1, 4, 4,0x201a,0x0006,-2, 6,0x1010,mesrdlce,
|
||||
0,0,&xtensa_mask33,0,0,0)
|
||||
XTREG(226,936, 1, 4, 4,0x201b,0x0006,-2, 6,0x1010,mesrilce,
|
||||
0,0,&xtensa_mask34,0,0,0)
|
||||
XTREG(227,940, 4, 4, 4,0x2020,0x0006,-2, 6,0x1010,dbnum,
|
||||
0,0,&xtensa_mask35,0,0,0)
|
||||
XTREG(228,944, 1, 4, 4,0x2022,0x0006, 1, 5,0x1010,ae_overflow,
|
||||
0,0,&xtensa_mask36,0,0,0)
|
||||
XTREG(229,948, 7, 4, 4,0x2023,0x0006, 1, 5,0x1010,ae_sar,
|
||||
0,0,&xtensa_mask37,0,0,0)
|
||||
XTREG(230,952, 1, 4, 4,0x2024,0x0006, 1, 5,0x1010,ae_cwrap,
|
||||
0,0,&xtensa_mask38,0,0,0)
|
||||
XTREG(231,956, 4, 4, 4,0x2025,0x0006, 1, 5,0x1010,ae_bitptr,
|
||||
0,0,&xtensa_mask39,0,0,0)
|
||||
XTREG(232,960, 4, 4, 4,0x2026,0x0006, 1, 5,0x1010,ae_bitsused,
|
||||
0,0,&xtensa_mask40,0,0,0)
|
||||
XTREG(233,964, 4, 4, 4,0x2027,0x0006, 1, 5,0x1010,ae_tablesize,
|
||||
0,0,&xtensa_mask41,0,0,0)
|
||||
XTREG(234,968, 4, 4, 4,0x2028,0x0006, 1, 5,0x1010,ae_first_ts,
|
||||
0,0,&xtensa_mask42,0,0,0)
|
||||
XTREG(235,972,27, 4, 4,0x2029,0x0006, 1, 5,0x1010,ae_nextoffset,
|
||||
0,0,&xtensa_mask43,0,0,0)
|
||||
XTREG(236,976, 1, 4, 4,0x202a,0x0006, 1, 5,0x1010,ae_searchdone,
|
||||
0,0,&xtensa_mask44,0,0,0)
|
||||
XTREG(237,980, 2, 4, 4,0x202b,0x0006, 0, 5,0x1010,roundmode,
|
||||
0,0,&xtensa_mask45,0,0,0)
|
||||
XTREG(238,984, 1, 4, 4,0x202c,0x0006, 0, 5,0x1010,invalidenable,
|
||||
0,0,&xtensa_mask46,0,0,0)
|
||||
XTREG(239,988, 1, 4, 4,0x202d,0x0006, 0, 5,0x1010,divzeroenable,
|
||||
0,0,&xtensa_mask47,0,0,0)
|
||||
XTREG(240,992, 1, 4, 4,0x202e,0x0006, 0, 5,0x1010,overflowenable,
|
||||
0,0,&xtensa_mask48,0,0,0)
|
||||
XTREG(241,996, 1, 4, 4,0x202f,0x0006, 0, 5,0x1010,underflowenable,
|
||||
0,0,&xtensa_mask49,0,0,0)
|
||||
XTREG(242,1000, 1, 4, 4,0x2030,0x0006, 0, 5,0x1010,inexactenable,
|
||||
0,0,&xtensa_mask50,0,0,0)
|
||||
XTREG(243,1004, 1, 4, 4,0x2031,0x0006, 0, 5,0x1010,invalidflag,
|
||||
0,0,&xtensa_mask51,0,0,0)
|
||||
XTREG(244,1008, 1, 4, 4,0x2032,0x0006, 0, 5,0x1010,divzeroflag,
|
||||
0,0,&xtensa_mask52,0,0,0)
|
||||
XTREG(245,1012, 1, 4, 4,0x2033,0x0006, 0, 5,0x1010,overflowflag,
|
||||
0,0,&xtensa_mask53,0,0,0)
|
||||
XTREG(246,1016, 1, 4, 4,0x2034,0x0006, 0, 5,0x1010,underflowflag,
|
||||
0,0,&xtensa_mask54,0,0,0)
|
||||
XTREG(247,1020, 1, 4, 4,0x2035,0x0006, 0, 5,0x1010,inexactflag,
|
||||
0,0,&xtensa_mask55,0,0,0)
|
||||
XTREG(248,1024,20, 4, 4,0x2036,0x0006, 0, 5,0x1010,fpreserved20,
|
||||
0,0,&xtensa_mask56,0,0,0)
|
||||
XTREG(249,1028,20, 4, 4,0x2037,0x0006, 0, 5,0x1010,fpreserved20a,
|
||||
0,0,&xtensa_mask57,0,0,0)
|
||||
XTREG(250,1032, 5, 4, 4,0x2038,0x0006, 0, 5,0x1010,fpreserved5,
|
||||
0,0,&xtensa_mask58,0,0,0)
|
||||
XTREG_END
|
||||
};
|
||||
|
||||
|
||||
|
||||
#ifdef XTENSA_CONFIG_INSTANTIATE
|
||||
XTENSA_CONFIG_INSTANTIATE(rmap,8)
|
||||
#endif
|
||||
|
||||
xtensa_gdbarch_tdep xtensa_tdep (rmap);
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
/* Customized table mapping between kernel xtregset and GDB register cache.
|
||||
|
||||
Copyright (c) 2007-2010 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
|
||||
typedef struct {
|
||||
int gdb_regnum;
|
||||
int gdb_offset;
|
||||
int ptrace_cp_offset;
|
||||
int ptrace_offset;
|
||||
int size;
|
||||
int coproc;
|
||||
int dbnum;
|
||||
char* name
|
||||
;} xtensa_regtable_t;
|
||||
|
||||
#define XTENSA_ELF_XTREG_SIZE 264
|
||||
|
||||
const xtensa_regtable_t xtensa_regmap_table[] = {
|
||||
/* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */
|
||||
{ 76, 304, 0, 0, 4, -1, 0x0204, "br" },
|
||||
{ 77, 308, 4, 4, 4, -1, 0x020c, "scompare1" },
|
||||
{ 78, 312, 8, 16, 4, 0, 0x0030, "f0" },
|
||||
{ 79, 316, 12, 20, 4, 0, 0x0031, "f1" },
|
||||
{ 80, 320, 16, 24, 4, 0, 0x0032, "f2" },
|
||||
{ 81, 324, 20, 28, 4, 0, 0x0033, "f3" },
|
||||
{ 82, 328, 24, 32, 4, 0, 0x0034, "f4" },
|
||||
{ 83, 332, 28, 36, 4, 0, 0x0035, "f5" },
|
||||
{ 84, 336, 32, 40, 4, 0, 0x0036, "f6" },
|
||||
{ 85, 340, 36, 44, 4, 0, 0x0037, "f7" },
|
||||
{ 86, 344, 40, 48, 4, 0, 0x0038, "f8" },
|
||||
{ 87, 348, 44, 52, 4, 0, 0x0039, "f9" },
|
||||
{ 88, 352, 48, 56, 4, 0, 0x003a, "f10" },
|
||||
{ 89, 356, 52, 60, 4, 0, 0x003b, "f11" },
|
||||
{ 90, 360, 56, 64, 4, 0, 0x003c, "f12" },
|
||||
{ 91, 364, 60, 68, 4, 0, 0x003d, "f13" },
|
||||
{ 92, 368, 64, 72, 4, 0, 0x003e, "f14" },
|
||||
{ 93, 372, 68, 76, 4, 0, 0x003f, "f15" },
|
||||
{ 94, 376, 0, 8, 4, 0, 0x03e8, "fcr" },
|
||||
{ 95, 380, 4, 12, 4, 0, 0x03e9, "fsr" },
|
||||
{ 96, 384, 0, 80, 4, 1, 0x03f0, "ae_ovf_sar" },
|
||||
{ 97, 388, 4, 84, 4, 1, 0x03f1, "ae_bithead" },
|
||||
{ 98, 392, 8, 88, 4, 1, 0x03f2, "ae_ts_fts_bu_bp" },
|
||||
{ 99, 396, 12, 92, 4, 1, 0x03f3, "ae_cw_sd_no" },
|
||||
{ 100, 400, 16, 96, 4, 1, 0x03f6, "ae_cbegin0" },
|
||||
{ 101, 404, 20, 100, 4, 1, 0x03f7, "ae_cend0" },
|
||||
{ 102, 408, 24, 104, 8, 1, 0x1000, "aed0" },
|
||||
{ 103, 416, 32, 112, 8, 1, 0x1001, "aed1" },
|
||||
{ 104, 424, 40, 120, 8, 1, 0x1002, "aed2" },
|
||||
{ 105, 432, 48, 128, 8, 1, 0x1003, "aed3" },
|
||||
{ 106, 440, 56, 136, 8, 1, 0x1004, "aed4" },
|
||||
{ 107, 448, 64, 144, 8, 1, 0x1005, "aed5" },
|
||||
{ 108, 456, 72, 152, 8, 1, 0x1006, "aed6" },
|
||||
{ 109, 464, 80, 160, 8, 1, 0x1007, "aed7" },
|
||||
{ 110, 472, 88, 168, 8, 1, 0x1008, "aed8" },
|
||||
{ 111, 480, 96, 176, 8, 1, 0x1009, "aed9" },
|
||||
{ 112, 488, 104, 184, 8, 1, 0x100a, "aed10" },
|
||||
{ 113, 496, 112, 192, 8, 1, 0x100b, "aed11" },
|
||||
{ 114, 504, 120, 200, 8, 1, 0x100c, "aed12" },
|
||||
{ 115, 512, 128, 208, 8, 1, 0x100d, "aed13" },
|
||||
{ 116, 520, 136, 216, 8, 1, 0x100e, "aed14" },
|
||||
{ 117, 528, 144, 224, 8, 1, 0x100f, "aed15" },
|
||||
{ 118, 536, 152, 232, 8, 1, 0x1010, "u0" },
|
||||
{ 119, 544, 160, 240, 8, 1, 0x1011, "u1" },
|
||||
{ 120, 552, 168, 248, 8, 1, 0x1012, "u2" },
|
||||
{ 121, 560, 176, 256, 8, 1, 0x1013, "u3" },
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
/* Customized table mapping between kernel xtregset and GDB register cache.
|
||||
|
||||
Copyright (c) 2007-2010 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
|
||||
typedef struct {
|
||||
int gdb_regnum;
|
||||
int gdb_offset;
|
||||
int ptrace_cp_offset;
|
||||
int ptrace_offset;
|
||||
int size;
|
||||
int coproc;
|
||||
int dbnum;
|
||||
char* name
|
||||
;} xtensa_regtable_t;
|
||||
|
||||
#define XTENSA_ELF_XTREG_SIZE 264
|
||||
|
||||
const xtensa_regtable_t xtensa_regmap_table[] = {
|
||||
/* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */
|
||||
{ 76, 304, 0, 0, 4, -1, 0x0204, "br" },
|
||||
{ 77, 308, 4, 4, 4, -1, 0x020c, "scompare1" },
|
||||
{ 78, 312, 8, 16, 4, 0, 0x0030, "f0" },
|
||||
{ 79, 316, 12, 20, 4, 0, 0x0031, "f1" },
|
||||
{ 80, 320, 16, 24, 4, 0, 0x0032, "f2" },
|
||||
{ 81, 324, 20, 28, 4, 0, 0x0033, "f3" },
|
||||
{ 82, 328, 24, 32, 4, 0, 0x0034, "f4" },
|
||||
{ 83, 332, 28, 36, 4, 0, 0x0035, "f5" },
|
||||
{ 84, 336, 32, 40, 4, 0, 0x0036, "f6" },
|
||||
{ 85, 340, 36, 44, 4, 0, 0x0037, "f7" },
|
||||
{ 86, 344, 40, 48, 4, 0, 0x0038, "f8" },
|
||||
{ 87, 348, 44, 52, 4, 0, 0x0039, "f9" },
|
||||
{ 88, 352, 48, 56, 4, 0, 0x003a, "f10" },
|
||||
{ 89, 356, 52, 60, 4, 0, 0x003b, "f11" },
|
||||
{ 90, 360, 56, 64, 4, 0, 0x003c, "f12" },
|
||||
{ 91, 364, 60, 68, 4, 0, 0x003d, "f13" },
|
||||
{ 92, 368, 64, 72, 4, 0, 0x003e, "f14" },
|
||||
{ 93, 372, 68, 76, 4, 0, 0x003f, "f15" },
|
||||
{ 94, 376, 0, 8, 4, 0, 0x03e8, "fcr" },
|
||||
{ 95, 380, 4, 12, 4, 0, 0x03e9, "fsr" },
|
||||
{ 96, 384, 0, 80, 4, 1, 0x03f0, "ae_ovf_sar" },
|
||||
{ 97, 388, 4, 84, 4, 1, 0x03f1, "ae_bithead" },
|
||||
{ 98, 392, 8, 88, 4, 1, 0x03f2, "ae_ts_fts_bu_bp" },
|
||||
{ 99, 396, 12, 92, 4, 1, 0x03f3, "ae_cw_sd_no" },
|
||||
{ 100, 400, 16, 96, 4, 1, 0x03f6, "ae_cbegin0" },
|
||||
{ 101, 404, 20, 100, 4, 1, 0x03f7, "ae_cend0" },
|
||||
{ 102, 408, 24, 104, 8, 1, 0x1000, "aed0" },
|
||||
{ 103, 416, 32, 112, 8, 1, 0x1001, "aed1" },
|
||||
{ 104, 424, 40, 120, 8, 1, 0x1002, "aed2" },
|
||||
{ 105, 432, 48, 128, 8, 1, 0x1003, "aed3" },
|
||||
{ 106, 440, 56, 136, 8, 1, 0x1004, "aed4" },
|
||||
{ 107, 448, 64, 144, 8, 1, 0x1005, "aed5" },
|
||||
{ 108, 456, 72, 152, 8, 1, 0x1006, "aed6" },
|
||||
{ 109, 464, 80, 160, 8, 1, 0x1007, "aed7" },
|
||||
{ 110, 472, 88, 168, 8, 1, 0x1008, "aed8" },
|
||||
{ 111, 480, 96, 176, 8, 1, 0x1009, "aed9" },
|
||||
{ 112, 488, 104, 184, 8, 1, 0x100a, "aed10" },
|
||||
{ 113, 496, 112, 192, 8, 1, 0x100b, "aed11" },
|
||||
{ 114, 504, 120, 200, 8, 1, 0x100c, "aed12" },
|
||||
{ 115, 512, 128, 208, 8, 1, 0x100d, "aed13" },
|
||||
{ 116, 520, 136, 216, 8, 1, 0x100e, "aed14" },
|
||||
{ 117, 528, 144, 224, 8, 1, 0x100f, "aed15" },
|
||||
{ 118, 536, 152, 232, 8, 1, 0x1010, "u0" },
|
||||
{ 119, 544, 160, 240, 8, 1, 0x1011, "u1" },
|
||||
{ 120, 552, 168, 248, 8, 1, 0x1012, "u2" },
|
||||
{ 121, 560, 176, 256, 8, 1, 0x1013, "u3" },
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,189 @@
|
|||
/* Xtensa configuration settings.
|
||||
Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
|
||||
Free Software Foundation, Inc.
|
||||
Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful, but
|
||||
WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
|
||||
|
||||
#ifndef XTENSA_CONFIG_H
|
||||
#define XTENSA_CONFIG_H
|
||||
|
||||
/* The macros defined here match those with the same names in the Xtensa
|
||||
compile-time HAL (Hardware Abstraction Layer). Please refer to the
|
||||
Xtensa System Software Reference Manual for documentation of these
|
||||
macros. */
|
||||
|
||||
#undef XCHAL_HAVE_BE
|
||||
#define XCHAL_HAVE_BE 0
|
||||
|
||||
#undef XCHAL_HAVE_DENSITY
|
||||
#define XCHAL_HAVE_DENSITY 1
|
||||
|
||||
#undef XCHAL_HAVE_CONST16
|
||||
#define XCHAL_HAVE_CONST16 0
|
||||
|
||||
#undef XCHAL_HAVE_ABS
|
||||
#define XCHAL_HAVE_ABS 1
|
||||
|
||||
#undef XCHAL_HAVE_ADDX
|
||||
#define XCHAL_HAVE_ADDX 1
|
||||
|
||||
#undef XCHAL_HAVE_L32R
|
||||
#define XCHAL_HAVE_L32R 1
|
||||
|
||||
#undef XSHAL_USE_ABSOLUTE_LITERALS
|
||||
#define XSHAL_USE_ABSOLUTE_LITERALS 0
|
||||
|
||||
#undef XSHAL_HAVE_TEXT_SECTION_LITERALS
|
||||
#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
|
||||
|
||||
#undef XCHAL_HAVE_MAC16
|
||||
#define XCHAL_HAVE_MAC16 0
|
||||
|
||||
#undef XCHAL_HAVE_MUL16
|
||||
#define XCHAL_HAVE_MUL16 1
|
||||
|
||||
#undef XCHAL_HAVE_MUL32
|
||||
#define XCHAL_HAVE_MUL32 1
|
||||
|
||||
#undef XCHAL_HAVE_MUL32_HIGH
|
||||
#define XCHAL_HAVE_MUL32_HIGH 1
|
||||
|
||||
#undef XCHAL_HAVE_DIV32
|
||||
#define XCHAL_HAVE_DIV32 1
|
||||
|
||||
#undef XCHAL_HAVE_NSA
|
||||
#define XCHAL_HAVE_NSA 1
|
||||
|
||||
#undef XCHAL_HAVE_MINMAX
|
||||
#define XCHAL_HAVE_MINMAX 1
|
||||
|
||||
#undef XCHAL_HAVE_SEXT
|
||||
#define XCHAL_HAVE_SEXT 1
|
||||
|
||||
#undef XCHAL_HAVE_LOOPS
|
||||
#define XCHAL_HAVE_LOOPS 1
|
||||
|
||||
#undef XCHAL_HAVE_THREADPTR
|
||||
#define XCHAL_HAVE_THREADPTR 1
|
||||
|
||||
#undef XCHAL_HAVE_RELEASE_SYNC
|
||||
#define XCHAL_HAVE_RELEASE_SYNC 1
|
||||
|
||||
#undef XCHAL_HAVE_S32C1I
|
||||
#define XCHAL_HAVE_S32C1I 1
|
||||
|
||||
#undef XCHAL_HAVE_BOOLEANS
|
||||
#define XCHAL_HAVE_BOOLEANS 1
|
||||
|
||||
#undef XCHAL_HAVE_FP
|
||||
#define XCHAL_HAVE_FP 0
|
||||
|
||||
#undef XCHAL_HAVE_FP_DIV
|
||||
#define XCHAL_HAVE_FP_DIV 0
|
||||
|
||||
#undef XCHAL_HAVE_FP_RECIP
|
||||
#define XCHAL_HAVE_FP_RECIP 0
|
||||
|
||||
#undef XCHAL_HAVE_FP_SQRT
|
||||
#define XCHAL_HAVE_FP_SQRT 0
|
||||
|
||||
#undef XCHAL_HAVE_FP_RSQRT
|
||||
#define XCHAL_HAVE_FP_RSQRT 0
|
||||
|
||||
#undef XCHAL_HAVE_DFP_ACCEL
|
||||
#define XCHAL_HAVE_DFP_ACCEL 0
|
||||
/* For backward compatibility */
|
||||
#undef XCHAL_HAVE_DFP_accel
|
||||
#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL
|
||||
|
||||
#undef XCHAL_HAVE_WINDOWED
|
||||
#define XCHAL_HAVE_WINDOWED 1
|
||||
|
||||
#undef XCHAL_NUM_AREGS
|
||||
#define XCHAL_NUM_AREGS 64
|
||||
|
||||
#undef XCHAL_HAVE_WIDE_BRANCHES
|
||||
#define XCHAL_HAVE_WIDE_BRANCHES 0
|
||||
|
||||
#undef XCHAL_HAVE_PREDICTED_BRANCHES
|
||||
#define XCHAL_HAVE_PREDICTED_BRANCHES 0
|
||||
|
||||
|
||||
#undef XCHAL_ICACHE_SIZE
|
||||
#define XCHAL_ICACHE_SIZE 16384
|
||||
|
||||
#undef XCHAL_DCACHE_SIZE
|
||||
#define XCHAL_DCACHE_SIZE 49152
|
||||
|
||||
#undef XCHAL_ICACHE_LINESIZE
|
||||
#define XCHAL_ICACHE_LINESIZE 64
|
||||
|
||||
#undef XCHAL_DCACHE_LINESIZE
|
||||
#define XCHAL_DCACHE_LINESIZE 64
|
||||
|
||||
#undef XCHAL_ICACHE_LINEWIDTH
|
||||
#define XCHAL_ICACHE_LINEWIDTH 6
|
||||
|
||||
#undef XCHAL_DCACHE_LINEWIDTH
|
||||
#define XCHAL_DCACHE_LINEWIDTH 6
|
||||
|
||||
#undef XCHAL_DCACHE_IS_WRITEBACK
|
||||
#define XCHAL_DCACHE_IS_WRITEBACK 1
|
||||
|
||||
|
||||
#undef XCHAL_HAVE_MMU
|
||||
#define XCHAL_HAVE_MMU 0
|
||||
|
||||
|
||||
#undef XCHAL_HAVE_DEBUG
|
||||
#define XCHAL_HAVE_DEBUG 1
|
||||
|
||||
#undef XCHAL_NUM_IBREAK
|
||||
#define XCHAL_NUM_IBREAK 2
|
||||
|
||||
#undef XCHAL_NUM_DBREAK
|
||||
#define XCHAL_NUM_DBREAK 2
|
||||
|
||||
#undef XCHAL_DEBUGLEVEL
|
||||
#define XCHAL_DEBUGLEVEL 6
|
||||
|
||||
|
||||
#undef XCHAL_MAX_INSTRUCTION_SIZE
|
||||
#define XCHAL_MAX_INSTRUCTION_SIZE 8
|
||||
|
||||
#undef XCHAL_INST_FETCH_WIDTH
|
||||
#define XCHAL_INST_FETCH_WIDTH 8
|
||||
|
||||
|
||||
#undef XSHAL_ABI
|
||||
#undef XTHAL_ABI_WINDOWED
|
||||
#undef XTHAL_ABI_CALL0
|
||||
#define XSHAL_ABI XTHAL_ABI_WINDOWED
|
||||
#define XTHAL_ABI_WINDOWED 0
|
||||
#define XTHAL_ABI_CALL0 1
|
||||
|
||||
|
||||
#undef XCHAL_M_STAGE
|
||||
#define XCHAL_M_STAGE 3
|
||||
|
||||
#undef XTENSA_MARCH_LATEST
|
||||
#define XTENSA_MARCH_LATEST 260003
|
||||
|
||||
#undef XTENSA_MARCH_EARLIEST
|
||||
#define XTENSA_MARCH_EARLIEST 260003
|
||||
|
||||
|
||||
#endif /* !XTENSA_CONFIG_H */
|
||||
|
|
@ -0,0 +1,629 @@
|
|||
/*
|
||||
* xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
|
||||
* processor CORE configuration
|
||||
*
|
||||
* See <xtensa/config/core.h>, which includes this file, for more details.
|
||||
*/
|
||||
|
||||
/* Xtensa processor core configuration information.
|
||||
|
||||
Copyright (c) 1999-2019 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#ifndef _XTENSA_CORE_CONFIGURATION_H
|
||||
#define _XTENSA_CORE_CONFIGURATION_H
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
Parameters Useful for Any Code, USER or PRIVILEGED
|
||||
****************************************************************************/
|
||||
|
||||
/*
|
||||
* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
|
||||
* configured, and a value of 0 otherwise. These macros are always defined.
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
ISA
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
|
||||
#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
|
||||
#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */
|
||||
#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */
|
||||
#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */
|
||||
#define XCHAL_HAVE_DEBUG 1 /* debug option */
|
||||
#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
|
||||
#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
|
||||
#define XCHAL_LOOP_BUFFER_SIZE 64 /* zero-ov. loop instr buffer size */
|
||||
#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
|
||||
#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
|
||||
#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
|
||||
#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
|
||||
#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
|
||||
#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
|
||||
#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
|
||||
#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */
|
||||
#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
|
||||
#define XCHAL_HAVE_L32R 1 /* L32R instruction */
|
||||
#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
|
||||
#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
|
||||
#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
|
||||
#define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */
|
||||
#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
|
||||
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
|
||||
#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
|
||||
#define XCHAL_HAVE_ABS 1 /* ABS instruction */
|
||||
/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
|
||||
/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
|
||||
#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
|
||||
#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
|
||||
#define XCHAL_HAVE_SPECULATION 0 /* speculation */
|
||||
#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
|
||||
#define XCHAL_NUM_CONTEXTS 1 /* */
|
||||
#define XCHAL_NUM_MISC_REGS 0 /* num of scratch regs (0..4) */
|
||||
#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
|
||||
#define XCHAL_HAVE_PRID 1 /* processor ID register */
|
||||
#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
|
||||
#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
|
||||
#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
|
||||
#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
|
||||
#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
|
||||
#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
|
||||
#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
|
||||
#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
|
||||
#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
|
||||
#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
|
||||
#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */
|
||||
#define XCHAL_HAVE_MAC16 0 /* MAC16 package */
|
||||
|
||||
#define XCHAL_HAVE_FUSION 0 /* Fusion*/
|
||||
#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
|
||||
#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
|
||||
#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
|
||||
#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
|
||||
#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
|
||||
#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
|
||||
#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
|
||||
#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
|
||||
#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */
|
||||
#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */
|
||||
#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
|
||||
#define XCHAL_HAVE_HIFI3 1 /* HiFi3 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
|
||||
#define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */
|
||||
#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
|
||||
#define XCHAL_HAVE_HIFI_MINI 0
|
||||
|
||||
|
||||
|
||||
#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
|
||||
#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
|
||||
#define XCHAL_HAVE_USER_SPFPU 0 /* user SP floating-point pkg */
|
||||
#define XCHAL_HAVE_FP 1 /* single prec floating point */
|
||||
#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */
|
||||
#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */
|
||||
#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */
|
||||
#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */
|
||||
#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
|
||||
#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
|
||||
#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
|
||||
#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
|
||||
#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
|
||||
#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */
|
||||
#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
|
||||
|
||||
#define XCHAL_HAVE_DFPU_SINGLE_ONLY 1 /* DFPU Coprocessor, single precision only */
|
||||
#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
|
||||
#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
|
||||
#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
|
||||
|
||||
#define XCHAL_HAVE_FUSIONG 0 /* FusionG */
|
||||
#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */
|
||||
#define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */
|
||||
#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */
|
||||
#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */
|
||||
#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */
|
||||
|
||||
#define XCHAL_HAVE_PDX 0 /* PDX */
|
||||
#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */
|
||||
#define XCHAL_HAVE_PDX4 0 /* PDX4 */
|
||||
#define XCHAL_HAVE_PDX8 0 /* PDX8 */
|
||||
#define XCHAL_HAVE_PDX16 0 /* PDX16 */
|
||||
|
||||
#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
|
||||
#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */
|
||||
#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
|
||||
#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
|
||||
#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
|
||||
#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
|
||||
#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
|
||||
#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */
|
||||
#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
|
||||
#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
|
||||
#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
|
||||
#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
|
||||
#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
|
||||
#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
|
||||
#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
|
||||
#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */
|
||||
#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
|
||||
|
||||
#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */
|
||||
#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */
|
||||
#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, or P3 */
|
||||
#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */
|
||||
#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */
|
||||
#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6 */
|
||||
#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6 */
|
||||
|
||||
#define XCHAL_HAVE_VISIONC 0 /* Vision C */
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MISC
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
|
||||
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 16 /* size of write buffer */
|
||||
#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */
|
||||
#define XCHAL_DATA_WIDTH 8 /* data width in bytes */
|
||||
#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay
|
||||
(1 = 5-stage, 2 = 7-stage) */
|
||||
#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */
|
||||
#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */
|
||||
/* In T1050, applies to selected core load and store instructions (see ISA): */
|
||||
#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
|
||||
#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
|
||||
#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */
|
||||
#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/
|
||||
|
||||
#define XCHAL_SW_VERSION 1200008 /* sw version of this header */
|
||||
|
||||
#define XCHAL_CORE_ID "cavs2x_LX6HiFi3_2017_8" /* alphanum core name
|
||||
(CoreID) set in the Xtensa
|
||||
Processor Generator */
|
||||
|
||||
#define XCHAL_BUILD_UNIQUE_ID 0x0007AF71 /* 22-bit sw build ID */
|
||||
|
||||
/*
|
||||
* These definitions describe the hardware targeted by this software.
|
||||
*/
|
||||
#define XCHAL_HW_CONFIGID0 0xC2F3FBFE /* ConfigID hi 32 bits*/
|
||||
#define XCHAL_HW_CONFIGID1 0x1CC6C29B /* ConfigID lo 32 bits*/
|
||||
#define XCHAL_HW_VERSION_NAME "LX6.0.3" /* full version name */
|
||||
#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */
|
||||
#define XCHAL_HW_VERSION_MINOR 3 /* minor ver# of targeted hw */
|
||||
#define XCHAL_HW_VERSION 260003 /* major*100+minor */
|
||||
#define XCHAL_HW_REL_LX6 1
|
||||
#define XCHAL_HW_REL_LX6_0 1
|
||||
#define XCHAL_HW_REL_LX6_0_3 1
|
||||
#define XCHAL_HW_CONFIGID_RELIABLE 1
|
||||
/* If software targets a *range* of hardware versions, these are the bounds: */
|
||||
#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION_MINOR 3 /* minor v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION 260003 /* earliest targeted hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MINOR 3 /* minor v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION 260003 /* latest targeted hw */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CACHE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_ICACHE_LINESIZE 64 /* I-cache line size in bytes */
|
||||
#define XCHAL_DCACHE_LINESIZE 64 /* D-cache line size in bytes */
|
||||
#define XCHAL_ICACHE_LINEWIDTH 6 /* log2(I line size in bytes) */
|
||||
#define XCHAL_DCACHE_LINEWIDTH 6 /* log2(D line size in bytes) */
|
||||
|
||||
#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */
|
||||
#define XCHAL_DCACHE_SIZE 49152 /* D-cache size in bytes or 0 */
|
||||
|
||||
#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
|
||||
#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
|
||||
|
||||
#define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */
|
||||
#define XCHAL_HAVE_PREFETCH_L1 1 /* prefetch to L1 dcache */
|
||||
#define XCHAL_PREFETCH_CASTOUT_LINES 2 /* dcache pref. castout bufsz */
|
||||
#define XCHAL_PREFETCH_ENTRIES 8 /* cache prefetch entries */
|
||||
#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
|
||||
#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
|
||||
#define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */
|
||||
#define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */
|
||||
#define XCHAL_HAVE_ICACHE_DYN_WAYS 1 /* Icache dynamic way support */
|
||||
#define XCHAL_HAVE_DCACHE_DYN_WAYS 1 /* Dcache dynamic way support */
|
||||
|
||||
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CACHE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_PIF 1 /* any outbound bus present */
|
||||
|
||||
#define XCHAL_HAVE_AXI 0 /* AXI bus */
|
||||
#define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */
|
||||
#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */
|
||||
|
||||
#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */
|
||||
#define XCHAL_HAVE_PIF_REQ_ATTR 1 /* pif attribute */
|
||||
|
||||
/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
|
||||
|
||||
/* Number of cache sets in log2(lines per way): */
|
||||
#define XCHAL_ICACHE_SETWIDTH 6
|
||||
#define XCHAL_DCACHE_SETWIDTH 8
|
||||
|
||||
/* Cache set associativity (number of ways): */
|
||||
#define XCHAL_ICACHE_WAYS 4
|
||||
#define XCHAL_DCACHE_WAYS 3
|
||||
|
||||
/* Cache features: */
|
||||
#define XCHAL_ICACHE_LINE_LOCKABLE 1
|
||||
#define XCHAL_DCACHE_LINE_LOCKABLE 1
|
||||
#define XCHAL_ICACHE_ECC_PARITY XTHAL_MEMEP_ECC
|
||||
#define XCHAL_DCACHE_ECC_PARITY XTHAL_MEMEP_ECC
|
||||
|
||||
/* Cache access size in bytes (affects operation of SICW instruction): */
|
||||
#define XCHAL_ICACHE_ACCESS_SIZE 8
|
||||
#define XCHAL_DCACHE_ACCESS_SIZE 8
|
||||
|
||||
#define XCHAL_DCACHE_BANKS 1 /* number of banks */
|
||||
|
||||
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
|
||||
#define XCHAL_CA_BITS 4
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
INTERNAL I/D RAM/ROMs and XLMI
|
||||
----------------------------------------------------------------------*/
|
||||
#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
|
||||
#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */
|
||||
#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
|
||||
#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */
|
||||
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
|
||||
#define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */
|
||||
|
||||
/* Instruction RAM 0: */
|
||||
#define XCHAL_INSTRAM0_VADDR 0x9F100000 /* virtual address */
|
||||
#define XCHAL_INSTRAM0_PADDR 0x9F100000 /* physical address */
|
||||
#define XCHAL_INSTRAM0_SIZE 1048576 /* size in bytes */
|
||||
#define XCHAL_INSTRAM0_ECC_PARITY XTHAL_MEMEP_ECC /* ECC/parity type, 0=none */
|
||||
#define XCHAL_HAVE_INSTRAM0 1
|
||||
#define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */
|
||||
|
||||
/* Data RAM 0: */
|
||||
#define XCHAL_DATARAM0_VADDR 0x9F000000 /* virtual address */
|
||||
#define XCHAL_DATARAM0_PADDR 0x9F000000 /* physical address */
|
||||
#define XCHAL_DATARAM0_SIZE 524288 /* size in bytes */
|
||||
#define XCHAL_DATARAM0_ECC_PARITY XTHAL_MEMEP_ECC /* ECC/parity type, 0=none */
|
||||
#define XCHAL_DATARAM0_BANKS 1 /* number of banks */
|
||||
#define XCHAL_HAVE_DATARAM0 1
|
||||
#define XCHAL_DATARAM0_HAVE_IDMA 0 /* idma supported by this local memory */
|
||||
|
||||
/* XLMI Port 0: */
|
||||
#define XCHAL_XLMI0_VADDR 0x9F080000 /* virtual address */
|
||||
#define XCHAL_XLMI0_PADDR 0x9F080000 /* physical address */
|
||||
#define XCHAL_XLMI0_SIZE 65536 /* size in bytes */
|
||||
#define XCHAL_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */
|
||||
|
||||
#define XCHAL_HAVE_IDMA 0
|
||||
#define XCHAL_HAVE_IDMA_TRANSPOSE 0
|
||||
|
||||
#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
INTERRUPTS and TIMERS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
|
||||
#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
|
||||
#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
|
||||
#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
|
||||
#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
|
||||
#define XCHAL_NUM_INTERRUPTS 21 /* number of interrupts */
|
||||
#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
|
||||
#define XCHAL_NUM_EXTINTERRUPTS 8 /* num of external interrupts */
|
||||
#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
|
||||
(not including level zero) */
|
||||
#define XCHAL_EXCM_LEVEL 5 /* level masked by PS.EXCM */
|
||||
/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
|
||||
|
||||
/* Masks of interrupts at each interrupt level: */
|
||||
#define XCHAL_INTLEVEL1_MASK 0x0000000F
|
||||
#define XCHAL_INTLEVEL2_MASK 0x000000F0
|
||||
#define XCHAL_INTLEVEL3_MASK 0x00000F00
|
||||
#define XCHAL_INTLEVEL4_MASK 0x00007000
|
||||
#define XCHAL_INTLEVEL5_MASK 0x000F8000
|
||||
#define XCHAL_INTLEVEL6_MASK 0x00000000
|
||||
#define XCHAL_INTLEVEL7_MASK 0x00100000
|
||||
|
||||
/* Masks of interrupts at each range 1..n of interrupt levels: */
|
||||
#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x0000000F
|
||||
#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x000000FF
|
||||
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x00000FFF
|
||||
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00007FFF
|
||||
#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x000FFFFF
|
||||
#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x000FFFFF
|
||||
#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x001FFFFF
|
||||
|
||||
/* Level of each interrupt: */
|
||||
#define XCHAL_INT0_LEVEL 1
|
||||
#define XCHAL_INT1_LEVEL 1
|
||||
#define XCHAL_INT2_LEVEL 1
|
||||
#define XCHAL_INT3_LEVEL 1
|
||||
#define XCHAL_INT4_LEVEL 2
|
||||
#define XCHAL_INT5_LEVEL 2
|
||||
#define XCHAL_INT6_LEVEL 2
|
||||
#define XCHAL_INT7_LEVEL 2
|
||||
#define XCHAL_INT8_LEVEL 3
|
||||
#define XCHAL_INT9_LEVEL 3
|
||||
#define XCHAL_INT10_LEVEL 3
|
||||
#define XCHAL_INT11_LEVEL 3
|
||||
#define XCHAL_INT12_LEVEL 4
|
||||
#define XCHAL_INT13_LEVEL 4
|
||||
#define XCHAL_INT14_LEVEL 4
|
||||
#define XCHAL_INT15_LEVEL 5
|
||||
#define XCHAL_INT16_LEVEL 5
|
||||
#define XCHAL_INT17_LEVEL 5
|
||||
#define XCHAL_INT18_LEVEL 5
|
||||
#define XCHAL_INT19_LEVEL 5
|
||||
#define XCHAL_INT20_LEVEL 7
|
||||
#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
|
||||
#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
|
||||
#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
|
||||
EXCSAVE/EPS/EPC_n, RFI n) */
|
||||
|
||||
/* Type of each interrupt: */
|
||||
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT1_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT3_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT4_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT5_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT8_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT9_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT12_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT14_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT15_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT19_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT20_TYPE XTHAL_INTTYPE_NMI
|
||||
|
||||
/* Masks of interrupts for each type of interrupt: */
|
||||
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFE00000
|
||||
#define XCHAL_INTTYPE_MASK_SOFTWARE 0x0008D999
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x00072444
|
||||
#define XCHAL_INTTYPE_MASK_TIMER 0x00000222
|
||||
#define XCHAL_INTTYPE_MASK_NMI 0x00100000
|
||||
#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000
|
||||
|
||||
/* Interrupt numbers assigned to specific interrupt sources: */
|
||||
#define XCHAL_TIMER0_INTERRUPT 1 /* CCOMPARE0 */
|
||||
#define XCHAL_TIMER1_INTERRUPT 5 /* CCOMPARE1 */
|
||||
#define XCHAL_TIMER2_INTERRUPT 9 /* CCOMPARE2 */
|
||||
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
|
||||
#define XCHAL_NMI_INTERRUPT 20 /* non-maskable interrupt */
|
||||
|
||||
/* Interrupt numbers for levels at which only one interrupt is configured: */
|
||||
#define XCHAL_INTLEVEL7_NUM 20
|
||||
/* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */
|
||||
|
||||
|
||||
/*
|
||||
* External interrupt mapping.
|
||||
* These macros describe how Xtensa processor interrupt numbers
|
||||
* (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
|
||||
* map to external BInterrupt<n> pins, for those interrupts
|
||||
* configured as external (level-triggered, edge-triggered, or NMI).
|
||||
* See the Xtensa processor databook for more details.
|
||||
*/
|
||||
|
||||
/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
|
||||
#define XCHAL_EXTINT0_NUM 2 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT1_NUM 6 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT2_NUM 10 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT3_NUM 13 /* (intlevel 4) */
|
||||
#define XCHAL_EXTINT4_NUM 16 /* (intlevel 5) */
|
||||
#define XCHAL_EXTINT5_NUM 17 /* (intlevel 5) */
|
||||
#define XCHAL_EXTINT6_NUM 18 /* (intlevel 5) */
|
||||
#define XCHAL_EXTINT7_NUM 20 /* (intlevel 7) */
|
||||
/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
|
||||
#define XCHAL_INT2_EXTNUM 0 /* (intlevel 1) */
|
||||
#define XCHAL_INT6_EXTNUM 1 /* (intlevel 2) */
|
||||
#define XCHAL_INT10_EXTNUM 2 /* (intlevel 3) */
|
||||
#define XCHAL_INT13_EXTNUM 3 /* (intlevel 4) */
|
||||
#define XCHAL_INT16_EXTNUM 4 /* (intlevel 5) */
|
||||
#define XCHAL_INT17_EXTNUM 5 /* (intlevel 5) */
|
||||
#define XCHAL_INT18_EXTNUM 6 /* (intlevel 5) */
|
||||
#define XCHAL_INT20_EXTNUM 7 /* (intlevel 7) */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
EXCEPTIONS and VECTORS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
|
||||
number: 1 == XEA1 (old)
|
||||
2 == XEA2 (new)
|
||||
0 == XEAX (extern) or TX */
|
||||
#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
|
||||
#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
|
||||
#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
|
||||
#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
|
||||
#define XCHAL_HAVE_HALT 0 /* halt architecture option */
|
||||
#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
|
||||
#define XCHAL_HAVE_MEM_ECC_PARITY 1 /* local memory ECC/parity */
|
||||
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
|
||||
#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
|
||||
#define XCHAL_VECBASE_RESET_VADDR 0x9F180800 /* VECBASE reset value */
|
||||
#define XCHAL_VECBASE_RESET_PADDR 0x9F180800
|
||||
#define XCHAL_RESET_VECBASE_OVERLAP 0
|
||||
|
||||
#define XCHAL_RESET_VECTOR0_VADDR 0x9F180000
|
||||
#define XCHAL_RESET_VECTOR0_PADDR 0x9F180000
|
||||
#define XCHAL_RESET_VECTOR1_VADDR 0xBE800000
|
||||
#define XCHAL_RESET_VECTOR1_PADDR 0xBE800000
|
||||
#define XCHAL_RESET_VECTOR_VADDR 0x9F180000
|
||||
#define XCHAL_RESET_VECTOR_PADDR 0x9F180000
|
||||
#define XCHAL_MEMERROR_VECTOR0_VADDR 0x9F180400
|
||||
#define XCHAL_MEMERROR_VECTOR0_PADDR 0x9F180400
|
||||
#define XCHAL_MEMERROR_VECTOR1_VADDR 0xBE800400
|
||||
#define XCHAL_MEMERROR_VECTOR1_PADDR 0xBE800400
|
||||
#define XCHAL_MEMERROR_VECTOR_VADDR 0x9F180400
|
||||
#define XCHAL_MEMERROR_VECTOR_PADDR 0x9F180400
|
||||
#define XCHAL_USER_VECOFS 0x00000340
|
||||
#define XCHAL_USER_VECTOR_VADDR 0x9F180B40
|
||||
#define XCHAL_USER_VECTOR_PADDR 0x9F180B40
|
||||
#define XCHAL_KERNEL_VECOFS 0x00000300
|
||||
#define XCHAL_KERNEL_VECTOR_VADDR 0x9F180B00
|
||||
#define XCHAL_KERNEL_VECTOR_PADDR 0x9F180B00
|
||||
#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x9F180BC0
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x9F180BC0
|
||||
#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
|
||||
#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
|
||||
#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
|
||||
#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
|
||||
#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
|
||||
#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
|
||||
#define XCHAL_WINDOW_VECTORS_VADDR 0x9F180800
|
||||
#define XCHAL_WINDOW_VECTORS_PADDR 0x9F180800
|
||||
#define XCHAL_INTLEVEL2_VECOFS 0x00000180
|
||||
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x9F180980
|
||||
#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x9F180980
|
||||
#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
|
||||
#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x9F1809C0
|
||||
#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x9F1809C0
|
||||
#define XCHAL_INTLEVEL4_VECOFS 0x00000200
|
||||
#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x9F180A00
|
||||
#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x9F180A00
|
||||
#define XCHAL_INTLEVEL5_VECOFS 0x00000240
|
||||
#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x9F180A40
|
||||
#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x9F180A40
|
||||
#define XCHAL_INTLEVEL6_VECOFS 0x00000280
|
||||
#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x9F180A80
|
||||
#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x9F180A80
|
||||
#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
|
||||
#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
|
||||
#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
|
||||
#define XCHAL_NMI_VECOFS 0x000002C0
|
||||
#define XCHAL_NMI_VECTOR_VADDR 0x9F180AC0
|
||||
#define XCHAL_NMI_VECTOR_PADDR 0x9F180AC0
|
||||
#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
|
||||
#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
|
||||
#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
DEBUG MODULE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* Misc */
|
||||
#define XCHAL_HAVE_DEBUG_ERI 0 /* ERI to debug module */
|
||||
#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */
|
||||
#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
|
||||
|
||||
/* On-Chip Debug (OCD) */
|
||||
#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
|
||||
#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
|
||||
#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
|
||||
#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */
|
||||
#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
|
||||
|
||||
/* TRAX (in core) */
|
||||
#define XCHAL_HAVE_TRAX 0 /* TRAX in debug module */
|
||||
#define XCHAL_TRAX_MEM_SIZE 0 /* TRAX memory size in bytes */
|
||||
#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */
|
||||
#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
|
||||
#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
|
||||
|
||||
/* Perf counters */
|
||||
#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MMU
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* See core-matmap.h header file for more details. */
|
||||
|
||||
#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
|
||||
#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
|
||||
#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */
|
||||
#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */
|
||||
#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
|
||||
#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
|
||||
#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
|
||||
#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
|
||||
[autorefill] and protection)
|
||||
usable for an MMU-based OS */
|
||||
|
||||
/* If none of the above last 5 are set, it's a custom TLB configuration. */
|
||||
|
||||
#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
|
||||
#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
|
||||
#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MPU
|
||||
----------------------------------------------------------------------*/
|
||||
#define XCHAL_HAVE_MPU 0
|
||||
#define XCHAL_MPU_ENTRIES 0
|
||||
|
||||
#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */
|
||||
#define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/
|
||||
#define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */
|
||||
|
||||
#define XCHAL_MPU_ALIGN_BITS 0
|
||||
#define XCHAL_MPU_ALIGN 0
|
||||
|
||||
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
|
||||
|
||||
|
||||
#endif /* _XTENSA_CORE_CONFIGURATION_H */
|
||||
|
||||
Loading…
Reference in New Issue