xtensa: Add nxp_rt600_adsp toolchain
Files taken from "nxp_rt600_RI23_11_newlib_linux.tgz" available from https://tensilicatools.com. Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
This commit is contained in:
Vit Stanicek
Stephanos Ioannidis
parent
29657c97e8
commit
15daabb558
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@ -61,6 +61,7 @@ on:
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- xtensa-nxp_imx8m_adsp_zephyr-elf
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- xtensa-nxp_imx8ulp_adsp_zephyr-elf
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- xtensa-nxp_rt500_adsp_zephyr-elf
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- xtensa-nxp_rt600_adsp_zephyr-elf
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- xtensa-sample_controller_zephyr-elf
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debug:
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description: 'Debug'
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@ -173,6 +174,7 @@ jobs:
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xtensa-nxp_imx8m_adsp_zephyr-elf) build_target_xtensa_nxp_imx8m_adsp_zephyr_elf="y";;
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xtensa-nxp_imx8ulp_adsp_zephyr-elf) build_target_xtensa_nxp_imx8ulp_adsp_zephyr_elf="y";;
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xtensa-nxp_rt500_adsp_zephyr-elf) build_target_xtensa_nxp_rt500_adsp_zephyr_elf="y";;
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xtensa-nxp_rt600_adsp_zephyr-elf) build_target_xtensa_nxp_rt600_adsp_zephyr_elf="y";;
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xtensa-sample_controller_zephyr-elf) build_target_xtensa_sample_controller_zephyr_elf="y";;
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esac
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@ -213,6 +215,7 @@ jobs:
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build_target_xtensa_nxp_imx8m_adsp_zephyr_elf="y"
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build_target_xtensa_nxp_imx8ulp_adsp_zephyr_elf="y"
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build_target_xtensa_nxp_rt500_adsp_zephyr_elf="y"
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build_target_xtensa_nxp_rt600_adsp_zephyr_elf="y"
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build_target_xtensa_sample_controller_zephyr_elf="y"
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fi
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@ -293,6 +296,7 @@ jobs:
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[ "${build_target_xtensa_nxp_imx8m_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-nxp_imx8m_adsp_zephyr-elf",'
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[ "${build_target_xtensa_nxp_imx8ulp_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-nxp_imx8ulp_adsp_zephyr-elf",'
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[ "${build_target_xtensa_nxp_rt500_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-nxp_rt500_adsp_zephyr-elf",'
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[ "${build_target_xtensa_nxp_rt600_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-nxp_rt600_adsp_zephyr-elf",'
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[ "${build_target_xtensa_sample_controller_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-sample_controller_zephyr-elf",'
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MATRIX_TARGETS+=']'
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@ -0,0 +1,10 @@
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CT_CONFIG_VERSION="3"
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CT_EXPERIMENTAL=y
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CT_OVERLAY_LOCATION="overlays"
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CT_OVERLAY_NAME="nxp_rt600_adsp"
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CT_ARCH_XTENSA=y
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CT_XTENSA_CUSTOM=y
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CT_TARGET_VENDOR="nxp_rt600_adsp_zephyr"
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CT_TARGET_CFLAGS="-ftls-model=local-exec"
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CT_CC_GCC_CONFIG_TLS=n
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CT_GDB_CROSS_EXTRA_CONFIG_ARRAY="--enable-xtensa-use-target-regnum --disable-xtensa-remote-g-packet"
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,189 @@
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/* Xtensa configuration settings.
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Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
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Free Software Foundation, Inc.
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Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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#ifndef XTENSA_CONFIG_H
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#define XTENSA_CONFIG_H
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/* The macros defined here match those with the same names in the Xtensa
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compile-time HAL (Hardware Abstraction Layer). Please refer to the
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Xtensa System Software Reference Manual for documentation of these
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macros. */
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#undef XCHAL_HAVE_BE
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#define XCHAL_HAVE_BE 0
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#undef XCHAL_HAVE_DENSITY
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#define XCHAL_HAVE_DENSITY 1
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#undef XCHAL_HAVE_CONST16
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#define XCHAL_HAVE_CONST16 0
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#undef XCHAL_HAVE_ABS
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#define XCHAL_HAVE_ABS 1
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#undef XCHAL_HAVE_ADDX
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#define XCHAL_HAVE_ADDX 1
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#undef XCHAL_HAVE_L32R
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#define XCHAL_HAVE_L32R 1
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#undef XSHAL_USE_ABSOLUTE_LITERALS
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#define XSHAL_USE_ABSOLUTE_LITERALS 0
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#undef XSHAL_HAVE_TEXT_SECTION_LITERALS
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#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
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#undef XCHAL_HAVE_MAC16
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#define XCHAL_HAVE_MAC16 1
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#undef XCHAL_HAVE_MUL16
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#define XCHAL_HAVE_MUL16 1
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#undef XCHAL_HAVE_MUL32
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#define XCHAL_HAVE_MUL32 1
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#undef XCHAL_HAVE_MUL32_HIGH
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#define XCHAL_HAVE_MUL32_HIGH 1
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#undef XCHAL_HAVE_DIV32
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#define XCHAL_HAVE_DIV32 1
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#undef XCHAL_HAVE_NSA
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#define XCHAL_HAVE_NSA 1
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#undef XCHAL_HAVE_MINMAX
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#define XCHAL_HAVE_MINMAX 1
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#undef XCHAL_HAVE_SEXT
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#define XCHAL_HAVE_SEXT 1
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#undef XCHAL_HAVE_LOOPS
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#define XCHAL_HAVE_LOOPS 1
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#undef XCHAL_HAVE_THREADPTR
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#define XCHAL_HAVE_THREADPTR 1
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#undef XCHAL_HAVE_RELEASE_SYNC
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#define XCHAL_HAVE_RELEASE_SYNC 1
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#undef XCHAL_HAVE_S32C1I
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#define XCHAL_HAVE_S32C1I 1
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#undef XCHAL_HAVE_BOOLEANS
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#define XCHAL_HAVE_BOOLEANS 1
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#undef XCHAL_HAVE_FP
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#define XCHAL_HAVE_FP 0
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#undef XCHAL_HAVE_FP_DIV
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#define XCHAL_HAVE_FP_DIV 0
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#undef XCHAL_HAVE_FP_RECIP
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#define XCHAL_HAVE_FP_RECIP 0
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#undef XCHAL_HAVE_FP_SQRT
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#define XCHAL_HAVE_FP_SQRT 0
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#undef XCHAL_HAVE_FP_RSQRT
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#define XCHAL_HAVE_FP_RSQRT 0
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#undef XCHAL_HAVE_DFP_ACCEL
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#define XCHAL_HAVE_DFP_ACCEL 1
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/* For backward compatibility */
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#undef XCHAL_HAVE_DFP_accel
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#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL
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#undef XCHAL_HAVE_WINDOWED
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#define XCHAL_HAVE_WINDOWED 1
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#undef XCHAL_NUM_AREGS
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#define XCHAL_NUM_AREGS 32
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#undef XCHAL_HAVE_WIDE_BRANCHES
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#define XCHAL_HAVE_WIDE_BRANCHES 0
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#undef XCHAL_HAVE_PREDICTED_BRANCHES
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#define XCHAL_HAVE_PREDICTED_BRANCHES 0
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#undef XCHAL_ICACHE_SIZE
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#define XCHAL_ICACHE_SIZE 32768
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#undef XCHAL_DCACHE_SIZE
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#define XCHAL_DCACHE_SIZE 65536
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#undef XCHAL_ICACHE_LINESIZE
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#define XCHAL_ICACHE_LINESIZE 256
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#undef XCHAL_DCACHE_LINESIZE
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#define XCHAL_DCACHE_LINESIZE 256
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#undef XCHAL_ICACHE_LINEWIDTH
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#define XCHAL_ICACHE_LINEWIDTH 8
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#undef XCHAL_DCACHE_LINEWIDTH
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#define XCHAL_DCACHE_LINEWIDTH 8
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#undef XCHAL_DCACHE_IS_WRITEBACK
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#define XCHAL_DCACHE_IS_WRITEBACK 1
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#undef XCHAL_HAVE_MMU
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#define XCHAL_HAVE_MMU 0
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#undef XCHAL_HAVE_DEBUG
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#define XCHAL_HAVE_DEBUG 1
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#undef XCHAL_NUM_IBREAK
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#define XCHAL_NUM_IBREAK 2
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#undef XCHAL_NUM_DBREAK
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#define XCHAL_NUM_DBREAK 2
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#undef XCHAL_DEBUGLEVEL
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#define XCHAL_DEBUGLEVEL 4
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#undef XCHAL_MAX_INSTRUCTION_SIZE
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#define XCHAL_MAX_INSTRUCTION_SIZE 11
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#undef XCHAL_INST_FETCH_WIDTH
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#define XCHAL_INST_FETCH_WIDTH 16
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#undef XSHAL_ABI
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#undef XTHAL_ABI_WINDOWED
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#undef XTHAL_ABI_CALL0
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#define XSHAL_ABI XTHAL_ABI_WINDOWED
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#define XTHAL_ABI_WINDOWED 0
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#define XTHAL_ABI_CALL0 1
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#undef XCHAL_M_STAGE
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#define XCHAL_M_STAGE 3
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#undef XTENSA_MARCH_LATEST
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#define XTENSA_MARCH_LATEST 260004
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#undef XTENSA_MARCH_EARLIEST
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#define XTENSA_MARCH_EARLIEST 260004
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#endif /* !XTENSA_CONFIG_H */
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@ -0,0 +1,189 @@
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/* Xtensa configuration settings.
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Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
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Free Software Foundation, Inc.
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Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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#ifndef XTENSA_CONFIG_H
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#define XTENSA_CONFIG_H
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/* The macros defined here match those with the same names in the Xtensa
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compile-time HAL (Hardware Abstraction Layer). Please refer to the
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Xtensa System Software Reference Manual for documentation of these
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macros. */
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#undef XCHAL_HAVE_BE
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#define XCHAL_HAVE_BE 0
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#undef XCHAL_HAVE_DENSITY
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#define XCHAL_HAVE_DENSITY 1
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#undef XCHAL_HAVE_CONST16
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#define XCHAL_HAVE_CONST16 0
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#undef XCHAL_HAVE_ABS
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#define XCHAL_HAVE_ABS 1
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#undef XCHAL_HAVE_ADDX
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#define XCHAL_HAVE_ADDX 1
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#undef XCHAL_HAVE_L32R
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#define XCHAL_HAVE_L32R 1
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#undef XSHAL_USE_ABSOLUTE_LITERALS
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#define XSHAL_USE_ABSOLUTE_LITERALS 0
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#undef XSHAL_HAVE_TEXT_SECTION_LITERALS
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#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
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#undef XCHAL_HAVE_MAC16
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#define XCHAL_HAVE_MAC16 1
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#undef XCHAL_HAVE_MUL16
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#define XCHAL_HAVE_MUL16 1
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#undef XCHAL_HAVE_MUL32
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#define XCHAL_HAVE_MUL32 1
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#undef XCHAL_HAVE_MUL32_HIGH
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#define XCHAL_HAVE_MUL32_HIGH 1
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#undef XCHAL_HAVE_DIV32
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#define XCHAL_HAVE_DIV32 1
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#undef XCHAL_HAVE_NSA
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#define XCHAL_HAVE_NSA 1
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#undef XCHAL_HAVE_MINMAX
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#define XCHAL_HAVE_MINMAX 1
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#undef XCHAL_HAVE_SEXT
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#define XCHAL_HAVE_SEXT 1
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#undef XCHAL_HAVE_LOOPS
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#define XCHAL_HAVE_LOOPS 1
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#undef XCHAL_HAVE_THREADPTR
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#define XCHAL_HAVE_THREADPTR 1
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#undef XCHAL_HAVE_RELEASE_SYNC
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#define XCHAL_HAVE_RELEASE_SYNC 1
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#undef XCHAL_HAVE_S32C1I
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#define XCHAL_HAVE_S32C1I 1
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#undef XCHAL_HAVE_BOOLEANS
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#define XCHAL_HAVE_BOOLEANS 1
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#undef XCHAL_HAVE_FP
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#define XCHAL_HAVE_FP 0
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#undef XCHAL_HAVE_FP_DIV
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#define XCHAL_HAVE_FP_DIV 0
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|
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#undef XCHAL_HAVE_FP_RECIP
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#define XCHAL_HAVE_FP_RECIP 0
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#undef XCHAL_HAVE_FP_SQRT
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#define XCHAL_HAVE_FP_SQRT 0
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#undef XCHAL_HAVE_FP_RSQRT
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#define XCHAL_HAVE_FP_RSQRT 0
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|
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#undef XCHAL_HAVE_DFP_ACCEL
|
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#define XCHAL_HAVE_DFP_ACCEL 1
|
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/* For backward compatibility */
|
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#undef XCHAL_HAVE_DFP_accel
|
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#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL
|
||||
|
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#undef XCHAL_HAVE_WINDOWED
|
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#define XCHAL_HAVE_WINDOWED 1
|
||||
|
||||
#undef XCHAL_NUM_AREGS
|
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#define XCHAL_NUM_AREGS 32
|
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|
||||
#undef XCHAL_HAVE_WIDE_BRANCHES
|
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#define XCHAL_HAVE_WIDE_BRANCHES 0
|
||||
|
||||
#undef XCHAL_HAVE_PREDICTED_BRANCHES
|
||||
#define XCHAL_HAVE_PREDICTED_BRANCHES 0
|
||||
|
||||
|
||||
#undef XCHAL_ICACHE_SIZE
|
||||
#define XCHAL_ICACHE_SIZE 32768
|
||||
|
||||
#undef XCHAL_DCACHE_SIZE
|
||||
#define XCHAL_DCACHE_SIZE 65536
|
||||
|
||||
#undef XCHAL_ICACHE_LINESIZE
|
||||
#define XCHAL_ICACHE_LINESIZE 256
|
||||
|
||||
#undef XCHAL_DCACHE_LINESIZE
|
||||
#define XCHAL_DCACHE_LINESIZE 256
|
||||
|
||||
#undef XCHAL_ICACHE_LINEWIDTH
|
||||
#define XCHAL_ICACHE_LINEWIDTH 8
|
||||
|
||||
#undef XCHAL_DCACHE_LINEWIDTH
|
||||
#define XCHAL_DCACHE_LINEWIDTH 8
|
||||
|
||||
#undef XCHAL_DCACHE_IS_WRITEBACK
|
||||
#define XCHAL_DCACHE_IS_WRITEBACK 1
|
||||
|
||||
|
||||
#undef XCHAL_HAVE_MMU
|
||||
#define XCHAL_HAVE_MMU 0
|
||||
|
||||
|
||||
#undef XCHAL_HAVE_DEBUG
|
||||
#define XCHAL_HAVE_DEBUG 1
|
||||
|
||||
#undef XCHAL_NUM_IBREAK
|
||||
#define XCHAL_NUM_IBREAK 2
|
||||
|
||||
#undef XCHAL_NUM_DBREAK
|
||||
#define XCHAL_NUM_DBREAK 2
|
||||
|
||||
#undef XCHAL_DEBUGLEVEL
|
||||
#define XCHAL_DEBUGLEVEL 4
|
||||
|
||||
|
||||
#undef XCHAL_MAX_INSTRUCTION_SIZE
|
||||
#define XCHAL_MAX_INSTRUCTION_SIZE 11
|
||||
|
||||
#undef XCHAL_INST_FETCH_WIDTH
|
||||
#define XCHAL_INST_FETCH_WIDTH 16
|
||||
|
||||
|
||||
#undef XSHAL_ABI
|
||||
#undef XTHAL_ABI_WINDOWED
|
||||
#undef XTHAL_ABI_CALL0
|
||||
#define XSHAL_ABI XTHAL_ABI_WINDOWED
|
||||
#define XTHAL_ABI_WINDOWED 0
|
||||
#define XTHAL_ABI_CALL0 1
|
||||
|
||||
|
||||
#undef XCHAL_M_STAGE
|
||||
#define XCHAL_M_STAGE 3
|
||||
|
||||
#undef XTENSA_MARCH_LATEST
|
||||
#define XTENSA_MARCH_LATEST 260004
|
||||
|
||||
#undef XTENSA_MARCH_EARLIEST
|
||||
#define XTENSA_MARCH_EARLIEST 260004
|
||||
|
||||
|
||||
#endif /* !XTENSA_CONFIG_H */
|
||||
File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,86 @@
|
|||
/* Customized table mapping between kernel xtregset and GDB register cache.
|
||||
|
||||
Copyright (c) 2007-2010 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
|
||||
typedef struct {
|
||||
int gdb_regnum;
|
||||
int gdb_offset;
|
||||
int ptrace_cp_offset;
|
||||
int ptrace_offset;
|
||||
int size;
|
||||
int coproc;
|
||||
int dbnum;
|
||||
char* name
|
||||
;} xtensa_regtable_t;
|
||||
|
||||
#define XTENSA_ELF_XTREG_SIZE 256
|
||||
|
||||
const xtensa_regtable_t xtensa_regmap_table[] = {
|
||||
/* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */
|
||||
{ 44, 176, 8, 8, 4, -1, 0x0204, "br" },
|
||||
{ 45, 180, 12, 12, 4, -1, 0x020c, "scompare1" },
|
||||
{ 46, 184, 0, 0, 4, -1, 0x0210, "acclo" },
|
||||
{ 47, 188, 4, 4, 4, -1, 0x0211, "acchi" },
|
||||
{ 48, 192, 16, 16, 4, -1, 0x0220, "m0" },
|
||||
{ 49, 196, 20, 20, 4, -1, 0x0221, "m1" },
|
||||
{ 50, 200, 24, 24, 4, -1, 0x0222, "m2" },
|
||||
{ 51, 204, 28, 28, 4, -1, 0x0223, "m3" },
|
||||
{ 53, 212, 32, 32, 4, -1, 0x03ea, "f64r_lo" },
|
||||
{ 54, 216, 36, 36, 4, -1, 0x03eb, "f64r_hi" },
|
||||
{ 55, 220, 40, 40, 4, -1, 0x03ec, "f64s" },
|
||||
{ 56, 224, 8, 56, 4, 1, 0x03f0, "ae_ovf_sar" },
|
||||
{ 57, 228, 12, 60, 4, 1, 0x03f1, "ae_bithead" },
|
||||
{ 58, 232, 16, 64, 4, 1, 0x03f2, "ae_ts_fts_bu_bp" },
|
||||
{ 59, 236, 20, 68, 4, 1, 0x03f3, "ae_cw_sd_no" },
|
||||
{ 60, 240, 24, 72, 4, 1, 0x03f6, "ae_cbegin0" },
|
||||
{ 61, 244, 28, 76, 4, 1, 0x03f7, "ae_cend0" },
|
||||
{ 62, 248, 32, 80, 4, 1, 0x03f8, "ae_cbegin1" },
|
||||
{ 63, 252, 36, 84, 4, 1, 0x03f9, "ae_cend1" },
|
||||
{ 64, 256, 40, 88, 8, 1, 0x1010, "aed0" },
|
||||
{ 65, 264, 48, 96, 8, 1, 0x1011, "aed1" },
|
||||
{ 66, 272, 56, 104, 8, 1, 0x1012, "aed2" },
|
||||
{ 67, 280, 64, 112, 8, 1, 0x1013, "aed3" },
|
||||
{ 68, 288, 72, 120, 8, 1, 0x1014, "aed4" },
|
||||
{ 69, 296, 80, 128, 8, 1, 0x1015, "aed5" },
|
||||
{ 70, 304, 88, 136, 8, 1, 0x1016, "aed6" },
|
||||
{ 71, 312, 96, 144, 8, 1, 0x1017, "aed7" },
|
||||
{ 72, 320, 104, 152, 8, 1, 0x1018, "aed8" },
|
||||
{ 73, 328, 112, 160, 8, 1, 0x1019, "aed9" },
|
||||
{ 74, 336, 120, 168, 8, 1, 0x101a, "aed10" },
|
||||
{ 75, 344, 128, 176, 8, 1, 0x101b, "aed11" },
|
||||
{ 76, 352, 136, 184, 8, 1, 0x101c, "aed12" },
|
||||
{ 77, 360, 144, 192, 8, 1, 0x101d, "aed13" },
|
||||
{ 78, 368, 152, 200, 8, 1, 0x101e, "aed14" },
|
||||
{ 79, 376, 160, 208, 8, 1, 0x101f, "aed15" },
|
||||
{ 80, 384, 176, 224, 8, 1, 0x1020, "u0" },
|
||||
{ 81, 392, 184, 232, 8, 1, 0x1021, "u1" },
|
||||
{ 82, 400, 192, 240, 8, 1, 0x1022, "u2" },
|
||||
{ 83, 408, 200, 248, 8, 1, 0x1023, "u3" },
|
||||
{ 84, 416, 168, 216, 1, 1, 0x1024, "aep0" },
|
||||
{ 85, 417, 169, 217, 1, 1, 0x1025, "aep1" },
|
||||
{ 86, 418, 170, 218, 1, 1, 0x1026, "aep2" },
|
||||
{ 87, 419, 171, 219, 1, 1, 0x1027, "aep3" },
|
||||
{ 88, 420, 0, 48, 4, 1, 0x1029, "fcr_fsr" },
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
/* Customized table mapping between kernel xtregset and GDB register cache.
|
||||
|
||||
Copyright (c) 2007-2010 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
|
||||
typedef struct {
|
||||
int gdb_regnum;
|
||||
int gdb_offset;
|
||||
int ptrace_cp_offset;
|
||||
int ptrace_offset;
|
||||
int size;
|
||||
int coproc;
|
||||
int dbnum;
|
||||
char* name
|
||||
;} xtensa_regtable_t;
|
||||
|
||||
#define XTENSA_ELF_XTREG_SIZE 256
|
||||
|
||||
const xtensa_regtable_t xtensa_regmap_table[] = {
|
||||
/* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */
|
||||
{ 44, 176, 8, 8, 4, -1, 0x0204, "br" },
|
||||
{ 45, 180, 12, 12, 4, -1, 0x020c, "scompare1" },
|
||||
{ 46, 184, 0, 0, 4, -1, 0x0210, "acclo" },
|
||||
{ 47, 188, 4, 4, 4, -1, 0x0211, "acchi" },
|
||||
{ 48, 192, 16, 16, 4, -1, 0x0220, "m0" },
|
||||
{ 49, 196, 20, 20, 4, -1, 0x0221, "m1" },
|
||||
{ 50, 200, 24, 24, 4, -1, 0x0222, "m2" },
|
||||
{ 51, 204, 28, 28, 4, -1, 0x0223, "m3" },
|
||||
{ 53, 212, 32, 32, 4, -1, 0x03ea, "f64r_lo" },
|
||||
{ 54, 216, 36, 36, 4, -1, 0x03eb, "f64r_hi" },
|
||||
{ 55, 220, 40, 40, 4, -1, 0x03ec, "f64s" },
|
||||
{ 56, 224, 8, 56, 4, 1, 0x03f0, "ae_ovf_sar" },
|
||||
{ 57, 228, 12, 60, 4, 1, 0x03f1, "ae_bithead" },
|
||||
{ 58, 232, 16, 64, 4, 1, 0x03f2, "ae_ts_fts_bu_bp" },
|
||||
{ 59, 236, 20, 68, 4, 1, 0x03f3, "ae_cw_sd_no" },
|
||||
{ 60, 240, 24, 72, 4, 1, 0x03f6, "ae_cbegin0" },
|
||||
{ 61, 244, 28, 76, 4, 1, 0x03f7, "ae_cend0" },
|
||||
{ 62, 248, 32, 80, 4, 1, 0x03f8, "ae_cbegin1" },
|
||||
{ 63, 252, 36, 84, 4, 1, 0x03f9, "ae_cend1" },
|
||||
{ 64, 256, 40, 88, 8, 1, 0x1010, "aed0" },
|
||||
{ 65, 264, 48, 96, 8, 1, 0x1011, "aed1" },
|
||||
{ 66, 272, 56, 104, 8, 1, 0x1012, "aed2" },
|
||||
{ 67, 280, 64, 112, 8, 1, 0x1013, "aed3" },
|
||||
{ 68, 288, 72, 120, 8, 1, 0x1014, "aed4" },
|
||||
{ 69, 296, 80, 128, 8, 1, 0x1015, "aed5" },
|
||||
{ 70, 304, 88, 136, 8, 1, 0x1016, "aed6" },
|
||||
{ 71, 312, 96, 144, 8, 1, 0x1017, "aed7" },
|
||||
{ 72, 320, 104, 152, 8, 1, 0x1018, "aed8" },
|
||||
{ 73, 328, 112, 160, 8, 1, 0x1019, "aed9" },
|
||||
{ 74, 336, 120, 168, 8, 1, 0x101a, "aed10" },
|
||||
{ 75, 344, 128, 176, 8, 1, 0x101b, "aed11" },
|
||||
{ 76, 352, 136, 184, 8, 1, 0x101c, "aed12" },
|
||||
{ 77, 360, 144, 192, 8, 1, 0x101d, "aed13" },
|
||||
{ 78, 368, 152, 200, 8, 1, 0x101e, "aed14" },
|
||||
{ 79, 376, 160, 208, 8, 1, 0x101f, "aed15" },
|
||||
{ 80, 384, 176, 224, 8, 1, 0x1020, "u0" },
|
||||
{ 81, 392, 184, 232, 8, 1, 0x1021, "u1" },
|
||||
{ 82, 400, 192, 240, 8, 1, 0x1022, "u2" },
|
||||
{ 83, 408, 200, 248, 8, 1, 0x1023, "u3" },
|
||||
{ 84, 416, 168, 216, 1, 1, 0x1024, "aep0" },
|
||||
{ 85, 417, 169, 217, 1, 1, 0x1025, "aep1" },
|
||||
{ 86, 418, 170, 218, 1, 1, 0x1026, "aep2" },
|
||||
{ 87, 419, 171, 219, 1, 1, 0x1027, "aep3" },
|
||||
{ 88, 420, 0, 48, 4, 1, 0x1029, "fcr_fsr" },
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
name:xtensa
|
||||
expedite:pc,windowbase,windowstart
|
||||
32:pc
|
||||
32:ar0
|
||||
32:ar1
|
||||
32:ar2
|
||||
32:ar3
|
||||
32:ar4
|
||||
32:ar5
|
||||
32:ar6
|
||||
32:ar7
|
||||
32:ar8
|
||||
32:ar9
|
||||
32:ar10
|
||||
32:ar11
|
||||
32:ar12
|
||||
32:ar13
|
||||
32:ar14
|
||||
32:ar15
|
||||
32:ar16
|
||||
32:ar17
|
||||
32:ar18
|
||||
32:ar19
|
||||
32:ar20
|
||||
32:ar21
|
||||
32:ar22
|
||||
32:ar23
|
||||
32:ar24
|
||||
32:ar25
|
||||
32:ar26
|
||||
32:ar27
|
||||
32:ar28
|
||||
32:ar29
|
||||
32:ar30
|
||||
32:ar31
|
||||
32:lbeg
|
||||
32:lend
|
||||
32:lcount
|
||||
32:sar
|
||||
32:prefctl
|
||||
32:windowbase
|
||||
32:windowstart
|
||||
32:configid0
|
||||
32:configid1
|
||||
32:ps
|
||||
32:threadptr
|
||||
32:br
|
||||
32:scompare1
|
||||
32:acclo
|
||||
32:acchi
|
||||
32:m0
|
||||
32:m1
|
||||
32:m2
|
||||
32:m3
|
||||
32:expstate
|
||||
32:f64r_lo
|
||||
32:f64r_hi
|
||||
32:f64s
|
||||
32:ae_ovf_sar
|
||||
32:ae_bithead
|
||||
32:ae_ts_fts_bu_bp
|
||||
32:ae_cw_sd_no
|
||||
32:ae_cbegin0
|
||||
32:ae_cend0
|
||||
32:ae_cbegin1
|
||||
32:ae_cend1
|
||||
64:aed0
|
||||
64:aed1
|
||||
64:aed2
|
||||
64:aed3
|
||||
64:aed4
|
||||
64:aed5
|
||||
64:aed6
|
||||
64:aed7
|
||||
64:aed8
|
||||
64:aed9
|
||||
64:aed10
|
||||
64:aed11
|
||||
64:aed12
|
||||
64:aed13
|
||||
64:aed14
|
||||
64:aed15
|
||||
64:u0
|
||||
64:u1
|
||||
64:u2
|
||||
64:u3
|
||||
8:aep0
|
||||
8:aep1
|
||||
8:aep2
|
||||
8:aep3
|
||||
32:fcr_fsr
|
||||
|
|
@ -0,0 +1,421 @@
|
|||
/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
|
||||
|
||||
Copyright (c) 2003-2023 Cadence Design Systems, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#define XTENSA_CONFIG_VERSION 0x70
|
||||
|
||||
#include "defs.h"
|
||||
#include "xtensa-config.h"
|
||||
#include "xtensa-tdep.h"
|
||||
|
||||
|
||||
|
||||
/* Masked registers. */
|
||||
xtensa_reg_mask_t xtensa_submask0[] = { { 44, 0, 1 } };
|
||||
const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 };
|
||||
xtensa_reg_mask_t xtensa_submask1[] = { { 44, 1, 1 } };
|
||||
const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 };
|
||||
xtensa_reg_mask_t xtensa_submask2[] = { { 44, 2, 1 } };
|
||||
const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 };
|
||||
xtensa_reg_mask_t xtensa_submask3[] = { { 44, 3, 1 } };
|
||||
const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 };
|
||||
xtensa_reg_mask_t xtensa_submask4[] = { { 44, 4, 1 } };
|
||||
const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 };
|
||||
xtensa_reg_mask_t xtensa_submask5[] = { { 44, 5, 1 } };
|
||||
const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 };
|
||||
xtensa_reg_mask_t xtensa_submask6[] = { { 44, 6, 1 } };
|
||||
const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 };
|
||||
xtensa_reg_mask_t xtensa_submask7[] = { { 44, 7, 1 } };
|
||||
const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 };
|
||||
xtensa_reg_mask_t xtensa_submask8[] = { { 44, 8, 1 } };
|
||||
const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 };
|
||||
xtensa_reg_mask_t xtensa_submask9[] = { { 44, 9, 1 } };
|
||||
const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 };
|
||||
xtensa_reg_mask_t xtensa_submask10[] = { { 44, 10, 1 } };
|
||||
const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 };
|
||||
xtensa_reg_mask_t xtensa_submask11[] = { { 44, 11, 1 } };
|
||||
const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 };
|
||||
xtensa_reg_mask_t xtensa_submask12[] = { { 44, 12, 1 } };
|
||||
const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 };
|
||||
xtensa_reg_mask_t xtensa_submask13[] = { { 44, 13, 1 } };
|
||||
const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 };
|
||||
xtensa_reg_mask_t xtensa_submask14[] = { { 44, 14, 1 } };
|
||||
const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 };
|
||||
xtensa_reg_mask_t xtensa_submask15[] = { { 44, 15, 1 } };
|
||||
const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 };
|
||||
xtensa_reg_mask_t xtensa_submask16[] = { { 42, 0, 4 } };
|
||||
const xtensa_mask_t xtensa_mask16 = { 1, xtensa_submask16 };
|
||||
xtensa_reg_mask_t xtensa_submask17[] = { { 42, 5, 1 } };
|
||||
const xtensa_mask_t xtensa_mask17 = { 1, xtensa_submask17 };
|
||||
xtensa_reg_mask_t xtensa_submask18[] = { { 42, 18, 1 } };
|
||||
const xtensa_mask_t xtensa_mask18 = { 1, xtensa_submask18 };
|
||||
xtensa_reg_mask_t xtensa_submask19[] = { { 42, 4, 1 } };
|
||||
const xtensa_mask_t xtensa_mask19 = { 1, xtensa_submask19 };
|
||||
xtensa_reg_mask_t xtensa_submask20[] = { { 42, 16, 2 } };
|
||||
const xtensa_mask_t xtensa_mask20 = { 1, xtensa_submask20 };
|
||||
xtensa_reg_mask_t xtensa_submask21[] = { { 42, 8, 4 } };
|
||||
const xtensa_mask_t xtensa_mask21 = { 1, xtensa_submask21 };
|
||||
xtensa_reg_mask_t xtensa_submask22[] = { { 46, 0, 32 }, { 47, 0, 8 } };
|
||||
const xtensa_mask_t xtensa_mask22 = { 2, xtensa_submask22 };
|
||||
xtensa_reg_mask_t xtensa_submask23[] = { { 122, 8, 4 } };
|
||||
const xtensa_mask_t xtensa_mask23 = { 1, xtensa_submask23 };
|
||||
xtensa_reg_mask_t xtensa_submask24[] = { { 56, 7, 1 } };
|
||||
const xtensa_mask_t xtensa_mask24 = { 1, xtensa_submask24 };
|
||||
xtensa_reg_mask_t xtensa_submask25[] = { { 56, 0, 7 }, { 56, 8, 7 } };
|
||||
const xtensa_mask_t xtensa_mask25 = { 2, xtensa_submask25 };
|
||||
xtensa_reg_mask_t xtensa_submask26[] = { { 59, 28, 1 } };
|
||||
const xtensa_mask_t xtensa_mask26 = { 1, xtensa_submask26 };
|
||||
xtensa_reg_mask_t xtensa_submask27[] = { { 58, 0, 4 } };
|
||||
const xtensa_mask_t xtensa_mask27 = { 1, xtensa_submask27 };
|
||||
xtensa_reg_mask_t xtensa_submask28[] = { { 58, 4, 4 } };
|
||||
const xtensa_mask_t xtensa_mask28 = { 1, xtensa_submask28 };
|
||||
xtensa_reg_mask_t xtensa_submask29[] = { { 58, 12, 4 } };
|
||||
const xtensa_mask_t xtensa_mask29 = { 1, xtensa_submask29 };
|
||||
xtensa_reg_mask_t xtensa_submask30[] = { { 58, 8, 4 } };
|
||||
const xtensa_mask_t xtensa_mask30 = { 1, xtensa_submask30 };
|
||||
xtensa_reg_mask_t xtensa_submask31[] = { { 59, 0, 27 } };
|
||||
const xtensa_mask_t xtensa_mask31 = { 1, xtensa_submask31 };
|
||||
xtensa_reg_mask_t xtensa_submask32[] = { { 59, 27, 1 } };
|
||||
const xtensa_mask_t xtensa_mask32 = { 1, xtensa_submask32 };
|
||||
xtensa_reg_mask_t xtensa_submask33[] = { { 88, 5, 2 } };
|
||||
const xtensa_mask_t xtensa_mask33 = { 1, xtensa_submask33 };
|
||||
xtensa_reg_mask_t xtensa_submask34[] = { { 88, 4, 1 } };
|
||||
const xtensa_mask_t xtensa_mask34 = { 1, xtensa_submask34 };
|
||||
xtensa_reg_mask_t xtensa_submask35[] = { { 88, 3, 1 } };
|
||||
const xtensa_mask_t xtensa_mask35 = { 1, xtensa_submask35 };
|
||||
xtensa_reg_mask_t xtensa_submask36[] = { { 88, 2, 1 } };
|
||||
const xtensa_mask_t xtensa_mask36 = { 1, xtensa_submask36 };
|
||||
xtensa_reg_mask_t xtensa_submask37[] = { { 88, 1, 1 } };
|
||||
const xtensa_mask_t xtensa_mask37 = { 1, xtensa_submask37 };
|
||||
xtensa_reg_mask_t xtensa_submask38[] = { { 88, 0, 1 } };
|
||||
const xtensa_mask_t xtensa_mask38 = { 1, xtensa_submask38 };
|
||||
xtensa_reg_mask_t xtensa_submask39[] = { { 53, 0, 32 }, { 54, 0, 32 } };
|
||||
const xtensa_mask_t xtensa_mask39 = { 2, xtensa_submask39 };
|
||||
|
||||
|
||||
/* Register map. */
|
||||
xtensa_register_t rmap[] =
|
||||
{
|
||||
/* idx ofs bi sz al targno flags cp typ group name */
|
||||
XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x2100,pc, 0,0,0,0,0,0)
|
||||
XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
|
||||
XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
|
||||
XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
|
||||
XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
|
||||
XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
|
||||
XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
|
||||
XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
|
||||
XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
|
||||
XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
|
||||
XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0)
|
||||
XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0)
|
||||
XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0)
|
||||
XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0)
|
||||
XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0)
|
||||
XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0)
|
||||
XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0)
|
||||
XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0)
|
||||
XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0)
|
||||
XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0)
|
||||
XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0)
|
||||
XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0)
|
||||
XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0)
|
||||
XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0)
|
||||
XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0)
|
||||
XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0)
|
||||
XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0)
|
||||
XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0)
|
||||
XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0)
|
||||
XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0)
|
||||
XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
|
||||
XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
|
||||
XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
|
||||
XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0)
|
||||
XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0)
|
||||
XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0)
|
||||
XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
|
||||
XTREG( 37,148,20, 4, 4,0x0228,0x0006,-2, 2,0x1100,prefctl, 0,0,0,0,0,0)
|
||||
XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
|
||||
XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
|
||||
XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0)
|
||||
XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0)
|
||||
XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
|
||||
XTREG( 43,172,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0)
|
||||
XTREG( 44,176,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0)
|
||||
XTREG( 45,180,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
|
||||
XTREG( 46,184,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo, 0,0,0,0,0,0)
|
||||
XTREG( 47,188, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi, 0,0,0,0,0,0)
|
||||
XTREG( 48,192,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0, 0,0,0,0,0,0)
|
||||
XTREG( 49,196,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1, 0,0,0,0,0,0)
|
||||
XTREG( 50,200,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, 0,0,0,0,0,0)
|
||||
XTREG( 51,204,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3, 0,0,0,0,0,0)
|
||||
XTREG( 52,208,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0)
|
||||
XTREG( 53,212,32, 4, 4,0x03ea,0x0006,-1, 3,0x0100,f64r_lo, 0,0,0,0,0,0)
|
||||
XTREG( 54,216,32, 4, 4,0x03eb,0x0006,-1, 3,0x0100,f64r_hi, 0,0,0,0,0,0)
|
||||
XTREG( 55,220,32, 4, 4,0x03ec,0x0006,-1, 3,0x0110,f64s, 0,0,0,0,0,0)
|
||||
XTREG( 56,224,15, 4, 4,0x03f0,0x0006, 1, 3,0x0100,ae_ovf_sar, 0,0,0,0,0,0)
|
||||
XTREG( 57,228,32, 4, 4,0x03f1,0x0006, 1, 3,0x0110,ae_bithead, 0,0,0,0,0,0)
|
||||
XTREG( 58,232,16, 4, 4,0x03f2,0x0006, 1, 3,0x0100,ae_ts_fts_bu_bp,0,0,0,0,0,0)
|
||||
XTREG( 59,236,29, 4, 4,0x03f3,0x0006, 1, 3,0x0100,ae_cw_sd_no, 0,0,0,0,0,0)
|
||||
XTREG( 60,240,32, 4, 4,0x03f6,0x0006, 1, 3,0x0110,ae_cbegin0, 0,0,0,0,0,0)
|
||||
XTREG( 61,244,32, 4, 4,0x03f7,0x0006, 1, 3,0x0110,ae_cend0, 0,0,0,0,0,0)
|
||||
XTREG( 62,248,32, 4, 4,0x03f8,0x0006, 1, 3,0x0110,ae_cbegin1, 0,0,0,0,0,0)
|
||||
XTREG( 63,252,32, 4, 4,0x03f9,0x0006, 1, 3,0x0110,ae_cend1, 0,0,0,0,0,0)
|
||||
XTREG( 64,256,64, 8, 8,0x1010,0x0006, 1, 4,0x0101,aed0,
|
||||
"03:04:04:01","03:04:04:cf",0,0,0,0)
|
||||
XTREG( 65,264,64, 8, 8,0x1011,0x0006, 1, 4,0x0101,aed1,
|
||||
"03:04:14:01","03:04:14:cf",0,0,0,0)
|
||||
XTREG( 66,272,64, 8, 8,0x1012,0x0006, 1, 4,0x0101,aed2,
|
||||
"03:04:24:01","03:04:24:cf",0,0,0,0)
|
||||
XTREG( 67,280,64, 8, 8,0x1013,0x0006, 1, 4,0x0101,aed3,
|
||||
"03:04:34:01","03:04:34:cf",0,0,0,0)
|
||||
XTREG( 68,288,64, 8, 8,0x1014,0x0006, 1, 4,0x0101,aed4,
|
||||
"03:04:44:01","03:04:44:cf",0,0,0,0)
|
||||
XTREG( 69,296,64, 8, 8,0x1015,0x0006, 1, 4,0x0101,aed5,
|
||||
"03:04:54:01","03:04:54:cf",0,0,0,0)
|
||||
XTREG( 70,304,64, 8, 8,0x1016,0x0006, 1, 4,0x0101,aed6,
|
||||
"03:04:64:01","03:04:64:cf",0,0,0,0)
|
||||
XTREG( 71,312,64, 8, 8,0x1017,0x0006, 1, 4,0x0101,aed7,
|
||||
"03:04:74:01","03:04:74:cf",0,0,0,0)
|
||||
XTREG( 72,320,64, 8, 8,0x1018,0x0006, 1, 4,0x0101,aed8,
|
||||
"03:04:84:01","03:04:84:cf",0,0,0,0)
|
||||
XTREG( 73,328,64, 8, 8,0x1019,0x0006, 1, 4,0x0101,aed9,
|
||||
"03:04:94:01","03:04:94:cf",0,0,0,0)
|
||||
XTREG( 74,336,64, 8, 8,0x101a,0x0006, 1, 4,0x0101,aed10,
|
||||
"03:04:a4:01","03:04:a4:cf",0,0,0,0)
|
||||
XTREG( 75,344,64, 8, 8,0x101b,0x0006, 1, 4,0x0101,aed11,
|
||||
"03:04:b4:01","03:04:b4:cf",0,0,0,0)
|
||||
XTREG( 76,352,64, 8, 8,0x101c,0x0006, 1, 4,0x0101,aed12,
|
||||
"03:04:c4:01","03:04:c4:cf",0,0,0,0)
|
||||
XTREG( 77,360,64, 8, 8,0x101d,0x0006, 1, 4,0x0101,aed13,
|
||||
"03:04:d4:01","03:04:d4:cf",0,0,0,0)
|
||||
XTREG( 78,368,64, 8, 8,0x101e,0x0006, 1, 4,0x0101,aed14,
|
||||
"03:04:e4:01","03:04:e4:cf",0,0,0,0)
|
||||
XTREG( 79,376,64, 8, 8,0x101f,0x0006, 1, 4,0x0101,aed15,
|
||||
"03:04:f4:01","03:04:f4:cf",0,0,0,0)
|
||||
XTREG( 80,384,64, 8, 8,0x1020,0x0006, 1, 4,0x0101,u0,
|
||||
"0b:9f:24:70:16:3d:00:6c:a4:c5:77:39","0b:9f:24:70:16:2d:00:6c:a4:c5:77:39",0,0,0,0)
|
||||
XTREG( 81,392,64, 8, 8,0x1021,0x0006, 1, 4,0x0101,u1,
|
||||
"0b:9f:64:70:16:3d:00:6c:a4:c5:77:39","0b:9f:64:70:16:2d:00:6c:a4:c5:77:39",0,0,0,0)
|
||||
XTREG( 82,400,64, 8, 8,0x1022,0x0006, 1, 4,0x0101,u2,
|
||||
"0b:9f:a4:70:16:3d:00:6c:a4:c5:77:39","0b:9f:a4:70:16:2d:00:6c:a4:c5:77:39",0,0,0,0)
|
||||
XTREG( 83,408,64, 8, 8,0x1023,0x0006, 1, 4,0x0101,u3,
|
||||
"0b:9f:e4:70:16:3d:00:6c:a4:c5:77:39","0b:9f:e4:70:16:2d:00:6c:a4:c5:77:39",0,0,0,0)
|
||||
XTREG( 84,416, 8, 1, 1,0x1024,0x0006, 1, 4,0x0101,aep0,
|
||||
"03:52:64:01:06:5e:f0:06:01:e6:fc:03:52:44:00:03:52:24:01","03:52:64:01:03:52:04:00:06:5e:f4:06:01:e6:fc:03:52:24:01",0,0,0,0)
|
||||
XTREG( 85,417, 8, 1, 1,0x1025,0x0006, 1, 4,0x0101,aep1,
|
||||
"03:52:64:01:06:5e:f1:06:01:e6:fc:03:52:44:00:03:52:24:01","03:52:64:01:03:52:04:00:06:5e:f5:06:01:e6:fc:03:52:24:01",0,0,0,0)
|
||||
XTREG( 86,418, 8, 1, 1,0x1026,0x0006, 1, 4,0x0101,aep2,
|
||||
"03:52:64:01:06:5e:f2:06:01:e6:fc:03:52:44:00:03:52:24:01","03:52:64:01:03:52:04:00:06:5e:f6:06:01:e6:fc:03:52:24:01",0,0,0,0)
|
||||
XTREG( 87,419, 8, 1, 1,0x1027,0x0006, 1, 4,0x0101,aep3,
|
||||
"03:52:64:01:06:5e:f3:06:01:e6:fc:03:52:44:00:03:52:24:01","03:52:64:01:03:52:04:00:06:5e:f7:06:01:e6:fc:03:52:24:01",0,0,0,0)
|
||||
XTREG( 88,420, 7, 4, 4,0x1029,0x0006, 1, 3,0x0200,fcr_fsr,
|
||||
"03:14:04:01:0b:1f:15:70:06:3d:e3:6d:c4:c7:7f:39:03:04:04:01:03:14:04:cf","03:14:04:01:03:04:04:cf:0b:1f:15:70:06:1d:e3:6d:c4:c7:7f:39:03:14:04:cf",0,0,0,0)
|
||||
XTREG( 89,424,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0)
|
||||
XTREG( 90,428, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
|
||||
XTREG( 91,432, 1, 4, 4,0x0261,0x0007,-2, 2,0x1000,memctl, 0,0,0,0,0,0)
|
||||
XTREG( 92,436, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0)
|
||||
XTREG( 93,440,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
|
||||
XTREG( 94,444,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
|
||||
XTREG( 95,448,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0)
|
||||
XTREG( 96,452,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
|
||||
XTREG( 97,456,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0)
|
||||
XTREG( 98,460,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
|
||||
XTREG( 99,464,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0)
|
||||
XTREG(100,468,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
|
||||
XTREG(101,472,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
|
||||
XTREG(102,476,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
|
||||
XTREG(103,480,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0)
|
||||
XTREG(104,484,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
|
||||
XTREG(105,488,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
|
||||
XTREG(106,492,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
|
||||
XTREG(107,496,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0)
|
||||
XTREG(108,500,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0)
|
||||
XTREG(109,504,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0)
|
||||
XTREG(110,508,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
|
||||
XTREG(111,512,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
|
||||
XTREG(112,516,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0)
|
||||
XTREG(113,520,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0)
|
||||
XTREG(114,524,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0)
|
||||
XTREG(115,528, 2, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0)
|
||||
XTREG(116,532,32, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
|
||||
XTREG(117,536,32, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
|
||||
XTREG(118,540,32, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
|
||||
XTREG(119,544,32, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
|
||||
XTREG(120,548,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
|
||||
XTREG(121,552, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
|
||||
XTREG(122,556,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
|
||||
XTREG(123,560,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
|
||||
XTREG(124,564,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
|
||||
XTREG(125,568,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
|
||||
XTREG(126,572, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
|
||||
XTREG(127,576,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
|
||||
XTREG(128,580,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
|
||||
XTREG(129,584,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
|
||||
XTREG(130,588,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0)
|
||||
XTREG(131,592,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
|
||||
XTREG(132,596,32, 4, 4,0x2024,0x000f,-2, 4,0x0101,pwrctl,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(133,600,32, 4, 4,0x2025,0x000f,-2, 4,0x0101,pwrstat,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(134,604, 1, 4, 4,0x2026,0x000f,-2, 4,0x0101,eristat,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(135,608,32, 4, 4,0x2027,0x000f,-2, 4,0x0101,cs_itctrl,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(136,612,16, 4, 4,0x2028,0x000f,-2, 4,0x0101,cs_claimset,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(137,616,16, 4, 4,0x2029,0x000f,-2, 4,0x0101,cs_claimclr,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(138,620,32, 4, 4,0x202a,0x000d,-2, 4,0x0101,cs_lockaccess,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(139,624,32, 4, 4,0x202b,0x000b,-2, 4,0x0101,cs_lockstatus,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(140,628, 1, 4, 4,0x202c,0x000b,-2, 4,0x0101,cs_authstatus,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(141,632,32, 4, 4,0x203b,0x000f,-2, 4,0x0101,pmg,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(142,636,32, 4, 4,0x203c,0x000f,-2, 4,0x0101,pmpc,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(143,640,32, 4, 4,0x203d,0x000f,-2, 4,0x0101,pm0,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(144,644,32, 4, 4,0x203e,0x000f,-2, 4,0x0101,pm1,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(145,648,32, 4, 4,0x203f,0x000f,-2, 4,0x0101,pmctrl0,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(146,652,32, 4, 4,0x2040,0x000f,-2, 4,0x0101,pmctrl1,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(147,656,32, 4, 4,0x2041,0x000f,-2, 4,0x0101,pmstat0,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(148,660,32, 4, 4,0x2042,0x000f,-2, 4,0x0101,pmstat1,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(149,664,32, 4, 4,0x2043,0x0003,-2, 4,0x0101,ocdid,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(150,668,32, 4, 4,0x2044,0x000f,-2, 4,0x0101,ocd_dcrclr,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(151,672,32, 4, 4,0x2045,0x000f,-2, 4,0x0101,ocd_dcrset,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(152,676,32, 4, 4,0x2046,0x000f,-2, 4,0x0101,ocd_dsr,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(153,680,32, 4, 4,0x0000,0x0006,-2, 8,0x2100,a0, 0,0,0,0,0,0)
|
||||
XTREG(154,684,32, 4, 4,0x0001,0x0006,-2, 8,0x2100,a1, 0,0,0,0,0,0)
|
||||
XTREG(155,688,32, 4, 4,0x0002,0x0006,-2, 8,0x2100,a2, 0,0,0,0,0,0)
|
||||
XTREG(156,692,32, 4, 4,0x0003,0x0006,-2, 8,0x2100,a3, 0,0,0,0,0,0)
|
||||
XTREG(157,696,32, 4, 4,0x0004,0x0006,-2, 8,0x2100,a4, 0,0,0,0,0,0)
|
||||
XTREG(158,700,32, 4, 4,0x0005,0x0006,-2, 8,0x2100,a5, 0,0,0,0,0,0)
|
||||
XTREG(159,704,32, 4, 4,0x0006,0x0006,-2, 8,0x2100,a6, 0,0,0,0,0,0)
|
||||
XTREG(160,708,32, 4, 4,0x0007,0x0006,-2, 8,0x2100,a7, 0,0,0,0,0,0)
|
||||
XTREG(161,712,32, 4, 4,0x0008,0x0006,-2, 8,0x2100,a8, 0,0,0,0,0,0)
|
||||
XTREG(162,716,32, 4, 4,0x0009,0x0006,-2, 8,0x2100,a9, 0,0,0,0,0,0)
|
||||
XTREG(163,720,32, 4, 4,0x000a,0x0006,-2, 8,0x2100,a10, 0,0,0,0,0,0)
|
||||
XTREG(164,724,32, 4, 4,0x000b,0x0006,-2, 8,0x2100,a11, 0,0,0,0,0,0)
|
||||
XTREG(165,728,32, 4, 4,0x000c,0x0006,-2, 8,0x2100,a12, 0,0,0,0,0,0)
|
||||
XTREG(166,732,32, 4, 4,0x000d,0x0006,-2, 8,0x2100,a13, 0,0,0,0,0,0)
|
||||
XTREG(167,736,32, 4, 4,0x000e,0x0006,-2, 8,0x2100,a14, 0,0,0,0,0,0)
|
||||
XTREG(168,740,32, 4, 4,0x000f,0x0006,-2, 8,0x2100,a15, 0,0,0,0,0,0)
|
||||
XTREG(169,744, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,
|
||||
0,0,&xtensa_mask0,0,0,0)
|
||||
XTREG(170,745, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,
|
||||
0,0,&xtensa_mask1,0,0,0)
|
||||
XTREG(171,746, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,
|
||||
0,0,&xtensa_mask2,0,0,0)
|
||||
XTREG(172,747, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,
|
||||
0,0,&xtensa_mask3,0,0,0)
|
||||
XTREG(173,748, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,
|
||||
0,0,&xtensa_mask4,0,0,0)
|
||||
XTREG(174,749, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,
|
||||
0,0,&xtensa_mask5,0,0,0)
|
||||
XTREG(175,750, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,
|
||||
0,0,&xtensa_mask6,0,0,0)
|
||||
XTREG(176,751, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,
|
||||
0,0,&xtensa_mask7,0,0,0)
|
||||
XTREG(177,752, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,
|
||||
0,0,&xtensa_mask8,0,0,0)
|
||||
XTREG(178,753, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,
|
||||
0,0,&xtensa_mask9,0,0,0)
|
||||
XTREG(179,754, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
|
||||
0,0,&xtensa_mask10,0,0,0)
|
||||
XTREG(180,755, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,
|
||||
0,0,&xtensa_mask11,0,0,0)
|
||||
XTREG(181,756, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,
|
||||
0,0,&xtensa_mask12,0,0,0)
|
||||
XTREG(182,757, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,
|
||||
0,0,&xtensa_mask13,0,0,0)
|
||||
XTREG(183,758, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,
|
||||
0,0,&xtensa_mask14,0,0,0)
|
||||
XTREG(184,759, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,
|
||||
0,0,&xtensa_mask15,0,0,0)
|
||||
XTREG(185,760, 4, 4, 4,0x2006,0x0006,-2, 6,0x1010,psintlevel,
|
||||
0,0,&xtensa_mask16,0,0,0)
|
||||
XTREG(186,764, 1, 4, 4,0x2007,0x0006,-2, 6,0x1010,psum,
|
||||
0,0,&xtensa_mask17,0,0,0)
|
||||
XTREG(187,768, 1, 4, 4,0x2008,0x0006,-2, 6,0x1010,pswoe,
|
||||
0,0,&xtensa_mask18,0,0,0)
|
||||
XTREG(188,772, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psexcm,
|
||||
0,0,&xtensa_mask19,0,0,0)
|
||||
XTREG(189,776, 2, 4, 4,0x200a,0x0006,-2, 6,0x1010,pscallinc,
|
||||
0,0,&xtensa_mask20,0,0,0)
|
||||
XTREG(190,780, 4, 4, 4,0x200b,0x0006,-2, 6,0x1010,psowb,
|
||||
0,0,&xtensa_mask21,0,0,0)
|
||||
XTREG(191,784,40, 8, 4,0x200c,0x0006,-2, 6,0x1010,acc,
|
||||
0,0,&xtensa_mask22,0,0,0)
|
||||
XTREG(192,792, 4, 4, 4,0x2011,0x0006,-2, 6,0x1010,dbnum,
|
||||
0,0,&xtensa_mask23,0,0,0)
|
||||
XTREG(193,796, 1, 4, 4,0x2014,0x0006, 1, 6,0x1010,ae_overflow,
|
||||
0,0,&xtensa_mask24,0,0,0)
|
||||
XTREG(194,800,14, 4, 4,0x2015,0x0006, 1, 6,0x1010,ae_sar,
|
||||
0,0,&xtensa_mask25,0,0,0)
|
||||
XTREG(195,804, 1, 4, 4,0x2016,0x0006, 1, 6,0x1010,ae_cwrap,
|
||||
0,0,&xtensa_mask26,0,0,0)
|
||||
XTREG(196,808, 4, 4, 4,0x2017,0x0006, 1, 6,0x1010,ae_bitptr,
|
||||
0,0,&xtensa_mask27,0,0,0)
|
||||
XTREG(197,812, 4, 4, 4,0x2018,0x0006, 1, 6,0x1010,ae_bitsused,
|
||||
0,0,&xtensa_mask28,0,0,0)
|
||||
XTREG(198,816, 4, 4, 4,0x2019,0x0006, 1, 6,0x1010,ae_tablesize,
|
||||
0,0,&xtensa_mask29,0,0,0)
|
||||
XTREG(199,820, 4, 4, 4,0x201a,0x0006, 1, 6,0x1010,ae_first_ts,
|
||||
0,0,&xtensa_mask30,0,0,0)
|
||||
XTREG(200,824,27, 4, 4,0x201b,0x0006, 1, 6,0x1010,ae_nextoffset,
|
||||
0,0,&xtensa_mask31,0,0,0)
|
||||
XTREG(201,828, 1, 4, 4,0x201c,0x0006, 1, 6,0x1010,ae_searchdone,
|
||||
0,0,&xtensa_mask32,0,0,0)
|
||||
XTREG(202,832, 2, 4, 4,0x201d,0x0006, 1, 6,0x1010,roundmode,
|
||||
0,0,&xtensa_mask33,0,0,0)
|
||||
XTREG(203,836, 1, 4, 4,0x201e,0x0006, 1, 6,0x1010,invalidflag,
|
||||
0,0,&xtensa_mask34,0,0,0)
|
||||
XTREG(204,840, 1, 4, 4,0x201f,0x0006, 1, 6,0x1010,divzeroflag,
|
||||
0,0,&xtensa_mask35,0,0,0)
|
||||
XTREG(205,844, 1, 4, 4,0x2020,0x0006, 1, 6,0x1010,overflowflag,
|
||||
0,0,&xtensa_mask36,0,0,0)
|
||||
XTREG(206,848, 1, 4, 4,0x2021,0x0006, 1, 6,0x1010,underflowflag,
|
||||
0,0,&xtensa_mask37,0,0,0)
|
||||
XTREG(207,852, 1, 4, 4,0x2022,0x0006, 1, 6,0x1010,inexactflag,
|
||||
0,0,&xtensa_mask38,0,0,0)
|
||||
XTREG_END
|
||||
};
|
||||
|
||||
|
||||
|
||||
#ifdef XTENSA_CONFIG_INSTANTIATE
|
||||
XTENSA_CONFIG_INSTANTIATE(rmap,16)
|
||||
#endif
|
||||
|
||||
xtensa_gdbarch_tdep xtensa_tdep (rmap);
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
/* Customized table mapping between kernel xtregset and GDB register cache.
|
||||
|
||||
Copyright (c) 2007-2010 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
|
||||
typedef struct {
|
||||
int gdb_regnum;
|
||||
int gdb_offset;
|
||||
int ptrace_cp_offset;
|
||||
int ptrace_offset;
|
||||
int size;
|
||||
int coproc;
|
||||
int dbnum;
|
||||
char* name
|
||||
;} xtensa_regtable_t;
|
||||
|
||||
#define XTENSA_ELF_XTREG_SIZE 256
|
||||
|
||||
const xtensa_regtable_t xtensa_regmap_table[] = {
|
||||
/* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */
|
||||
{ 44, 176, 8, 8, 4, -1, 0x0204, "br" },
|
||||
{ 45, 180, 12, 12, 4, -1, 0x020c, "scompare1" },
|
||||
{ 46, 184, 0, 0, 4, -1, 0x0210, "acclo" },
|
||||
{ 47, 188, 4, 4, 4, -1, 0x0211, "acchi" },
|
||||
{ 48, 192, 16, 16, 4, -1, 0x0220, "m0" },
|
||||
{ 49, 196, 20, 20, 4, -1, 0x0221, "m1" },
|
||||
{ 50, 200, 24, 24, 4, -1, 0x0222, "m2" },
|
||||
{ 51, 204, 28, 28, 4, -1, 0x0223, "m3" },
|
||||
{ 53, 212, 32, 32, 4, -1, 0x03ea, "f64r_lo" },
|
||||
{ 54, 216, 36, 36, 4, -1, 0x03eb, "f64r_hi" },
|
||||
{ 55, 220, 40, 40, 4, -1, 0x03ec, "f64s" },
|
||||
{ 56, 224, 8, 56, 4, 1, 0x03f0, "ae_ovf_sar" },
|
||||
{ 57, 228, 12, 60, 4, 1, 0x03f1, "ae_bithead" },
|
||||
{ 58, 232, 16, 64, 4, 1, 0x03f2, "ae_ts_fts_bu_bp" },
|
||||
{ 59, 236, 20, 68, 4, 1, 0x03f3, "ae_cw_sd_no" },
|
||||
{ 60, 240, 24, 72, 4, 1, 0x03f6, "ae_cbegin0" },
|
||||
{ 61, 244, 28, 76, 4, 1, 0x03f7, "ae_cend0" },
|
||||
{ 62, 248, 32, 80, 4, 1, 0x03f8, "ae_cbegin1" },
|
||||
{ 63, 252, 36, 84, 4, 1, 0x03f9, "ae_cend1" },
|
||||
{ 64, 256, 40, 88, 8, 1, 0x1010, "aed0" },
|
||||
{ 65, 264, 48, 96, 8, 1, 0x1011, "aed1" },
|
||||
{ 66, 272, 56, 104, 8, 1, 0x1012, "aed2" },
|
||||
{ 67, 280, 64, 112, 8, 1, 0x1013, "aed3" },
|
||||
{ 68, 288, 72, 120, 8, 1, 0x1014, "aed4" },
|
||||
{ 69, 296, 80, 128, 8, 1, 0x1015, "aed5" },
|
||||
{ 70, 304, 88, 136, 8, 1, 0x1016, "aed6" },
|
||||
{ 71, 312, 96, 144, 8, 1, 0x1017, "aed7" },
|
||||
{ 72, 320, 104, 152, 8, 1, 0x1018, "aed8" },
|
||||
{ 73, 328, 112, 160, 8, 1, 0x1019, "aed9" },
|
||||
{ 74, 336, 120, 168, 8, 1, 0x101a, "aed10" },
|
||||
{ 75, 344, 128, 176, 8, 1, 0x101b, "aed11" },
|
||||
{ 76, 352, 136, 184, 8, 1, 0x101c, "aed12" },
|
||||
{ 77, 360, 144, 192, 8, 1, 0x101d, "aed13" },
|
||||
{ 78, 368, 152, 200, 8, 1, 0x101e, "aed14" },
|
||||
{ 79, 376, 160, 208, 8, 1, 0x101f, "aed15" },
|
||||
{ 80, 384, 176, 224, 8, 1, 0x1020, "u0" },
|
||||
{ 81, 392, 184, 232, 8, 1, 0x1021, "u1" },
|
||||
{ 82, 400, 192, 240, 8, 1, 0x1022, "u2" },
|
||||
{ 83, 408, 200, 248, 8, 1, 0x1023, "u3" },
|
||||
{ 84, 416, 168, 216, 1, 1, 0x1024, "aep0" },
|
||||
{ 85, 417, 169, 217, 1, 1, 0x1025, "aep1" },
|
||||
{ 86, 418, 170, 218, 1, 1, 0x1026, "aep2" },
|
||||
{ 87, 419, 171, 219, 1, 1, 0x1027, "aep3" },
|
||||
{ 88, 420, 0, 48, 4, 1, 0x1029, "fcr_fsr" },
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,189 @@
|
|||
/* Xtensa configuration settings.
|
||||
Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
|
||||
Free Software Foundation, Inc.
|
||||
Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful, but
|
||||
WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
|
||||
|
||||
#ifndef XTENSA_CONFIG_H
|
||||
#define XTENSA_CONFIG_H
|
||||
|
||||
/* The macros defined here match those with the same names in the Xtensa
|
||||
compile-time HAL (Hardware Abstraction Layer). Please refer to the
|
||||
Xtensa System Software Reference Manual for documentation of these
|
||||
macros. */
|
||||
|
||||
#undef XCHAL_HAVE_BE
|
||||
#define XCHAL_HAVE_BE 0
|
||||
|
||||
#undef XCHAL_HAVE_DENSITY
|
||||
#define XCHAL_HAVE_DENSITY 1
|
||||
|
||||
#undef XCHAL_HAVE_CONST16
|
||||
#define XCHAL_HAVE_CONST16 0
|
||||
|
||||
#undef XCHAL_HAVE_ABS
|
||||
#define XCHAL_HAVE_ABS 1
|
||||
|
||||
#undef XCHAL_HAVE_ADDX
|
||||
#define XCHAL_HAVE_ADDX 1
|
||||
|
||||
#undef XCHAL_HAVE_L32R
|
||||
#define XCHAL_HAVE_L32R 1
|
||||
|
||||
#undef XSHAL_USE_ABSOLUTE_LITERALS
|
||||
#define XSHAL_USE_ABSOLUTE_LITERALS 0
|
||||
|
||||
#undef XSHAL_HAVE_TEXT_SECTION_LITERALS
|
||||
#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
|
||||
|
||||
#undef XCHAL_HAVE_MAC16
|
||||
#define XCHAL_HAVE_MAC16 1
|
||||
|
||||
#undef XCHAL_HAVE_MUL16
|
||||
#define XCHAL_HAVE_MUL16 1
|
||||
|
||||
#undef XCHAL_HAVE_MUL32
|
||||
#define XCHAL_HAVE_MUL32 1
|
||||
|
||||
#undef XCHAL_HAVE_MUL32_HIGH
|
||||
#define XCHAL_HAVE_MUL32_HIGH 1
|
||||
|
||||
#undef XCHAL_HAVE_DIV32
|
||||
#define XCHAL_HAVE_DIV32 1
|
||||
|
||||
#undef XCHAL_HAVE_NSA
|
||||
#define XCHAL_HAVE_NSA 1
|
||||
|
||||
#undef XCHAL_HAVE_MINMAX
|
||||
#define XCHAL_HAVE_MINMAX 1
|
||||
|
||||
#undef XCHAL_HAVE_SEXT
|
||||
#define XCHAL_HAVE_SEXT 1
|
||||
|
||||
#undef XCHAL_HAVE_LOOPS
|
||||
#define XCHAL_HAVE_LOOPS 1
|
||||
|
||||
#undef XCHAL_HAVE_THREADPTR
|
||||
#define XCHAL_HAVE_THREADPTR 1
|
||||
|
||||
#undef XCHAL_HAVE_RELEASE_SYNC
|
||||
#define XCHAL_HAVE_RELEASE_SYNC 1
|
||||
|
||||
#undef XCHAL_HAVE_S32C1I
|
||||
#define XCHAL_HAVE_S32C1I 1
|
||||
|
||||
#undef XCHAL_HAVE_BOOLEANS
|
||||
#define XCHAL_HAVE_BOOLEANS 1
|
||||
|
||||
#undef XCHAL_HAVE_FP
|
||||
#define XCHAL_HAVE_FP 0
|
||||
|
||||
#undef XCHAL_HAVE_FP_DIV
|
||||
#define XCHAL_HAVE_FP_DIV 0
|
||||
|
||||
#undef XCHAL_HAVE_FP_RECIP
|
||||
#define XCHAL_HAVE_FP_RECIP 0
|
||||
|
||||
#undef XCHAL_HAVE_FP_SQRT
|
||||
#define XCHAL_HAVE_FP_SQRT 0
|
||||
|
||||
#undef XCHAL_HAVE_FP_RSQRT
|
||||
#define XCHAL_HAVE_FP_RSQRT 0
|
||||
|
||||
#undef XCHAL_HAVE_DFP_ACCEL
|
||||
#define XCHAL_HAVE_DFP_ACCEL 1
|
||||
/* For backward compatibility */
|
||||
#undef XCHAL_HAVE_DFP_accel
|
||||
#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL
|
||||
|
||||
#undef XCHAL_HAVE_WINDOWED
|
||||
#define XCHAL_HAVE_WINDOWED 1
|
||||
|
||||
#undef XCHAL_NUM_AREGS
|
||||
#define XCHAL_NUM_AREGS 32
|
||||
|
||||
#undef XCHAL_HAVE_WIDE_BRANCHES
|
||||
#define XCHAL_HAVE_WIDE_BRANCHES 0
|
||||
|
||||
#undef XCHAL_HAVE_PREDICTED_BRANCHES
|
||||
#define XCHAL_HAVE_PREDICTED_BRANCHES 0
|
||||
|
||||
|
||||
#undef XCHAL_ICACHE_SIZE
|
||||
#define XCHAL_ICACHE_SIZE 32768
|
||||
|
||||
#undef XCHAL_DCACHE_SIZE
|
||||
#define XCHAL_DCACHE_SIZE 65536
|
||||
|
||||
#undef XCHAL_ICACHE_LINESIZE
|
||||
#define XCHAL_ICACHE_LINESIZE 256
|
||||
|
||||
#undef XCHAL_DCACHE_LINESIZE
|
||||
#define XCHAL_DCACHE_LINESIZE 256
|
||||
|
||||
#undef XCHAL_ICACHE_LINEWIDTH
|
||||
#define XCHAL_ICACHE_LINEWIDTH 8
|
||||
|
||||
#undef XCHAL_DCACHE_LINEWIDTH
|
||||
#define XCHAL_DCACHE_LINEWIDTH 8
|
||||
|
||||
#undef XCHAL_DCACHE_IS_WRITEBACK
|
||||
#define XCHAL_DCACHE_IS_WRITEBACK 1
|
||||
|
||||
|
||||
#undef XCHAL_HAVE_MMU
|
||||
#define XCHAL_HAVE_MMU 0
|
||||
|
||||
|
||||
#undef XCHAL_HAVE_DEBUG
|
||||
#define XCHAL_HAVE_DEBUG 1
|
||||
|
||||
#undef XCHAL_NUM_IBREAK
|
||||
#define XCHAL_NUM_IBREAK 2
|
||||
|
||||
#undef XCHAL_NUM_DBREAK
|
||||
#define XCHAL_NUM_DBREAK 2
|
||||
|
||||
#undef XCHAL_DEBUGLEVEL
|
||||
#define XCHAL_DEBUGLEVEL 4
|
||||
|
||||
|
||||
#undef XCHAL_MAX_INSTRUCTION_SIZE
|
||||
#define XCHAL_MAX_INSTRUCTION_SIZE 11
|
||||
|
||||
#undef XCHAL_INST_FETCH_WIDTH
|
||||
#define XCHAL_INST_FETCH_WIDTH 16
|
||||
|
||||
|
||||
#undef XSHAL_ABI
|
||||
#undef XTHAL_ABI_WINDOWED
|
||||
#undef XTHAL_ABI_CALL0
|
||||
#define XSHAL_ABI XTHAL_ABI_WINDOWED
|
||||
#define XTHAL_ABI_WINDOWED 0
|
||||
#define XTHAL_ABI_CALL0 1
|
||||
|
||||
|
||||
#undef XCHAL_M_STAGE
|
||||
#define XCHAL_M_STAGE 3
|
||||
|
||||
#undef XTENSA_MARCH_LATEST
|
||||
#define XTENSA_MARCH_LATEST 260004
|
||||
|
||||
#undef XTENSA_MARCH_EARLIEST
|
||||
#define XTENSA_MARCH_EARLIEST 260004
|
||||
|
||||
|
||||
#endif /* !XTENSA_CONFIG_H */
|
||||
|
|
@ -0,0 +1,813 @@
|
|||
/*
|
||||
* xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
|
||||
* processor CORE configuration
|
||||
*
|
||||
* See <xtensa/config/core.h>, which includes this file, for more details.
|
||||
*/
|
||||
|
||||
/* Xtensa processor core configuration information.
|
||||
|
||||
Copyright (c) 1999-2023 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#ifndef XTENSA_CORE_CONFIGURATION_H_
|
||||
#define XTENSA_CORE_CONFIGURATION_H_
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
Parameters Useful for Any Code, USER or PRIVILEGED
|
||||
****************************************************************************/
|
||||
|
||||
/*
|
||||
* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
|
||||
* configured, and a value of 0 otherwise. These macros are always defined.
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
ISA
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
|
||||
#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
|
||||
#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
|
||||
#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
|
||||
#define XCHAL_MAX_INSTRUCTION_SIZE 11 /* max instr bytes (3..8) */
|
||||
#define XCHAL_HAVE_DEBUG 1 /* debug option */
|
||||
#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
|
||||
#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
|
||||
#define XCHAL_LOOP_BUFFER_SIZE 256 /* zero-ov. loop instr buffer size */
|
||||
#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
|
||||
#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
|
||||
#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
|
||||
#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
|
||||
#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
|
||||
#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
|
||||
#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
|
||||
#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */
|
||||
#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
|
||||
#define XCHAL_HAVE_L32R 1 /* L32R instruction */
|
||||
#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
|
||||
#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
|
||||
#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
|
||||
#define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */
|
||||
#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
|
||||
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
|
||||
#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
|
||||
#define XCHAL_HAVE_ABS 1 /* ABS instruction */
|
||||
#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
|
||||
#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
|
||||
#define XCHAL_HAVE_SPECULATION 0 /* speculation */
|
||||
#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
|
||||
#define XCHAL_NUM_CONTEXTS 1 /* */
|
||||
#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
|
||||
#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
|
||||
#define XCHAL_HAVE_PRID 1 /* processor ID register */
|
||||
#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
|
||||
#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
|
||||
#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
|
||||
#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
|
||||
#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
|
||||
#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
|
||||
#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
|
||||
#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
|
||||
#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
|
||||
#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
|
||||
#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */
|
||||
#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
|
||||
#define XCHAL_HAVE_LX 1 /* LX core */
|
||||
#define XCHAL_HAVE_NX 0 /* NX core (starting RH) */
|
||||
#define XCHAL_HAVE_RNX 0 /* RNX core (starting RJ) */
|
||||
|
||||
#define XCHAL_HAVE_SUPERGATHER 0 /* SuperGather */
|
||||
|
||||
#define XCHAL_HAVE_FUSION 0 /* Fusion */
|
||||
#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
|
||||
#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
|
||||
#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
|
||||
#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
|
||||
#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
|
||||
#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
|
||||
#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
|
||||
#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
|
||||
#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */
|
||||
#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */
|
||||
#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI5 0 /* HiFi5 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI5_NN_MAC 0 /* HiFi5 Audio Engine NN-MAC option */
|
||||
#define XCHAL_HAVE_HIFI5_VFPU 0 /* HiFi5 Audio Engine Single-Precision VFPU option */
|
||||
#define XCHAL_HAVE_HIFI5_HP_VFPU 0 /* HiFi5 Audio Engine Half-Precision VFPU option */
|
||||
#define XCHAL_HAVE_HIFI4 1 /* HiFi4 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI4_VFPU 1 /* HiFi4 Audio Engine VFPU option */
|
||||
#define XCHAL_HAVE_HIFI3 1 /* HiFi3 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
|
||||
#define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */
|
||||
#define XCHAL_HAVE_HIFI1 0 /* HiFi1 */
|
||||
#define XCHAL_HAVE_HIFI1_VFPU 0 /* HiFi1 VFPU option */
|
||||
#define XCHAL_HAVE_HIFI1_LOW_LATENCY_MAC_FMA 0 /* HiFi1 Low-latency MAC/FMA option */
|
||||
#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
|
||||
#define XCHAL_HAVE_HIFI_MINI 0
|
||||
|
||||
|
||||
|
||||
#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
|
||||
#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
|
||||
#define XCHAL_HAVE_USER_SPFPU 1 /* user SP floating-point pkg */
|
||||
#define XCHAL_HAVE_FP 1 /* single prec floating point */
|
||||
#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */
|
||||
#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */
|
||||
#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */
|
||||
#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */
|
||||
#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
|
||||
#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
|
||||
#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
|
||||
#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
|
||||
#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
|
||||
#define XCHAL_HAVE_DFP_ACCEL 1 /* double precision FP acceleration pkg */
|
||||
#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
|
||||
|
||||
#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */
|
||||
#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
|
||||
#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
|
||||
#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
|
||||
|
||||
#define XCHAL_HAVE_FUSIONG 0 /* FusionG */
|
||||
#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */
|
||||
#define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */
|
||||
#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */
|
||||
#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */
|
||||
#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */
|
||||
|
||||
#define XCHAL_HAVE_FUSIONJ 0 /* FusionJ */
|
||||
#define XCHAL_HAVE_FUSIONJ6 0 /* FusionJ6 */
|
||||
#define XCHAL_HAVE_FUSIONJ_SP_VFPU 0 /* sp_vfpu option on FusionJ */
|
||||
#define XCHAL_HAVE_FUSIONJ_DP_VFPU 0 /* dp_vfpu option on FusionJ */
|
||||
#define XCHAL_FUSIONJ_SIMD32 0 /* simd32 for FusionJ */
|
||||
|
||||
#define XCHAL_HAVE_PDX 0 /* PDX-LX */
|
||||
#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */
|
||||
#define XCHAL_HAVE_PDX4 0 /* PDX4-LX */
|
||||
#define XCHAL_HAVE_PDX8 0 /* PDX8-LX */
|
||||
#define XCHAL_HAVE_PDX16 0 /* PDX16-LX */
|
||||
#define XCHAL_HAVE_PDXNX 0 /* PDX-NX */
|
||||
|
||||
#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
|
||||
#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */
|
||||
#define XCHAL_HAVE_BALL 0
|
||||
#define XCHAL_HAVE_BALLAP 0
|
||||
#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
|
||||
#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
|
||||
#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
|
||||
#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
|
||||
#define XCHAL_HAVE_CONNX_B10 0 /* ConnX B10 pkg*/
|
||||
#define XCHAL_HAVE_CONNX_B20 0 /* ConnX B20 pkg*/
|
||||
#define XCHAL_HAVE_CONNX_B_DP_VFPU 0 /* Double-precision Vector Floating-point option on ConnX B10 & B20 */
|
||||
#define XCHAL_HAVE_CONNX_B_DPX_VFPU 0 /* Double-precision Vector Floating-point option on FP Machine*/
|
||||
#define XCHAL_HAVE_CONNX_B_SP_VFPU 0 /* Single-precision Vector Floating-point option on ConnX B10 & B20 */
|
||||
#define XCHAL_HAVE_CONNX_B_SPX_VFPU 0 /* Single-precision Extended Vector Floating-point option on ConnX B10 & B20 */
|
||||
#define XCHAL_HAVE_CONNX_B_HP_VFPU 0 /* Half-precision Vector Floating-point option on ConnX B10 & B20 */
|
||||
#define XCHAL_HAVE_CONNX_B_HPX_VFPU 0 /* Half-precision Extended Vector Floating-point option on ConnX B10 & B20 */
|
||||
#define XCHAL_HAVE_CONNX_B_32B_MAC 0 /* 32-bit vector MAC (real and complex), FIR & FFT option on ConnX B10 & B20 */
|
||||
#define XCHAL_HAVE_CONNX_B_VITERBI 0 /* Viterbi option on ConnX B10 & B20 */
|
||||
#define XCHAL_HAVE_CONNX_B_TURBO 0 /* Turbo option on ConnX B10 & B20 */
|
||||
#define XCHAL_HAVE_CONNX_B_LDPC 0 /* LDPC option on ConnX B10 & B20 */
|
||||
#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
|
||||
#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */
|
||||
#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
|
||||
#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
|
||||
#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
|
||||
#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
|
||||
#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
|
||||
#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
|
||||
#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
|
||||
#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */
|
||||
#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
|
||||
|
||||
#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */
|
||||
#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */
|
||||
#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, Q6, Q7 or Q8 */
|
||||
#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */
|
||||
#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */
|
||||
#define XCHAL_HAVE_VISION_DP_VFPU 0 /* dp_vfpu option on Vision Q7/Q8 */
|
||||
#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6/Q6/Q7 */
|
||||
#define XCHAL_HAVE_VISION_SP_VFPU_2XFMAC 0 /* sp_vfpu_2xfma option on Vision Q7 */
|
||||
#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6/Q6 */
|
||||
#define XCHAL_HAVE_VISION_HP_VFPU_2XFMAC 0 /* hp_vfpu_2xfma option on Vision Q7 */
|
||||
|
||||
#define XCHAL_HAVE_VISIONC 0 /* Vision C */
|
||||
|
||||
#define XCHAL_HAVE_XNNE 0 /* XNNE */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MISC
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_NUM_LOADSTORE_UNITS 2 /* load/store units */
|
||||
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 32 /* size of write buffer */
|
||||
#define XCHAL_INST_FETCH_WIDTH 16 /* instr-fetch width in bytes */
|
||||
#define XCHAL_DATA_WIDTH 16 /* data width in bytes */
|
||||
#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay
|
||||
(1 = 5-stage, 2 = 7-stage) */
|
||||
#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */
|
||||
#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */
|
||||
/* In T1050, applies to selected core load and store instructions (see ISA): */
|
||||
#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
|
||||
#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
|
||||
#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */
|
||||
#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/
|
||||
|
||||
#define XCHAL_UNIFIED_LOADSTORE 0
|
||||
|
||||
#define XCHAL_SW_VERSION 1411000 /* sw version of this header */
|
||||
#define XCHAL_SW_VERSION_MAJOR 14000 /* major ver# of sw */
|
||||
#define XCHAL_SW_VERSION_MINOR 11 /* minor ver# of sw */
|
||||
#define XCHAL_SW_VERSION_MICRO 0 /* micro ver# of sw */
|
||||
#define XCHAL_SW_MINOR_VERSION 1411000 /* with zeroed micro */
|
||||
#define XCHAL_SW_MICRO_VERSION 1411000
|
||||
|
||||
#define XCHAL_CORE_ID "nxp_rt600_RI23_11_newlib" /* alphanum core name
|
||||
(CoreID) set in the Xtensa
|
||||
Processor Generator */
|
||||
|
||||
#define XCHAL_BUILD_UNIQUE_ID 0x000A98E8 /* 22-bit sw build ID */
|
||||
|
||||
/*
|
||||
* These definitions describe the hardware targeted by this software.
|
||||
*/
|
||||
#define XCHAL_HW_CONFIGID0 0xC2F3FFFE /* ConfigID hi 32 bits*/
|
||||
#define XCHAL_HW_CONFIGID1 0x1D06FB2F /* ConfigID lo 32 bits*/
|
||||
#define XCHAL_HW_VERSION_NAME "LX6.0.4" /* full version name */
|
||||
#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */
|
||||
#define XCHAL_HW_VERSION_MINOR 4 /* minor ver# of targeted hw */
|
||||
#define XCHAL_HW_VERSION_MICRO 0 /* subdot ver# of targeted hw */
|
||||
#define XCHAL_HW_VERSION 260004 /* major*100+(major<2810 ? minor : minor*10+micro) */
|
||||
#define XCHAL_HW_REL_LX6 1
|
||||
#define XCHAL_HW_REL_LX6_0 1
|
||||
#define XCHAL_HW_REL_LX6_0_4 1
|
||||
#define XCHAL_HW_CONFIGID_RELIABLE 1
|
||||
/* If software targets a *range* of hardware versions, these are the bounds: */
|
||||
#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION_MINOR 4 /* minor v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION_MICRO 0 /* micro v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION 260004 /* earliest targeted hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MINOR 4 /* minor v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MICRO 0 /* micro v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION 260004 /* latest targeted hw */
|
||||
|
||||
/* Config is enabled for functional safety: */
|
||||
#define XCHAL_HAVE_FUNC_SAFETY 0
|
||||
|
||||
/* Config is enabled for secure operation: */
|
||||
#define XCHAL_HAVE_SECURE 0
|
||||
|
||||
#define XCHAL_HAVE_APB 0
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CACHE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_ICACHE_LINESIZE 256 /* I-cache line size in bytes */
|
||||
#define XCHAL_DCACHE_LINESIZE 256 /* D-cache line size in bytes */
|
||||
#define XCHAL_ICACHE_LINEWIDTH 8 /* log2(I line size in bytes) */
|
||||
#define XCHAL_DCACHE_LINEWIDTH 8 /* log2(D line size in bytes) */
|
||||
|
||||
#define XCHAL_ICACHE_SIZE 32768 /* I-cache size in bytes or 0 */
|
||||
#define XCHAL_ICACHE_SIZE_LOG2 15
|
||||
#define XCHAL_DCACHE_SIZE 65536 /* D-cache size in bytes or 0 */
|
||||
#define XCHAL_DCACHE_SIZE_LOG2 16
|
||||
|
||||
#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
|
||||
#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
|
||||
|
||||
#define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */
|
||||
#define XCHAL_HAVE_PREFETCH_L1 1 /* prefetch to L1 cache */
|
||||
#define XCHAL_PREFETCH_CASTOUT_LINES 1 /* dcache pref. castout bufsz */
|
||||
#define XCHAL_PREFETCH_ENTRIES 16 /* cache prefetch entries */
|
||||
#define XCHAL_PREFETCH_BLOCK_ENTRIES 8 /* prefetch block streams */
|
||||
#define XCHAL_HAVE_CACHE_BLOCKOPS 1 /* block prefetch for caches */
|
||||
#define XCHAL_HAVE_CME_DOWNGRADES 0
|
||||
#define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */
|
||||
#define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */
|
||||
#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
|
||||
#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
|
||||
#define XCHAL_HAVE_ICACHE_DYN_ENABLE 0 /* Icache enabled via MEMCTL */
|
||||
#define XCHAL_HAVE_DCACHE_DYN_ENABLE 0 /* Dcache enabled via MEMCTL */
|
||||
|
||||
#define XCHAL_L1SCACHE_SIZE 0
|
||||
#define XCHAL_L1SCACHE_SIZE_LOG2 0
|
||||
#define XCHAL_L1SCACHE_WAYS 1
|
||||
#define XCHAL_L1SCACHE_WAYS_LOG2 0
|
||||
#define XCHAL_L1SCACHE_ACCESS_SIZE 0
|
||||
#define XCHAL_L1SCACHE_BANKS 1
|
||||
|
||||
#define XCHAL_L1VCACHE_SIZE 0
|
||||
|
||||
#define XCHAL_HAVE_L2 0 /* NX L2 cache controller */
|
||||
#define XCHAL_HAVE_L2_CACHE 0
|
||||
#define XCHAL_NUM_CORES_IN_CLUSTER 0
|
||||
|
||||
/* PRID_ID macros are for internal use only ... subject to removal */
|
||||
#define PRID_ID_SHIFT 0
|
||||
#define PRID_ID_BITS 4
|
||||
#define PRID_ID_MASK 0x0000000F
|
||||
|
||||
/* This one is a form of caching, though not architecturally visible: */
|
||||
#define XCHAL_HAVE_BRANCH_PREDICTION 0 /* branch [target] prediction */
|
||||
|
||||
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CACHE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_PIF 1 /* any outbound bus present */
|
||||
|
||||
#define XCHAL_HAVE_AXI 0 /* AXI bus */
|
||||
#define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */
|
||||
#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */
|
||||
|
||||
#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */
|
||||
#define XCHAL_HAVE_PIF_REQ_ATTR 0 /* pif attribute */
|
||||
|
||||
/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
|
||||
|
||||
/* Number of cache sets in log2(lines per way): */
|
||||
#define XCHAL_ICACHE_SETWIDTH 5
|
||||
#define XCHAL_DCACHE_SETWIDTH 6
|
||||
|
||||
/* Cache set associativity (number of ways): */
|
||||
#define XCHAL_ICACHE_WAYS 4
|
||||
#define XCHAL_ICACHE_WAYS_LOG2 2
|
||||
#define XCHAL_DCACHE_WAYS 4
|
||||
#define XCHAL_DCACHE_WAYS_LOG2 2
|
||||
|
||||
/* Cache features: */
|
||||
#define XCHAL_ICACHE_LINE_LOCKABLE 1
|
||||
#define XCHAL_DCACHE_LINE_LOCKABLE 1
|
||||
#define XCHAL_ICACHE_ECC_PARITY 0
|
||||
#define XCHAL_DCACHE_ECC_PARITY 0
|
||||
#define XCHAL_ICACHE_ECC_WIDTH 4
|
||||
#define XCHAL_DCACHE_ECC_WIDTH 1
|
||||
|
||||
/* Cache access size in bytes (affects operation of SICW instruction): */
|
||||
#define XCHAL_ICACHE_ACCESS_SIZE 16
|
||||
#define XCHAL_DCACHE_ACCESS_SIZE 16
|
||||
|
||||
#define XCHAL_DCACHE_BANKS 4 /* number of banks */
|
||||
|
||||
/* The number of Cache lines associated with a single cache tag */
|
||||
#define XCHAL_DCACHE_LINES_PER_TAG_LOG2 0
|
||||
|
||||
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
|
||||
#define XCHAL_CA_BITS 4
|
||||
|
||||
/* Extended memory attributes supported. */
|
||||
#define XCHAL_HAVE_EXT_CA 0
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
INTERNAL I/D RAM/ROMs and XLMI
|
||||
----------------------------------------------------------------------*/
|
||||
#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
|
||||
#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */
|
||||
#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
|
||||
#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */
|
||||
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
|
||||
#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
|
||||
#define XCHAL_HAVE_IRAMCFG 0 /* IRAMxCFG register present */
|
||||
#define XCHAL_HAVE_DRAMCFG 0 /* DRAMxCFG register present */
|
||||
|
||||
/* Instruction RAM 0: */
|
||||
#define XCHAL_INSTRAM0_VADDR 0x24020000 /* virtual address */
|
||||
#define XCHAL_INSTRAM0_PADDR 0x24020000 /* physical address */
|
||||
#define XCHAL_INSTRAM0_SIZE 65536 /* size in bytes */
|
||||
#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
|
||||
#define XCHAL_HAVE_INSTRAM0 1
|
||||
#define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */
|
||||
|
||||
/* Data RAM 0: */
|
||||
#define XCHAL_DATARAM0_VADDR 0x24000000 /* virtual address */
|
||||
#define XCHAL_DATARAM0_PADDR 0x24000000 /* physical address */
|
||||
#define XCHAL_DATARAM0_SIZE 65536 /* size in bytes */
|
||||
#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
|
||||
#define XCHAL_DATARAM0_BANKS 4 /* number of banks */
|
||||
#define XCHAL_HAVE_DATARAM0 1
|
||||
#define XCHAL_DATARAM0_HAVE_IDMA 0 /* idma supported by this local memory */
|
||||
|
||||
#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
IDMA
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_IDMA 0
|
||||
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
INTERRUPTS and TIMERS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
|
||||
#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
|
||||
#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
|
||||
#define XCHAL_NUM_TIMERS 2 /* number of CCOMPAREn regs */
|
||||
#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */
|
||||
#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
|
||||
#define XCHAL_NUM_EXTINTERRUPTS 28 /* num of external interrupts */
|
||||
#define XCHAL_NUM_INTLEVELS 4 /* number of interrupt levels
|
||||
(not including level zero) */
|
||||
#define XCHAL_INTERRUPT_RANGE 32 /* range of interrupt numbers */
|
||||
|
||||
|
||||
#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
|
||||
#define XCHAL_EXCM_LEVEL 2 /* level masked by PS.EXCM */
|
||||
/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
|
||||
|
||||
/* Masks of interrupts at each interrupt level: */
|
||||
#define XCHAL_INTLEVEL1_MASK 0x0000FFE0
|
||||
#define XCHAL_INTLEVEL2_MASK 0x00FF0006
|
||||
#define XCHAL_INTLEVEL3_MASK 0xFF000018
|
||||
#define XCHAL_INTLEVEL4_MASK 0x00000000
|
||||
#define XCHAL_INTLEVEL5_MASK 0x00000001
|
||||
#define XCHAL_INTLEVEL6_MASK 0x00000000
|
||||
#define XCHAL_INTLEVEL7_MASK 0x00000000
|
||||
|
||||
/* Masks of interrupts at each range 1..n of interrupt levels: */
|
||||
#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x0000FFE0
|
||||
#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x00FFFFE6
|
||||
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0xFFFFFFFE
|
||||
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0xFFFFFFFE
|
||||
#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFFFFFFFF
|
||||
#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFFFFF
|
||||
#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF
|
||||
|
||||
/* Level of each interrupt: */
|
||||
#define XCHAL_INT0_LEVEL 5
|
||||
#define XCHAL_INT1_LEVEL 2
|
||||
#define XCHAL_INT2_LEVEL 2
|
||||
#define XCHAL_INT3_LEVEL 3
|
||||
#define XCHAL_INT4_LEVEL 3
|
||||
#define XCHAL_INT5_LEVEL 1
|
||||
#define XCHAL_INT6_LEVEL 1
|
||||
#define XCHAL_INT7_LEVEL 1
|
||||
#define XCHAL_INT8_LEVEL 1
|
||||
#define XCHAL_INT9_LEVEL 1
|
||||
#define XCHAL_INT10_LEVEL 1
|
||||
#define XCHAL_INT11_LEVEL 1
|
||||
#define XCHAL_INT12_LEVEL 1
|
||||
#define XCHAL_INT13_LEVEL 1
|
||||
#define XCHAL_INT14_LEVEL 1
|
||||
#define XCHAL_INT15_LEVEL 1
|
||||
#define XCHAL_INT16_LEVEL 2
|
||||
#define XCHAL_INT17_LEVEL 2
|
||||
#define XCHAL_INT18_LEVEL 2
|
||||
#define XCHAL_INT19_LEVEL 2
|
||||
#define XCHAL_INT20_LEVEL 2
|
||||
#define XCHAL_INT21_LEVEL 2
|
||||
#define XCHAL_INT22_LEVEL 2
|
||||
#define XCHAL_INT23_LEVEL 2
|
||||
#define XCHAL_INT24_LEVEL 3
|
||||
#define XCHAL_INT25_LEVEL 3
|
||||
#define XCHAL_INT26_LEVEL 3
|
||||
#define XCHAL_INT27_LEVEL 3
|
||||
#define XCHAL_INT28_LEVEL 3
|
||||
#define XCHAL_INT29_LEVEL 3
|
||||
#define XCHAL_INT30_LEVEL 3
|
||||
#define XCHAL_INT31_LEVEL 3
|
||||
#define XCHAL_DEBUGLEVEL 4 /* debug interrupt level */
|
||||
#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
|
||||
#define XCHAL_NMILEVEL 5 /* NMI "level" (for use with
|
||||
EXCSAVE/EPS/EPC_n, RFI n) */
|
||||
|
||||
/* Type of each interrupt: */
|
||||
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_NMI
|
||||
#define XCHAL_INT1_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT2_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT3_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT4_TYPE XTHAL_INTTYPE_PROFILING
|
||||
#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT14_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT25_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT26_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT27_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT28_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT29_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT30_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT31_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
|
||||
/* Masks of interrupts for each type of interrupt: */
|
||||
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0xFFFFFFE0
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_NMI 0x00000001
|
||||
#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000002
|
||||
#define XCHAL_INTTYPE_MASK_TIMER 0x0000000C
|
||||
#define XCHAL_INTTYPE_MASK_ETIE 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_DBG_REQUEST 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_BREAKIN 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_TRAX 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_PROFILING 0x00000010
|
||||
#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_L2_ERR 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_L2_STATUS 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_COR_ECC_ERR 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_WWDT 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_FXLK 0x00000000
|
||||
|
||||
/* Interrupt numbers assigned to specific interrupt sources: */
|
||||
#define XCHAL_TIMER0_INTERRUPT 2 /* CCOMPARE0 */
|
||||
#define XCHAL_TIMER1_INTERRUPT 3 /* CCOMPARE1 */
|
||||
#define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED
|
||||
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
|
||||
#define XCHAL_NMI_INTERRUPT 0 /* non-maskable interrupt */
|
||||
#define XCHAL_PROFILING_INTERRUPT 4
|
||||
|
||||
/* Interrupt numbers for levels at which only one interrupt is configured: */
|
||||
#define XCHAL_INTLEVEL5_NUM 0
|
||||
/* (There are many interrupts each at level(s) 1, 2, 3.) */
|
||||
|
||||
|
||||
/*
|
||||
* External interrupt mapping.
|
||||
* These macros describe how Xtensa processor interrupt numbers
|
||||
* (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
|
||||
* map to external BInterrupt<n> pins, for those interrupts
|
||||
* configured as external (level-triggered, edge-triggered, or NMI).
|
||||
* See the Xtensa processor databook for more details.
|
||||
*/
|
||||
|
||||
/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
|
||||
#define XCHAL_EXTINT0_NUM 0 /* (intlevel 5) */
|
||||
#define XCHAL_EXTINT1_NUM 5 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT2_NUM 6 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT3_NUM 7 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT4_NUM 8 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT5_NUM 9 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT6_NUM 10 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT7_NUM 11 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT8_NUM 12 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT9_NUM 13 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT10_NUM 14 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT11_NUM 15 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT12_NUM 16 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT13_NUM 17 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT14_NUM 18 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT15_NUM 19 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT16_NUM 20 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT17_NUM 21 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT18_NUM 22 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT19_NUM 23 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT20_NUM 24 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT21_NUM 25 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT22_NUM 26 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT23_NUM 27 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT24_NUM 28 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT25_NUM 29 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT26_NUM 30 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT27_NUM 31 /* (intlevel 3) */
|
||||
/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
|
||||
#define XCHAL_INT0_EXTNUM 0 /* (intlevel 5) */
|
||||
#define XCHAL_INT5_EXTNUM 1 /* (intlevel 1) */
|
||||
#define XCHAL_INT6_EXTNUM 2 /* (intlevel 1) */
|
||||
#define XCHAL_INT7_EXTNUM 3 /* (intlevel 1) */
|
||||
#define XCHAL_INT8_EXTNUM 4 /* (intlevel 1) */
|
||||
#define XCHAL_INT9_EXTNUM 5 /* (intlevel 1) */
|
||||
#define XCHAL_INT10_EXTNUM 6 /* (intlevel 1) */
|
||||
#define XCHAL_INT11_EXTNUM 7 /* (intlevel 1) */
|
||||
#define XCHAL_INT12_EXTNUM 8 /* (intlevel 1) */
|
||||
#define XCHAL_INT13_EXTNUM 9 /* (intlevel 1) */
|
||||
#define XCHAL_INT14_EXTNUM 10 /* (intlevel 1) */
|
||||
#define XCHAL_INT15_EXTNUM 11 /* (intlevel 1) */
|
||||
#define XCHAL_INT16_EXTNUM 12 /* (intlevel 2) */
|
||||
#define XCHAL_INT17_EXTNUM 13 /* (intlevel 2) */
|
||||
#define XCHAL_INT18_EXTNUM 14 /* (intlevel 2) */
|
||||
#define XCHAL_INT19_EXTNUM 15 /* (intlevel 2) */
|
||||
#define XCHAL_INT20_EXTNUM 16 /* (intlevel 2) */
|
||||
#define XCHAL_INT21_EXTNUM 17 /* (intlevel 2) */
|
||||
#define XCHAL_INT22_EXTNUM 18 /* (intlevel 2) */
|
||||
#define XCHAL_INT23_EXTNUM 19 /* (intlevel 2) */
|
||||
#define XCHAL_INT24_EXTNUM 20 /* (intlevel 3) */
|
||||
#define XCHAL_INT25_EXTNUM 21 /* (intlevel 3) */
|
||||
#define XCHAL_INT26_EXTNUM 22 /* (intlevel 3) */
|
||||
#define XCHAL_INT27_EXTNUM 23 /* (intlevel 3) */
|
||||
#define XCHAL_INT28_EXTNUM 24 /* (intlevel 3) */
|
||||
#define XCHAL_INT29_EXTNUM 25 /* (intlevel 3) */
|
||||
#define XCHAL_INT30_EXTNUM 26 /* (intlevel 3) */
|
||||
#define XCHAL_INT31_EXTNUM 27 /* (intlevel 3) */
|
||||
|
||||
#define XCHAL_HAVE_ISB 0 /* No ISB */
|
||||
#define XCHAL_ISB_VADDR 0 /* N/A */
|
||||
#define XCHAL_HAVE_ITB 0 /* No ITB */
|
||||
#define XCHAL_ITB_VADDR 0 /* N/A */
|
||||
|
||||
#define XCHAL_HAVE_KSL 0 /* Kernel Stack Limit */
|
||||
#define XCHAL_HAVE_ISL 0 /* Interrupt Stack Limit */
|
||||
#define XCHAL_HAVE_PSL 0 /* Pageable Stack Limit */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
EXCEPTIONS and VECTORS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
|
||||
number: 1 == XEA1 (until T1050)
|
||||
2 == XEA2 (LX)
|
||||
3 == XEA3 (NX)
|
||||
0 == XEA5 (RNX) */
|
||||
#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
|
||||
#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
|
||||
#define XCHAL_HAVE_XEA3 0 /* Exception Architecture 3 */
|
||||
#define XCHAL_HAVE_XEA5 0 /* Exception Architecture 5 */
|
||||
#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
|
||||
#define XCHAL_HAVE_IMPRECISE_EXCEPTIONS 0 /* imprecise exception option */
|
||||
#define XCHAL_EXCCAUSE_NUM 64 /* Number of exceptions */
|
||||
#define XCHAL_HAVE_HALT 0 /* halt architecture option */
|
||||
#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
|
||||
#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
|
||||
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
|
||||
#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
|
||||
#define XCHAL_VECBASE_RESET_VADDR 0x24020400 /* VECBASE reset value */
|
||||
#define XCHAL_VECBASE_RESET_PADDR 0x24020400
|
||||
#define XCHAL_RESET_VECBASE_OVERLAP 0 /* UNUSED */
|
||||
|
||||
#define XCHAL_RESET_VECTOR0_VADDR 0x24020000
|
||||
#define XCHAL_RESET_VECTOR0_PADDR 0x24020000
|
||||
#define XCHAL_RESET_VECTOR1_VADDR 0x20100000
|
||||
#define XCHAL_RESET_VECTOR1_PADDR 0x20100000
|
||||
#define XCHAL_RESET_VECTOR_VADDR XCHAL_RESET_VECTOR0_VADDR
|
||||
#define XCHAL_RESET_VECTOR_PADDR XCHAL_RESET_VECTOR0_PADDR
|
||||
#define XCHAL_USER_VECOFS 0x0000021C
|
||||
#define XCHAL_USER_VECTOR_VADDR 0x2402061C
|
||||
#define XCHAL_USER_VECTOR_PADDR 0x2402061C
|
||||
#define XCHAL_KERNEL_VECOFS 0x000001FC
|
||||
#define XCHAL_KERNEL_VECTOR_VADDR 0x240205FC
|
||||
#define XCHAL_KERNEL_VECTOR_PADDR 0x240205FC
|
||||
#define XCHAL_DOUBLEEXC_VECOFS 0x0000023C
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x2402063C
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x2402063C
|
||||
#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
|
||||
#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
|
||||
#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
|
||||
#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
|
||||
#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
|
||||
#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
|
||||
#define XCHAL_WINDOW_VECTORS_VADDR 0x24020400
|
||||
#define XCHAL_WINDOW_VECTORS_PADDR 0x24020400
|
||||
#define XCHAL_INTLEVEL2_VECOFS 0x0000017C
|
||||
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x2402057C
|
||||
#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x2402057C
|
||||
#define XCHAL_INTLEVEL3_VECOFS 0x0000019C
|
||||
#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x2402059C
|
||||
#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x2402059C
|
||||
#define XCHAL_INTLEVEL4_VECOFS 0x000001BC
|
||||
#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x240205BC
|
||||
#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x240205BC
|
||||
#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL4_VECOFS
|
||||
#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR
|
||||
#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR
|
||||
#define XCHAL_NMI_VECOFS 0x000001DC
|
||||
#define XCHAL_NMI_VECTOR_VADDR 0x240205DC
|
||||
#define XCHAL_NMI_VECTOR_PADDR 0x240205DC
|
||||
#define XCHAL_INTLEVEL5_VECOFS XCHAL_NMI_VECOFS
|
||||
#define XCHAL_INTLEVEL5_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
|
||||
#define XCHAL_INTLEVEL5_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
DEBUG MODULE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* Misc */
|
||||
#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */
|
||||
#define XCHAL_HAVE_DEBUG_APB 1 /* APB to debug module */
|
||||
#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
|
||||
|
||||
/* On-Chip Debug (OCD) */
|
||||
#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
|
||||
#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
|
||||
#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
|
||||
#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */
|
||||
#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
|
||||
|
||||
/* TRAX (in core) */
|
||||
#define XCHAL_HAVE_TRAX 0 /* TRAX in debug module */
|
||||
#define XCHAL_TRAX_MEM_SIZE 0 /* TRAX memory size in bytes */
|
||||
#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */
|
||||
#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
|
||||
#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
|
||||
|
||||
/* Perf counters */
|
||||
#define XCHAL_NUM_PERF_COUNTERS 2 /* performance counters */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MMU
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* See core-matmap.h header file for more details. */
|
||||
|
||||
#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
|
||||
#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
|
||||
#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */
|
||||
#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */
|
||||
#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
|
||||
#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
|
||||
#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
|
||||
#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
|
||||
[autorefill] and protection)
|
||||
usable for an MMU-based OS */
|
||||
|
||||
/* If none of the above last 5 are set, it's a custom TLB configuration. */
|
||||
|
||||
#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
|
||||
#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
|
||||
#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MPU
|
||||
----------------------------------------------------------------------*/
|
||||
#define XCHAL_HAVE_MPU 0
|
||||
#define XCHAL_MPU_ENTRIES 0
|
||||
#define XCHAL_MPU_LOCK 0
|
||||
|
||||
#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */
|
||||
#define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/
|
||||
#define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */
|
||||
|
||||
#define XCHAL_MPU_ALIGN_BITS 0
|
||||
#define XCHAL_MPU_ALIGN 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
CSR Parity
|
||||
------------------------------------------------------------------------*/
|
||||
#define XCHAL_HAVE_CSR_PARITY 0
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
FLEX-LOCK
|
||||
------------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_FXLK 0
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
WWDT (Windowed Watchdog Timer)
|
||||
------------------------------------------------------------------------*/
|
||||
#define XCHAL_HAVE_WWDT 0
|
||||
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
|
||||
|
||||
|
||||
#endif /* XTENSA_CORE_CONFIGURATION_H_ */
|
||||
|
||||
Loading…
Reference in New Issue