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nrf_hw_models
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AAR: Switched to level interrupts, readied for nrf53 

* Switched to level interrupts
 * Added DPPI connections
 * Added nrf53 glue and config
 * HAL: Added event and subscription overrides
 * Used code templates for common logic

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This commit is contained in:
Alberto Escolar Piedras 2023-09-19 10:12:53 +02:00
parent fbf58f36b0
commit 75a6cb4fd0
11 changed files with 395 additions and 109 deletions
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2
make_inc/52833_hw_files
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@ -4,7 +4,7 @@ src/HW_models/NRF_PPI.c
src/HW_models/NRF_HWLowL.c
src/HW_models/NRF_GPIO_backend.c
src/HW_models/NHW_EGU.c
src/HW_models/NRF_AAR.c
src/HW_models/NHW_AAR.c
src/HW_models/NRF_RADIO_bitcounter.c
src/HW_models/NRF_RADIO_utils.c
src/HW_models/trivial_xo.c

1
make_inc/5340_hw_files
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@ -6,6 +6,7 @@ src/HW_models/crc.c
src/HW_models/irq_ctrl.c
src/HW_models/bstest_ticker.c
src/HW_models/bs_compat.c
src/HW_models/NHW_AAR.c
src/HW_models/NHW_AES_ECB.c
src/HW_models/NHW_DPPI.c
src/HW_models/NHW_CLOCK.c

1
make_inc/5340_net_hal_files
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@ -1,4 +1,5 @@
src/nrfx/drivers/nrfx_common.c
src/nrfx/hal/nrf_aar.c
src/nrfx/hal/nrf_clock.c
src/nrfx/hal/nrf_dppi.c
src/nrfx/hal/nrf_ecb.c

134
src/HW_models/NRF_AAR.c → src/HW_models/NHW_AAR.c
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@ -8,6 +8,19 @@
/**
* AAR - Accelerated address resolver
* https://infocenter.nordicsemi.com/topic/ps_nrf52833/aar.html?cp=4_1_0_5_1
* https://infocenter.nordicsemi.com/topic/ps_nrf5340/aar.html?cp=4_0_0_6_3
*
* Notes:
* * Unlike in the real HW the AAR peripheral does not share resources with the CCM or ECB peripherals.
* They are actually 2 separate peripherals, so if they are used simultaneously nothing will fail.
* Therefore
* * Starting the AAR block while the ECB block is running will not abort the ECB and
* cause a ERRORECB
* * The AAR register map (including interrupt mask, enable, & task start) does not
* overlap the CCM one.
* * The AAR block could even be used in parallel to the CCM block without conflicts.
* * IMPORTANT: This may change in the future. No embedded SW or tests may rely on this,
* but instead they should behave like they would with real HW.
*/
#include <string.h>
@ -15,71 +28,64 @@
#include <stdint.h>
#include "NHW_config.h"
#include "NHW_common_types.h"
#include "NRF_AAR.h"
#include "NHW_templates.h"
#include "NHW_AAR.h"
#include "nsi_hw_scheduler.h"
#include "NHW_peri_types.h"
#include "NRF_PPI.h"
#include "NHW_xPPI.h"
#include "irq_ctrl.h"
#include "bs_tracing.h"
#include "BLECrypt_if.h"
#include "nsi_tasks.h"
#include "nsi_hws_models_if.h"
#if NHW_AAR_TOTAL_INST > 1
#error "This model only supports 1 instance so far"
#endif
static bs_time_t Timer_AAR = TIME_NEVER; /* Time when the AAR will finish */
NRF_AAR_Type NRF_AAR_regs;
/* Mapping of peripheral instance to {int controller instance, int number} */
static struct nhw_irq_mapping nhw_aar_irq_map[NHW_AAR_TOTAL_INST] = NHW_AAR_INT_MAP;
#if (NHW_HAS_DPPI)
/* Mapping of peripheral instance to DPPI instance */
static uint nhw_AAR_dppi_map[NHW_AAR_TOTAL_INST] = NHW_AAR_DPPI_MAP;
#endif
static uint32_t AAR_INTEN = 0; //interrupt enable
static bool AAR_Running;
static int matching_irk;
static void nrf_aar_init(void) {
static void nhw_aar_init(void) {
memset(&NRF_AAR_regs, 0, sizeof(NRF_AAR_regs));
AAR_INTEN = 0;
Timer_AAR = TIME_NEVER;
AAR_Running = false;
}
NSI_TASK(nrf_aar_init, HW_INIT, 100);
NSI_TASK(nhw_aar_init, HW_INIT, 100);
static int nrf_aar_resolve(int *good_irk);
static int nhw_aar_resolve(int *good_irk);
static void signal_EVENTS_END(void) {
NRF_AAR_regs.EVENTS_END = 1;
nrf_ppi_event(AAR_EVENTS_END);
static void nhw_AAR_eval_interrupt(uint inst) {
static bool aar_int_line[NHW_AAR_TOTAL_INST]; /* Is the AAR currently driving its interrupt line high */
/* Mapping of peripheral instance to {int controller instance, int number} */
static struct nhw_irq_mapping nhw_aar_irq_map[NHW_AAR_TOTAL_INST] = NHW_AAR_INT_MAP;
bool new_int_line = false;
unsigned int inst = 0;
if (AAR_INTEN & AAR_INTENSET_END_Msk){
hw_irq_ctrl_set_irq(nhw_aar_irq_map[inst].cntl_inst,
nhw_aar_irq_map[inst].int_nbr);
}
NHW_CHECK_INTERRUPT_si(AAR, END, AAR_INTEN)
NHW_CHECK_INTERRUPT_si(AAR, RESOLVED, AAR_INTEN)
NHW_CHECK_INTERRUPT_si(AAR, NOTRESOLVED, AAR_INTEN)
hw_irq_ctrl_toggle_level_irq_line_if(&aar_int_line[inst],
new_int_line,
&nhw_aar_irq_map[inst]);
}
static void signal_EVENTS_RESOLVED(void) {
NRF_AAR_regs.EVENTS_RESOLVED = 1;
nrf_ppi_event(AAR_EVENTS_RESOLVED);
NHW_SIGNAL_EVENT_si(AAR, END)
NHW_SIGNAL_EVENT_si(AAR, RESOLVED)
NHW_SIGNAL_EVENT_si(AAR, NOTRESOLVED)
unsigned int inst = 0;
if (AAR_INTEN & AAR_INTENCLR_RESOLVED_Msk){
hw_irq_ctrl_set_irq(nhw_aar_irq_map[inst].cntl_inst,
nhw_aar_irq_map[inst].int_nbr);
}
}
static void signal_EVENTS_NOTRESOLVED(void) {
NRF_AAR_regs.EVENTS_NOTRESOLVED = 1;
nrf_ppi_event(AAR_EVENTS_NOTRESOLVED);
unsigned int inst = 0;
if (AAR_INTEN & AAR_INTENCLR_NOTRESOLVED_Msk){
hw_irq_ctrl_set_irq(nhw_aar_irq_map[inst].cntl_inst,
nhw_aar_irq_map[inst].int_nbr);
}
}
void nrf_aar_TASK_START(void) {
void nhw_AAR_TASK_START(void) {
int n_irks;
if (NRF_AAR_regs.ENABLE != 0x3) {
@ -87,13 +93,13 @@ void nrf_aar_TASK_START(void) {
}
AAR_Running = true;
n_irks = nrf_aar_resolve(&matching_irk);
n_irks = nhw_aar_resolve(&matching_irk);
Timer_AAR = nsi_hws_get_time() + 1 + 6 * n_irks; /*AAR delay*/
Timer_AAR = nsi_hws_get_time() + 1 + NHW_AAR_t_AAR * n_irks; /*AAR delay*/
nsi_hws_find_next_event();
}
void nrf_aar_TASK_STOP(void) {
void nhw_AAR_TASK_STOP(void) {
if (!AAR_Running) {
return;
}
@ -101,55 +107,39 @@ void nrf_aar_TASK_STOP(void) {
AAR_Running = false;
Timer_AAR = TIME_NEVER;
nsi_hws_find_next_event();
signal_EVENTS_END();
nhw_AAR_signal_EVENTS_END(0);
//Does this actually signal an END?
//and only an END?
}
void nrf_aar_regw_sideeffects_INTENSET(void) {
if ( NRF_AAR_regs.INTENSET ){
AAR_INTEN |= NRF_AAR_regs.INTENSET;
NRF_AAR_regs.INTENSET = AAR_INTEN;
}
}
NHW_SIDEEFFECTS_INTSET_si(AAR, NRF_AAR_regs., AAR_INTEN)
NHW_SIDEEFFECTS_INTCLR_si(AAR, NRF_AAR_regs., AAR_INTEN)
void nrf_aar_regw_sideeffects_INTENCLR(void) {
if ( NRF_AAR_regs.INTENCLR ){
AAR_INTEN &= ~NRF_AAR_regs.INTENCLR;
NRF_AAR_regs.INTENSET = AAR_INTEN;
NRF_AAR_regs.INTENCLR = 0;
}
}
NHW_SIDEEFFECTS_EVENTS(AAR)
void nrf_aar_regw_sideeffects_TASKS_START(void) {
if ( NRF_AAR_regs.TASKS_START ) {
NRF_AAR_regs.TASKS_START = 0;
nrf_aar_TASK_START();
}
}
NHW_SIDEEFFECTS_TASKS_si(AAR, START)
NHW_SIDEEFFECTS_TASKS_si(AAR, STOP)
void nrf_aar_regw_sideeffects_TASKS_STOP(void) {
if ( NRF_AAR_regs.TASKS_STOP ) {
NRF_AAR_regs.TASKS_STOP = 0;
nrf_aar_TASK_STOP();
}
}
#if (NHW_HAS_DPPI)
NHW_SIDEEFFECTS_SUBSCRIBE_si(AAR, START)
NHW_SIDEEFFECTS_SUBSCRIBE_si(AAR, STOP)
#endif /* NHW_HAS_DPPI */
static void nrf_aar_timer_triggered(void) {
static void nhw_aar_timer_triggered(void) {
AAR_Running = false;
Timer_AAR = TIME_NEVER;
nsi_hws_find_next_event();
if (matching_irk != -1) {
NRF_AAR_regs.STATUS = matching_irk;
signal_EVENTS_RESOLVED();
nhw_AAR_signal_EVENTS_RESOLVED(0);
} else {
signal_EVENTS_NOTRESOLVED();
nhw_AAR_signal_EVENTS_NOTRESOLVED(0);
}
signal_EVENTS_END();
nhw_AAR_signal_EVENTS_END(0);
}
NSI_HW_EVENT(Timer_AAR, nrf_aar_timer_triggered, 50);
NSI_HW_EVENT(Timer_AAR, nhw_aar_timer_triggered, 50);
/**
* Try to resolve the address
@ -159,7 +149,7 @@ NSI_HW_EVENT(Timer_AAR, nrf_aar_timer_triggered, 50);
* It sets *good_irk to the index of the IRK that matched
* or to -1 if none did.
*/
static int nrf_aar_resolve(int *good_irk) {
static int nhw_aar_resolve(int *good_irk) {
int i;
uint8_t prand_buf[16];
uint8_t hash_check_buf[16];

28
src/HW_models/NHW_AAR.h Normal file
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@ -0,0 +1,28 @@
/*
* Copyright (c) 2017 Oticon A/S
* Copyright (c) 2023 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _NRF_HW_MODEL_AAR_H
#define _NRF_HW_MODEL_AAR_H
#ifdef __cplusplus
extern "C"{
#endif
void nhw_AAR_TASK_START(void);
void nhw_AAR_TASK_STOP(void);
void nhw_AAR_regw_sideeffects_INTENSET(void);
void nhw_AAR_regw_sideeffects_INTENCLR(void);
void nhw_AAR_regw_sideeffects_TASKS_START(void);
void nhw_AAR_regw_sideeffects_TASKS_STOP(void);
void nhw_AAR_regw_sideeffects_SUBSCRIBE_START(unsigned int inst);
void nhw_AAR_regw_sideeffects_SUBSCRIBE_STOP(unsigned int inst);
void nhw_AAR_regw_sideeffects_EVENTS_all(unsigned int inst);
#ifdef __cplusplus
}
#endif
#endif

7
src/HW_models/NHW_config.h
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@ -27,6 +27,7 @@
#define NHW_AAR_TOTAL_INST 1
#define NHW_AAR_0 0
#define NHW_AAR_INT_MAP {{0 , 15}} /*Only core,CCM_AAR_IRQn*/
#define NHW_AAR_t_AAR 6
#define NHW_CCM_TOTAL_INST 1
#define NHW_CCM_0 0
@ -179,6 +180,12 @@
#define NHW_HAS_DPPI 1
#define NHW_USE_MDK_TYPES 0
#define NHW_AAR_TOTAL_INST 1
#define NHW_AAR_NET0 0
#define NHW_AAR_INT_MAP {{1 , 14}} /*Net core,AAR_CCM */
#define NHW_AAR_DPPI_MAP {1}
#define NHW_AAR_t_AAR 6
#define NHW_CLKPWR_TOTAL_INST 2
#define NHW_CLKPWR_APP0 0
#define NHW_CLKPWR_NET0 1

244
src/HW_models/NRF5340_peri_types.h
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@ -95,6 +95,250 @@ typedef struct {
__IOM uint32_t FORCEOFF; /*!< (@ 0x00000004) Force network core off */
} RESET_NETWORK_Type; /*!< Size = 8 (0x8) */
/* =========================================================================================================================== */
/* ================ AAR ================ */
/* =========================================================================================================================== */
/**
* @brief Accelerated Address Resolver (AAR)
*/
typedef struct { /*!< (@ 0x4100E000) AAR_NS Structure */
__OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified
in the IRK data structure */
__IM uint32_t RESERVED;
__OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */
__IM uint32_t RESERVED1[29];
__IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */
__IM uint32_t RESERVED2;
__IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000088) Subscribe configuration for task STOP */
__IM uint32_t RESERVED3[29];
__IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */
__IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */
__IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */
__IM uint32_t RESERVED4[29];
__IOM uint32_t PUBLISH_END; /*!< (@ 0x00000180) Publish configuration for event END */
__IOM uint32_t PUBLISH_RESOLVED; /*!< (@ 0x00000184) Publish configuration for event RESOLVED */
__IOM uint32_t PUBLISH_NOTRESOLVED; /*!< (@ 0x00000188) Publish configuration for event NOTRESOLVED */
__IM uint32_t RESERVED5[94];
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
__IM uint32_t RESERVED6[61];
__IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */
__IM uint32_t RESERVED7[63];
__IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */
__IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */
__IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */
__IM uint32_t RESERVED8;
__IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */
__IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */
} NRF_AAR_Type; /*!< Size = 1304 (0x518) */
/* Peripheral: AAR */
/* Description: Accelerated Address Resolver */
/* Register: AAR_TASKS_START */
/* Description: Start resolving addresses based on IRKs specified in the IRK data structure */
/* Bit 0 : Start resolving addresses based on IRKs specified in the IRK data structure */
#define AAR_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
#define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
#define AAR_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
/* Register: AAR_TASKS_STOP */
/* Description: Stop resolving addresses */
/* Bit 0 : Stop resolving addresses */
#define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
#define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
#define AAR_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
/* Register: AAR_SUBSCRIBE_START */
/* Description: Subscribe configuration for task START */
/* Bit 31 : */
#define AAR_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
#define AAR_SUBSCRIBE_START_EN_Msk (0x1UL << AAR_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
#define AAR_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
#define AAR_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
/* Bits 7..0 : DPPI channel that task START will subscribe to */
#define AAR_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define AAR_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << AAR_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: AAR_SUBSCRIBE_STOP */
/* Description: Subscribe configuration for task STOP */
/* Bit 31 : */
#define AAR_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
#define AAR_SUBSCRIBE_STOP_EN_Msk (0x1UL << AAR_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
#define AAR_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
#define AAR_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
#define AAR_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define AAR_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << AAR_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: AAR_EVENTS_END */
/* Description: Address resolution procedure complete */
/* Bit 0 : Address resolution procedure complete */
#define AAR_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
#define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
#define AAR_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
#define AAR_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
/* Register: AAR_EVENTS_RESOLVED */
/* Description: Address resolved */
/* Bit 0 : Address resolved */
#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field. */
#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of EVENTS_RESOLVED field. */
#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_NotGenerated (0UL) /*!< Event not generated */
#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (1UL) /*!< Event generated */
/* Register: AAR_EVENTS_NOTRESOLVED */
/* Description: Address not resolved */
/* Bit 0 : Address not resolved */
#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field. */
#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask of EVENTS_NOTRESOLVED field. */
#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_NotGenerated (0UL) /*!< Event not generated */
#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (1UL) /*!< Event generated */
/* Register: AAR_PUBLISH_END */
/* Description: Publish configuration for event END */
/* Bit 31 : */
#define AAR_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
#define AAR_PUBLISH_END_EN_Msk (0x1UL << AAR_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
#define AAR_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
#define AAR_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
/* Bits 7..0 : DPPI channel that event END will publish to. */
#define AAR_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define AAR_PUBLISH_END_CHIDX_Msk (0xFFUL << AAR_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: AAR_PUBLISH_RESOLVED */
/* Description: Publish configuration for event RESOLVED */
/* Bit 31 : */
#define AAR_PUBLISH_RESOLVED_EN_Pos (31UL) /*!< Position of EN field. */
#define AAR_PUBLISH_RESOLVED_EN_Msk (0x1UL << AAR_PUBLISH_RESOLVED_EN_Pos) /*!< Bit mask of EN field. */
#define AAR_PUBLISH_RESOLVED_EN_Disabled (0UL) /*!< Disable publishing */
#define AAR_PUBLISH_RESOLVED_EN_Enabled (1UL) /*!< Enable publishing */
/* Bits 7..0 : DPPI channel that event RESOLVED will publish to. */
#define AAR_PUBLISH_RESOLVED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define AAR_PUBLISH_RESOLVED_CHIDX_Msk (0xFFUL << AAR_PUBLISH_RESOLVED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: AAR_PUBLISH_NOTRESOLVED */
/* Description: Publish configuration for event NOTRESOLVED */
/* Bit 31 : */
#define AAR_PUBLISH_NOTRESOLVED_EN_Pos (31UL) /*!< Position of EN field. */
#define AAR_PUBLISH_NOTRESOLVED_EN_Msk (0x1UL << AAR_PUBLISH_NOTRESOLVED_EN_Pos) /*!< Bit mask of EN field. */
#define AAR_PUBLISH_NOTRESOLVED_EN_Disabled (0UL) /*!< Disable publishing */
#define AAR_PUBLISH_NOTRESOLVED_EN_Enabled (1UL) /*!< Enable publishing */
/* Bits 7..0 : DPPI channel that event NOTRESOLVED will publish to. */
#define AAR_PUBLISH_NOTRESOLVED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define AAR_PUBLISH_NOTRESOLVED_CHIDX_Msk (0xFFUL << AAR_PUBLISH_NOTRESOLVED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: AAR_INTENSET */
/* Description: Enable interrupt */
/* Bit 2 : Write '1' to enable interrupt for event NOTRESOLVED */
#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to enable interrupt for event RESOLVED */
#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to enable interrupt for event END */
#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
#define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
#define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
#define AAR_INTENSET_END_Set (1UL) /*!< Enable */
/* Register: AAR_INTENCLR */
/* Description: Disable interrupt */
/* Bit 2 : Write '1' to disable interrupt for event NOTRESOLVED */
#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to disable interrupt for event RESOLVED */
#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to disable interrupt for event END */
#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
#define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
#define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
/* Register: AAR_STATUS */
/* Description: Resolution status */
/* Bits 3..0 : The IRK that was used last time an address was resolved */
#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
/* Register: AAR_ENABLE */
/* Description: Enable AAR */
/* Bits 1..0 : Enable or disable AAR */
#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
#define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */
/* Register: AAR_NIRK */
/* Description: Number of IRKs */
/* Bits 4..0 : Number of Identity Root Keys available in the IRK data structure */
#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
/* Register: AAR_IRKPTR */
/* Description: Pointer to IRK data structure */
/* Bits 31..0 : Pointer to the IRK data structure */
#define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */
#define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */
/* Register: AAR_ADDRPTR */
/* Description: Pointer to the resolvable address */
/* Bits 31..0 : Pointer to the resolvable address (6-bytes) */
#define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */
#define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */
/* Register: AAR_SCRATCHPTR */
/* Description: Pointer to data area used for temporary storage */
/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. */
#define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
#define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
/* =========================================================================================================================== */
/* ================ CLOCK ================ */

24
src/HW_models/NRF_AAR.h
View File

@ -1,24 +0,0 @@
/*
* Copyright (c) 2017 Oticon A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _NRF_HW_MODEL_AAR_H
#define _NRF_HW_MODEL_AAR_H
#ifdef __cplusplus
extern "C"{
#endif
void nrf_aar_TASK_START(void);
void nrf_aar_TASK_STOP(void);
void nrf_aar_regw_sideeffects_INTENSET(void);
void nrf_aar_regw_sideeffects_INTENCLR(void);
void nrf_aar_regw_sideeffects_TASKS_START(void);
void nrf_aar_regw_sideeffects_TASKS_STOP(void);
#ifdef __cplusplus
}
#endif
#endif

6
src/HW_models/NRF_PPI.c
View File

@ -21,7 +21,7 @@
#include <stdint.h>
#include <string.h>
#include "NHW_peri_types.h"
#include "NRF_AAR.h"
#include "NHW_AAR.h"
#include "NRF_AES_CCM.h"
#include "NRF_GPIOTE.h"
#include "NHW_RNG.h"
@ -224,7 +224,7 @@ static const ppi_tasks_table_t ppi_tasks_table[]={ //just the ones we may use
//ECB
//AAR
{ (void*)&NRF_AAR_regs.TASKS_START , nrf_aar_TASK_START},
{ (void*)&NRF_AAR_regs.TASKS_START , nhw_AAR_TASK_START},
//CCM
{ (void*)&NRF_CCM_regs.TASKS_CRYPT , nrf_ccm_TASK_CRYPT},
@ -577,7 +577,7 @@ static void set_fixed_channel_routes(void) {
// 23 RADIO->EVENTS_BCMATCH AAR->TASKS_START
ppi_evt_to_ch[RADIO_EVENTS_BCMATCH].channels_mask |= ( 1 << 23 );
ppi_ch_tasks[23].tep_f = nrf_aar_TASK_START; //AAR->TASKS_START
ppi_ch_tasks[23].tep_f = nhw_AAR_TASK_START; //AAR->TASKS_START
// 24 RADIO->EVENTS_READY CCM->TASKS_KSGEN
ppi_evt_to_ch[RADIO_EVENTS_READY].channels_mask |= ( 1 << 24 );

54
src/nrfx/hal/nrf_aar.c
View File

@ -1,6 +1,6 @@
/*
* Copyright (c) 2020 Oticon A/S
* Copyright (c) 2020 Nordic Semiconductor ASA
* Copyright (c) 2020-2023 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*
@ -8,29 +8,67 @@
*/
#include "hal/nrf_aar.h"
#include "bs_tracing.h"
#include "NRF_AAR.h"
#include "NHW_AAR.h"
void nrf_aar_int_enable(NRF_AAR_Type * p_reg, uint32_t mask)
{
p_reg->INTENSET = mask;
nrf_aar_regw_sideeffects_INTENSET();
nhw_AAR_regw_sideeffects_INTENSET();
}
void nrf_aar_int_disable(NRF_AAR_Type * p_reg, uint32_t mask)
{
p_reg->INTENCLR = mask;
nrf_aar_regw_sideeffects_INTENCLR();
nhw_AAR_regw_sideeffects_INTENCLR();
}
void nrf_aar_task_trigger(NRF_AAR_Type * p_reg, nrf_aar_task_t task)
{
*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task) = 1;
if (task == NRF_AAR_TASK_START) {
p_reg->TASKS_START = 1;
nrf_aar_regw_sideeffects_TASKS_START();
nhw_AAR_regw_sideeffects_TASKS_START();
} else if (task == NRF_AAR_TASK_STOP) {
p_reg->TASKS_STOP = 1;
nrf_aar_regw_sideeffects_TASKS_STOP();
nhw_AAR_regw_sideeffects_TASKS_STOP();
} else {
bs_trace_error_line_time("Not supported task started in nrf_aar\n");
}
}
void nrf_aar_event_clear(NRF_AAR_Type * p_reg, nrf_aar_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
nhw_AAR_regw_sideeffects_EVENTS_all(0);
}
#if defined(DPPI_PRESENT)
static void nrf_aar_subscribe_common(NRF_AAR_Type * p_reg,
nrf_aar_task_t task)
{
if (task == NRF_AAR_TASK_START) {
nhw_AAR_regw_sideeffects_SUBSCRIBE_START(0);
} else if ( task == NRF_AAR_TASK_STOP ) {
nhw_AAR_regw_sideeffects_SUBSCRIBE_STOP(0);
} else {
bs_trace_error_line_time("Attempted to subscribe to an not-supported task in the nrf_aar (%i)\n",
task);
}
}
void nrf_aar_subscribe_set(NRF_AAR_Type * p_reg,
nrf_aar_task_t task,
uint8_t channel)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
nrf_aar_subscribe_common(p_reg, task);
}
void nrf_aar_subscribe_clear(NRF_AAR_Type * p_reg,
nrf_aar_task_t task)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
nrf_aar_subscribe_common(p_reg, task);
}
#endif /* defined(DPPI_PRESENT) */

3
src/nrfx/mdk_replacements/nrf_bsim_redef.h
View File

@ -134,8 +134,9 @@ extern NRF_RNG_Type NRF_RNG_regs;
#undef NRF_ECB_NS_BASE
extern NRF_ECB_Type NRF_ECB_regs;
#define NRF_ECB_NS_BASE (&NRF_ECB_regs)
extern NRF_AAR_Type NRF_AAR_regs;
#undef NRF_AAR_NS_BASE
#define NRF_AAR_NS_BASE NULL
#define NRF_AAR_NS_BASE (&NRF_AAR_regs)
#undef NRF_CCM_NS_BASE
#define NRF_CCM_NS_BASE NULL
extern NRF_DPPIC_Type NRF_DPPIC_regs[];