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nrf_hw_models
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AES_ECB: Switched to level interrupts, readied for nrf53 

* Switched to level interrupts
* Added DPPI connections
* Added nrf53 glue and config
* HAL: Added event and subscription overrides

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This commit is contained in:
Alberto Escolar Piedras 2023-09-18 17:03:31 +02:00
parent d084647bd7
commit fbf58f36b0
11 changed files with 409 additions and 178 deletions
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2
make_inc/52833_hw_files
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@ -10,7 +10,7 @@ src/HW_models/NRF_RADIO_utils.c
src/HW_models/trivial_xo.c
src/HW_models/fake_timer.c
src/HW_models/NRF_RADIO.c
src/HW_models/NRF_AES_ECB.c
src/HW_models/NHW_AES_ECB.c
src/HW_models/crc.c
src/HW_models/irq_ctrl.c
src/HW_models/NHW_RTC.c

1
make_inc/5340_hw_files
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@ -6,6 +6,7 @@ src/HW_models/crc.c
src/HW_models/irq_ctrl.c
src/HW_models/bstest_ticker.c
src/HW_models/bs_compat.c
src/HW_models/NHW_AES_ECB.c
src/HW_models/NHW_DPPI.c
src/HW_models/NHW_CLOCK.c
src/HW_models/NHW_EGU.c

1
make_inc/5340_net_hal_files
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@ -1,6 +1,7 @@
src/nrfx/drivers/nrfx_common.c
src/nrfx/hal/nrf_clock.c
src/nrfx/hal/nrf_dppi.c
src/nrfx/hal/nrf_ecb.c
src/nrfx/hal/nrf_egu.c
src/nrfx/hal/nrf_rng.c
src/nrfx/hal/nrf_rtc.c

153
src/HW_models/NHW_AES_ECB.c Normal file
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@ -0,0 +1,153 @@
/*
* Copyright (c) 2017 Oticon A/S
* Copyright (c) 2023 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* AES electronic codebook mode encryption
* https://infocenter.nordicsemi.com/topic/ps_nrf52833/ecb.html?cp=5_1_0_5_5
* https://infocenter.nordicsemi.com/topic/ps_nrf5340/ecb.html?cp=4_0_0_6_9
*/
#include <string.h>
#include <stdbool.h>
#include <stdint.h>
#include "NHW_common_types.h"
#include "NHW_templates.h"
#include "NHW_config.h"
#include "NHW_peri_types.h"
#include "NHW_AES_ECB.h"
#include "NHW_xPPI.h"
#include "nsi_hw_scheduler.h"
#include "irq_ctrl.h"
#include "bs_tracing.h"
#include "BLECrypt_if.h"
#include "nsi_tasks.h"
#include "nsi_hws_models_if.h"
#if NHW_ECB_TOTAL_INST > 1
#error "This model only supports 1 instance so far"
#endif
static bs_time_t Timer_ECB = TIME_NEVER; /* Time when the ECB will finish */
NRF_ECB_Type NRF_ECB_regs;
#if (NHW_HAS_DPPI)
/* Mapping of peripheral instance to DPPI instance */
static uint nhw_ECB_dppi_map[NHW_ECB_TOTAL_INST] = NHW_ECB_DPPI_MAP;
#endif
static uint32_t ECB_INTEN; /* interrupt enable */
static bool ECB_Running;
static uint ECB_t_ECB = NHW_ECB_t_ECB;
typedef struct {
uint8_t KEY[16]; /* 16 byte AES key */
uint8_t CLEARTEXT[16]; /* 16 byte AES cleartext input block */
uint8_t CIPHERTEXT[16]; /* 16 byte AES ciphertext output block */
} ecbdata_t;
static void nhw_aes_ecb_init(void) {
memset(&NRF_ECB_regs, 0, sizeof(NRF_ECB_regs));
Timer_ECB = TIME_NEVER;
ECB_INTEN = 0;
ECB_Running = false;
}
NSI_TASK(nhw_aes_ecb_init, HW_INIT, 100);
/*
* Cheat interface to adjust the time in microseconds it takes
* for a 16byte AES ECB block to be computed
*/
void nhw_aes_ecb_cheat_set_t_ecb(unsigned int new_t){
ECB_t_ECB = new_t;
}
void nrf_aes_ecb_cheat_set_t_ecb(unsigned int new_t) {
nhw_aes_ecb_cheat_set_t_ecb(new_t);
}
/*
* Cheat interface to reset the time it takes
* for a 16byte AES ECB block to be computed
* to the value specified in the infocenter spec.
*/
void nhw_aes_ecb_cheat_reset_t_ecb(void){
ECB_t_ECB = NHW_ECB_t_ECB;
}
void nrf_aes_ecb_cheat_reset_t_ecb(void){
nhw_aes_ecb_cheat_reset_t_ecb();
}
static void nhw_ECB_eval_interrupt(uint inst) {
static bool ecb_int_line[NHW_ECB_TOTAL_INST]; /* Is the ECB currently driving its interrupt line high */
/* Mapping of peripheral instance to {int controller instance, int number} */
static struct nhw_irq_mapping nhw_ecb_irq_map[NHW_ECB_TOTAL_INST] = NHW_ECB_INT_MAP;
bool new_int_line = false;
NHW_CHECK_INTERRUPT_si(ECB, ENDECB, ECB_INTEN)
NHW_CHECK_INTERRUPT_si(ECB, ERRORECB, ECB_INTEN)
hw_irq_ctrl_toggle_level_irq_line_if(&ecb_int_line[inst],
new_int_line,
&nhw_ecb_irq_map[inst]);
}
NHW_SIGNAL_EVENT_si(ECB, ENDECB)
NHW_SIGNAL_EVENT_si(ECB, ERRORECB)
void nhw_ECB_TASK_STOPECB(void) {
if (!ECB_Running) {
return;
}
ECB_Running = false;
Timer_ECB = TIME_NEVER;
nsi_hws_find_next_event();
nhw_ECB_signal_EVENTS_ERRORECB(0);
}
void nhw_ECB_TASK_STARTECB(void) {
ECB_Running = true;
Timer_ECB = nsi_hws_get_time() + ECB_t_ECB;
nsi_hws_find_next_event();
}
NHW_SIDEEFFECTS_INTSET_si(ECB, NRF_ECB_regs., ECB_INTEN)
NHW_SIDEEFFECTS_INTCLR_si(ECB, NRF_ECB_regs., ECB_INTEN)
NHW_SIDEEFFECTS_EVENTS(ECB)
NHW_SIDEEFFECTS_TASKS_si(ECB, STARTECB)
NHW_SIDEEFFECTS_TASKS_si(ECB, STOPECB)
#if (NHW_HAS_DPPI)
NHW_SIDEEFFECTS_SUBSCRIBE_si(ECB, STARTECB)
NHW_SIDEEFFECTS_SUBSCRIBE_si(ECB, STOPECB)
#endif /* NHW_HAS_DPPI */
static void nhw_ecb_timer_triggered(void) {
ECB_Running = false;
Timer_ECB = TIME_NEVER;
nsi_hws_find_next_event();
ecbdata_t *ecbptr = (ecbdata_t *)NRF_ECB_regs.ECBDATAPTR;
if (!ecbptr) {
bs_trace_error_time_line("NRF_ECB_regs.ECBDATAPT is NULL\n");
} else {
/* Note all KEY, and data are assumed to be big endian ordered */
BLECrypt_if_aes_128(
ecbptr->KEY,
ecbptr->CLEARTEXT,
ecbptr->CIPHERTEXT);
nhw_ECB_signal_EVENTS_ENDECB(0);
}
}
NSI_HW_EVENT(Timer_ECB, nhw_ecb_timer_triggered, 50);

28
src/HW_models/NHW_AES_ECB.h Normal file
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@ -0,0 +1,28 @@
/*
* Copyright (c) 2017 Oticon A/S
* Copyright (c) 2023 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _NRF_HW_MODEL_NHW_AES_ECB_H
#define _NRF_HW_MODEL_NHW_AES_ECB_H
#ifdef __cplusplus
extern "C"{
#endif
void nhw_ecb_regw_sideeffects_INTENSET(void);
void nhw_ecb_regw_sideeffects_INTENCLEAR(void);
void nhw_ECB_regw_sideeffects_TASKS_STARTECB(void);
void nhw_ECB_regw_sideeffects_TASKS_STOPECB(void);
void nhw_ECB_regw_sideeffects_SUBSCRIBE_STARTECB(unsigned int inst);
void nhw_ECB_regw_sideeffects_SUBSCRIBE_STOPECB(unsigned int inst);
void nhw_ECB_regw_sideeffects_EVENTS_all(unsigned int inst);
void nhw_aes_ecb_cheat_set_t_ecb(unsigned int new_t);
void nhw_aes_ecb_cheat_reset_t_ecb(void);
#ifdef __cplusplus
}
#endif
#endif

7
src/HW_models/NHW_config.h
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@ -45,6 +45,7 @@
#define NHW_ECB_TOTAL_INST 1
#define NHW_ECB_0 0
#define NHW_ECB_INT_MAP {{0 , 14}} /*Only core,ECB_IRQn*/
#define NHW_ECB_t_ECB 7 /* 7.2 */
#define NHW_EGU_TOTAL_INST 6
#define NHW_EGU_0 0
@ -194,6 +195,12 @@
#define NHW_CLKPWR_HAS_HFCLK192MCLK 1
#define NHW_CLKPWR_HAS_HFCLK192MCLK_I {1, 0}
#define NHW_ECB_TOTAL_INST 1
#define NHW_ECB_NET0 0
#define NHW_ECB_INT_MAP {{1 , 13}} /*Net core, ECB_IRQn*/
#define NHW_ECB_DPPI_MAP {1}
#define NHW_ECB_t_ECB 6 /* 6.2 */
#define NHW_EGU_TOTAL_INST 7
#define NHW_EGU_APP0 0
#define NHW_EGU_APP1 1

160
src/HW_models/NRF5340_peri_types.h
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@ -848,6 +848,166 @@ typedef struct { /*!< (@ 0x40005000) CLOCK_NS Str
#define CLOCK_HFCLK192MCTRL_HCLK192M_Div2 (1UL) /*!< Divide HFCLK192M by 2 */
#define CLOCK_HFCLK192MCTRL_HCLK192M_Div4 (2UL) /*!< Divide HFCLK192M by 4 */
/* =========================================================================================================================== */
/* ================ ECB_NS ================ */
/* =========================================================================================================================== */
/**
* @brief AES ECB Mode Encryption (ECB_NS)
*/
typedef struct { /*!< (@ 0x4100D000) ECB_NS Structure */
__OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */
__OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */
__IM uint32_t RESERVED[30];
__IOM uint32_t SUBSCRIBE_STARTECB; /*!< (@ 0x00000080) Subscribe configuration for task STARTECB */
__IOM uint32_t SUBSCRIBE_STOPECB; /*!< (@ 0x00000084) Subscribe configuration for task STOPECB */
__IM uint32_t RESERVED1[30];
__IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */
__IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB
task or due to an error */
__IM uint32_t RESERVED2[30];
__IOM uint32_t PUBLISH_ENDECB; /*!< (@ 0x00000180) Publish configuration for event ENDECB */
__IOM uint32_t PUBLISH_ERRORECB; /*!< (@ 0x00000184) Publish configuration for event ERRORECB */
__IM uint32_t RESERVED3[95];
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
__IM uint32_t RESERVED4[126];
__IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */
} NRF_ECB_Type; /*!< Size = 1288 (0x508) */
/* Peripheral: ECB */
/* Description: AES ECB Mode Encryption */
/* Register: ECB_TASKS_STARTECB */
/* Description: Start ECB block encrypt */
/* Bit 0 : Start ECB block encrypt */
#define ECB_TASKS_STARTECB_TASKS_STARTECB_Pos (0UL) /*!< Position of TASKS_STARTECB field. */
#define ECB_TASKS_STARTECB_TASKS_STARTECB_Msk (0x1UL << ECB_TASKS_STARTECB_TASKS_STARTECB_Pos) /*!< Bit mask of TASKS_STARTECB field. */
#define ECB_TASKS_STARTECB_TASKS_STARTECB_Trigger (1UL) /*!< Trigger task */
/* Register: ECB_TASKS_STOPECB */
/* Description: Abort a possible executing ECB operation */
/* Bit 0 : Abort a possible executing ECB operation */
#define ECB_TASKS_STOPECB_TASKS_STOPECB_Pos (0UL) /*!< Position of TASKS_STOPECB field. */
#define ECB_TASKS_STOPECB_TASKS_STOPECB_Msk (0x1UL << ECB_TASKS_STOPECB_TASKS_STOPECB_Pos) /*!< Bit mask of TASKS_STOPECB field. */
#define ECB_TASKS_STOPECB_TASKS_STOPECB_Trigger (1UL) /*!< Trigger task */
/* Register: ECB_SUBSCRIBE_STARTECB */
/* Description: Subscribe configuration for task STARTECB */
/* Bit 31 : */
#define ECB_SUBSCRIBE_STARTECB_EN_Pos (31UL) /*!< Position of EN field. */
#define ECB_SUBSCRIBE_STARTECB_EN_Msk (0x1UL << ECB_SUBSCRIBE_STARTECB_EN_Pos) /*!< Bit mask of EN field. */
#define ECB_SUBSCRIBE_STARTECB_EN_Disabled (0UL) /*!< Disable subscription */
#define ECB_SUBSCRIBE_STARTECB_EN_Enabled (1UL) /*!< Enable subscription */
/* Bits 7..0 : DPPI channel that task STARTECB will subscribe to */
#define ECB_SUBSCRIBE_STARTECB_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define ECB_SUBSCRIBE_STARTECB_CHIDX_Msk (0xFFUL << ECB_SUBSCRIBE_STARTECB_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: ECB_SUBSCRIBE_STOPECB */
/* Description: Subscribe configuration for task STOPECB */
/* Bit 31 : */
#define ECB_SUBSCRIBE_STOPECB_EN_Pos (31UL) /*!< Position of EN field. */
#define ECB_SUBSCRIBE_STOPECB_EN_Msk (0x1UL << ECB_SUBSCRIBE_STOPECB_EN_Pos) /*!< Bit mask of EN field. */
#define ECB_SUBSCRIBE_STOPECB_EN_Disabled (0UL) /*!< Disable subscription */
#define ECB_SUBSCRIBE_STOPECB_EN_Enabled (1UL) /*!< Enable subscription */
/* Bits 7..0 : DPPI channel that task STOPECB will subscribe to */
#define ECB_SUBSCRIBE_STOPECB_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define ECB_SUBSCRIBE_STOPECB_CHIDX_Msk (0xFFUL << ECB_SUBSCRIBE_STOPECB_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: ECB_EVENTS_ENDECB */
/* Description: ECB block encrypt complete */
/* Bit 0 : ECB block encrypt complete */
#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos (0UL) /*!< Position of EVENTS_ENDECB field. */
#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Msk (0x1UL << ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos) /*!< Bit mask of EVENTS_ENDECB field. */
#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_NotGenerated (0UL) /*!< Event not generated */
#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Generated (1UL) /*!< Event generated */
/* Register: ECB_EVENTS_ERRORECB */
/* Description: ECB block encrypt aborted because of a STOPECB task or due to an error */
/* Bit 0 : ECB block encrypt aborted because of a STOPECB task or due to an error */
#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos (0UL) /*!< Position of EVENTS_ERRORECB field. */
#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Msk (0x1UL << ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos) /*!< Bit mask of EVENTS_ERRORECB field. */
#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_NotGenerated (0UL) /*!< Event not generated */
#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Generated (1UL) /*!< Event generated */
/* Register: ECB_PUBLISH_ENDECB */
/* Description: Publish configuration for event ENDECB */
/* Bit 31 : */
#define ECB_PUBLISH_ENDECB_EN_Pos (31UL) /*!< Position of EN field. */
#define ECB_PUBLISH_ENDECB_EN_Msk (0x1UL << ECB_PUBLISH_ENDECB_EN_Pos) /*!< Bit mask of EN field. */
#define ECB_PUBLISH_ENDECB_EN_Disabled (0UL) /*!< Disable publishing */
#define ECB_PUBLISH_ENDECB_EN_Enabled (1UL) /*!< Enable publishing */
/* Bits 7..0 : DPPI channel that event ENDECB will publish to. */
#define ECB_PUBLISH_ENDECB_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define ECB_PUBLISH_ENDECB_CHIDX_Msk (0xFFUL << ECB_PUBLISH_ENDECB_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: ECB_PUBLISH_ERRORECB */
/* Description: Publish configuration for event ERRORECB */
/* Bit 31 : */
#define ECB_PUBLISH_ERRORECB_EN_Pos (31UL) /*!< Position of EN field. */
#define ECB_PUBLISH_ERRORECB_EN_Msk (0x1UL << ECB_PUBLISH_ERRORECB_EN_Pos) /*!< Bit mask of EN field. */
#define ECB_PUBLISH_ERRORECB_EN_Disabled (0UL) /*!< Disable publishing */
#define ECB_PUBLISH_ERRORECB_EN_Enabled (1UL) /*!< Enable publishing */
/* Bits 7..0 : DPPI channel that event ERRORECB will publish to. */
#define ECB_PUBLISH_ERRORECB_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define ECB_PUBLISH_ERRORECB_CHIDX_Msk (0xFFUL << ECB_PUBLISH_ERRORECB_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: ECB_INTENSET */
/* Description: Enable interrupt */
/* Bit 1 : Write '1' to enable interrupt for event ERRORECB */
#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to enable interrupt for event ENDECB */
#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */
/* Register: ECB_INTENCLR */
/* Description: Disable interrupt */
/* Bit 1 : Write '1' to disable interrupt for event ERRORECB */
#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to disable interrupt for event ENDECB */
#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */
/* Register: ECB_ECBDATAPTR */
/* Description: ECB block encrypt memory pointers */
/* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */
#define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */
#define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */
/* =========================================================================================================================== */
/* ================ EGU ================ */

161
src/HW_models/NRF_AES_ECB.c
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@ -1,161 +0,0 @@
/*
* Copyright (c) 2017 Oticon A/S
* Copyright (c) 2023 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* AES electronic codebook mode encryption
* https://infocenter.nordicsemi.com/topic/ps_nrf52833/ecb.html?cp=5_1_0_5_5
*/
#include <string.h>
#include <stdbool.h>
#include <stdint.h>
#include "NHW_common_types.h"
#include "NHW_config.h"
#include "NHW_peri_types.h"
#include "NRF_AES_ECB.h"
#include "NRF_PPI.h"
#include "nsi_hw_scheduler.h"
#include "irq_ctrl.h"
#include "bs_tracing.h"
#include "BLECrypt_if.h"
#include "nsi_tasks.h"
#include "nsi_hws_models_if.h"
static bs_time_t Timer_ECB = TIME_NEVER; /* Time when the ECB will finish */
NRF_ECB_Type NRF_ECB_regs;
/* Mapping of peripheral instance to {int controller instance, int number} */
static struct nhw_irq_mapping nhw_ecb_irq_map[NHW_ECB_TOTAL_INST] = NHW_ECB_INT_MAP;
static uint32_t ECB_INTEN; /* interrupt enable */
static bool ECB_Running;
#define DEFAULT_t_ECB 7
static uint ECB_t_ECB = DEFAULT_t_ECB;
typedef struct {
uint8_t KEY[16]; /* 16 byte AES key */
uint8_t CLEARTEXT[16]; /* 16 byte AES cleartext input block */
uint8_t CIPHERTEXT[16]; /* 16 byte AES ciphertext output block */
} ecbdata_t;
static void nrf_aes_ecb_init(void) {
memset(&NRF_ECB_regs, 0, sizeof(NRF_ECB_regs));
Timer_ECB = TIME_NEVER;
ECB_INTEN = 0;
ECB_Running = false;
}
NSI_TASK(nrf_aes_ecb_init, HW_INIT, 100);
/*
* Cheat interface to adjust the time in microseconds it takes
* for a 16byte AES ECB block to be computed
*/
void nrf_aes_ecb_cheat_set_t_ecb(unsigned int new_t){
ECB_t_ECB = new_t;
}
/*
* Cheat interface to reset the time it takes
* for a 16byte AES ECB block to be computed
* to the value specified in the infocenter spec.
*/
void nrf_aes_ecb_cheat_reset_t_ecb(void){
ECB_t_ECB = DEFAULT_t_ECB;
}
static void signal_ENDECB(void) {
NRF_ECB_regs.EVENTS_ENDECB = 1;
nrf_ppi_event(ECB_EVENTS_ENDECB);
int inst = 0;
if (ECB_INTEN & ECB_INTENSET_ENDECB_Msk){
hw_irq_ctrl_set_irq(nhw_ecb_irq_map[inst].cntl_inst,
nhw_ecb_irq_map[inst].int_nbr);
}
}
static void signal_ERRORECB(void) {
NRF_ECB_regs.EVENTS_ERRORECB = 1;
nrf_ppi_event(ECB_EVENTS_ERRORECB);
int inst = 0;
if (ECB_INTEN & ECB_INTENSET_ERRORECB_Msk){
hw_irq_ctrl_set_irq(nhw_ecb_irq_map[inst].cntl_inst,
nhw_ecb_irq_map[inst].int_nbr);
}
}
void nrf_ecb_TASK_STOPECB(void) {
if (!ECB_Running) {
return;
}
ECB_Running = false;
Timer_ECB = TIME_NEVER;
nsi_hws_find_next_event();
signal_ERRORECB();
}
void nrf_ecb_TASK_STARTECB(void) {
ECB_Running = true;
Timer_ECB = nsi_hws_get_time() + ECB_t_ECB;
nsi_hws_find_next_event();
}
void nrf_ecb_regw_sideeffects_INTENSET(void) {
if ( NRF_ECB_regs.INTENSET ) {
ECB_INTEN |= NRF_ECB_regs.INTENSET;
NRF_ECB_regs.INTENSET = ECB_INTEN;
}
}
void nrf_ecb_regw_sideeffects_INTENCLEAR(void) {
if ( NRF_ECB_regs.INTENCLR ) {
ECB_INTEN &= ~NRF_ECB_regs.INTENCLR;
NRF_ECB_regs.INTENSET = ECB_INTEN;
NRF_ECB_regs.INTENCLR = 0;
}
}
void nrf_ecb_regw_sideeffects_TASKS_STARTECB(void) {
if ( NRF_ECB_regs.TASKS_STARTECB ) {
NRF_ECB_regs.TASKS_STARTECB = 0;
nrf_ecb_TASK_STARTECB();
}
}
void nrf_ecb_regw_sideeffects_TASKS_STOPECB(void) {
if ( NRF_ECB_regs.TASKS_STOPECB ) {
NRF_ECB_regs.TASKS_STOPECB = 0;
nrf_ecb_TASK_STOPECB();
}
}
static void nrf_ecb_timer_triggered(void) {
ECB_Running = false;
Timer_ECB = TIME_NEVER;
nsi_hws_find_next_event();
ecbdata_t *ecbptr = (ecbdata_t *)NRF_ECB_regs.ECBDATAPTR;
if (!ecbptr) {
bs_trace_error_time_line("NRF_ECB_regs.ECBDATAPT is NULL\n");
} else {
/* Note all KEY, and data are assumed to be big endian ordered */
BLECrypt_if_aes_128(
ecbptr->KEY,
ecbptr->CLEARTEXT,
ecbptr->CIPHERTEXT);
signal_ENDECB();
}
}
NSI_HW_EVENT(Timer_ECB, nrf_ecb_timer_triggered, 50);

17
src/HW_models/NRF_AES_ECB.h
View File

@ -1,19 +1,22 @@
/*
* Copyright (c) 2017 Oticon A/S
* Copyright (c) 2023 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _NRF_HW_MODEL_AES_ECB_H
#define _NRF_HW_MODEL_AES_ECB_H
/*
* This header exists only for backwards compatibility
* please use NHW_AES_ECB.h instead
*/
#ifndef _NRF_HW_MODEL_NRF_AES_ECB_H
#define _NRF_HW_MODEL_NRF_AES_ECB_H
#include "NHW_AES_ECB.h"
#ifdef __cplusplus
extern "C"{
#endif
void nrf_ecb_regw_sideeffects_INTENSET(void);
void nrf_ecb_regw_sideeffects_INTENCLEAR(void);
void nrf_ecb_regw_sideeffects_TASKS_STARTECB(void);
void nrf_ecb_regw_sideeffects_TASKS_STOPECB(void);
void nrf_aes_ecb_cheat_set_t_ecb(unsigned int new_t);
void nrf_aes_ecb_cheat_reset_t_ecb(void);

54
src/nrfx/hal/nrf_ecb.c
View File

@ -7,30 +7,68 @@
*/
#include "hal/nrf_ecb.h"
#include "bs_tracing.h"
#include "NRF_AES_ECB.h"
#include "NHW_AES_ECB.h"
void nrf_ecb_task_trigger(NRF_ECB_Type * p_reg, nrf_ecb_task_t task)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
if ( task == NRF_ECB_TASK_STARTECB ) {
p_reg->TASKS_STARTECB = 1;
nrf_ecb_regw_sideeffects_TASKS_STARTECB();
nhw_ECB_regw_sideeffects_TASKS_STARTECB();
} else if ( task == NRF_ECB_TASK_STOPECB ) {
p_reg->TASKS_STOPECB = 1;
nrf_ecb_regw_sideeffects_TASKS_STOPECB();
nhw_ECB_regw_sideeffects_TASKS_STOPECB();
} else {
bs_trace_error_line_time("Not supported task started in nrf_ecb\n");
}
}
void nrf_ecb_int_enable(NRF_ECB_Type * p_reg, uint32_t mask)
{
p_reg->INTENSET = mask;
nrf_ecb_regw_sideeffects_INTENSET();
nhw_ecb_regw_sideeffects_INTENSET();
}
void nrf_ecb_int_disable(NRF_ECB_Type * p_reg, uint32_t mask)
{
p_reg->INTENCLR = mask;
nrf_ecb_regw_sideeffects_INTENCLEAR();
nhw_ecb_regw_sideeffects_INTENCLEAR();
}
void nrf_ecb_event_clear(NRF_ECB_Type * p_reg, nrf_ecb_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
nhw_ECB_regw_sideeffects_EVENTS_all(0);
}
#if defined(DPPI_PRESENT)
static void nrf_ecb_subscribe_common(NRF_ECB_Type * p_reg,
nrf_ecb_task_t task)
{
if (task == NRF_ECB_TASK_STARTECB) {
nhw_ECB_regw_sideeffects_SUBSCRIBE_STARTECB(0);
} else if ( task == NRF_ECB_TASK_STOPECB ) {
nhw_ECB_regw_sideeffects_SUBSCRIBE_STOPECB(0);
} else {
bs_trace_error_line_time("Attempted to subscribe to an not-supported task in the nrf_ecb (%i)\n",
task);
}
}
void nrf_ecb_subscribe_set(NRF_ECB_Type * p_reg,
nrf_ecb_task_t task,
uint8_t channel)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
nrf_ecb_subscribe_common(p_reg, task);
}
void nrf_ecb_subscribe_clear(NRF_ECB_Type * p_reg,
nrf_ecb_task_t task)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
nrf_ecb_subscribe_common(p_reg, task);
}
#endif /* defined(DPPI_PRESENT) */

3
src/nrfx/mdk_replacements/nrf_bsim_redef.h
View File

@ -132,7 +132,8 @@ extern NRF_RNG_Type NRF_RNG_regs;
#undef NRF_WDT_NS_BASE
#define NRF_WDT_NS_BASE NULL
#undef NRF_ECB_NS_BASE
#define NRF_ECB_NS_BASE NULL
extern NRF_ECB_Type NRF_ECB_regs;
#define NRF_ECB_NS_BASE (&NRF_ECB_regs)
#undef NRF_AAR_NS_BASE
#define NRF_AAR_NS_BASE NULL
#undef NRF_CCM_NS_BASE