TEMP: Switched to level interrupts, readied for nrf53
* Switched to level interrupts * Added DPPI connections * Added nrf53 glue and config * HAL: Added event and subscription overrides * Used code templates for common logic Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This commit is contained in:
Alberto Escolar Piedras
parent
6ef00694e4
commit
709f82bb69
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@ -18,7 +18,7 @@ src/HW_models/NHW_RTC.c
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src/HW_models/bstest_ticker.c
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src/HW_models/NRF_NVMC.c
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src/HW_models/NRF_GPIO.c
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src/HW_models/NRF_TEMP.c
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src/HW_models/NHW_TEMP.c
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src/HW_models/NRF_RADIO_tasks_regs.c
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src/HW_models/NHW_TIMER.c
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src/HW_models/bs_compat.c
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@ -17,4 +17,5 @@ src/HW_models/NHW_RNG.c
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src/HW_models/NHW_RTC.c
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src/HW_models/NHW_SWI.c
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src/HW_models/NHW_TIMER.c
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src/HW_models/NHW_TEMP.c
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src/HW_models/weak_stubs.c
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@ -7,5 +7,6 @@ src/nrfx/hal/nrf_ecb.c
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src/nrfx/hal/nrf_egu.c
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src/nrfx/hal/nrf_rng.c
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src/nrfx/hal/nrf_rtc.c
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src/nrfx/hal/nrf_temp.c
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src/nrfx/hal/nrf_timer.c
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src/nrfx/hal/nrf_hal_originals.c
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@ -0,0 +1,166 @@
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/*
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* Copyright (c) 2023 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* TEMP - Temperature sensor
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* https://infocenter.nordicsemi.com/topic/ps_nrf52833/temp.html?cp=4_1_0_5_25
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*
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* A very simple and rough model
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*
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* Notes:
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* * At this point the device is always at 25 C
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* * The measurement result will just be 25 +- 0.25 C
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* * There is no per device variability
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* * There is no modeling of possible calibration errors or inaccuracies due to no non-linearities compensation
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*/
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#include <string.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include "bs_rand_main.h"
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#include "nsi_tasks.h"
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#include "nsi_hws_models_if.h"
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#include "nsi_hw_scheduler.h"
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#include "NHW_common_types.h"
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#include "NHW_config.h"
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#include "NHW_templates.h"
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#include "NHW_TEMP.h"
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#include "NHW_peri_types.h"
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#include "NHW_xPPI.h"
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#include "irq_ctrl.h"
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#if NHW_TEMP_TOTAL_INST > 1
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#error "This model only supports 1 instance so far"
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#endif
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NRF_TEMP_Type NRF_TEMP_regs;
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#if (NHW_HAS_DPPI)
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/* Mapping of peripheral instance to DPPI instance */
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static uint nhw_TEMP_dppi_map[NHW_TEMP_TOTAL_INST] = NHW_TEMP_DPPI_MAP;
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#endif
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static bs_time_t Timer_TEMP = TIME_NEVER; //Time when the next temperature measurement will be ready
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static bool TEMP_hw_started;
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static uint32_t TEMP_INTEN; //interrupt enable
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static double temperature = 25.0; /* Actual temperature the device is at */
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/**
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* Initialize the TEMP model
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*/
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static void nhw_temp_init(void) {
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memset(&NRF_TEMP_regs, 0, sizeof(NRF_TEMP_regs));
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#if defined(NRF52833)
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NRF_TEMP_regs.A0 = 0x00000326;
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NRF_TEMP_regs.A1 = 0x00000348;
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NRF_TEMP_regs.A2 = 0x000003AA;
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NRF_TEMP_regs.A3 = 0x0000040E;
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NRF_TEMP_regs.A4 = 0x000004BD;
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NRF_TEMP_regs.A5 = 0x000005A3;
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NRF_TEMP_regs.B0 = 0x00003FEF;
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NRF_TEMP_regs.B1 = 0x00003FBE;
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NRF_TEMP_regs.B2 = 0x00003FBE;
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NRF_TEMP_regs.B3 = 0x00000012;
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NRF_TEMP_regs.B4 = 0x00000124;
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NRF_TEMP_regs.B5 = 0x0000027C;
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NRF_TEMP_regs.T0 = 0x000000E2;
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NRF_TEMP_regs.T1 = 0x00000000;
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NRF_TEMP_regs.T2 = 0x00000019;
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NRF_TEMP_regs.T3 = 0x0000003C;
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NRF_TEMP_regs.T4 = 0x00000050;
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#elif defined(NRF5340)
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NRF_TEMP_regs.A0 = 0x000002D9;
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NRF_TEMP_regs.A1 = 0x00000322;
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NRF_TEMP_regs.A2 = 0x00000355;
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NRF_TEMP_regs.A3 = 0x000003DF;
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NRF_TEMP_regs.A4 = 0x0000044E;
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NRF_TEMP_regs.A5 = 0x000004B7;
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NRF_TEMP_regs.B0 = 0x00000FC7;
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NRF_TEMP_regs.B1 = 0x00000F71;
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NRF_TEMP_regs.B2 = 0x00000F6C;
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NRF_TEMP_regs.B3 = 0x00000FCB;
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NRF_TEMP_regs.B4 = 0x0000004B;
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NRF_TEMP_regs.B5 = 0x000000F6;
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NRF_TEMP_regs.T0 = 0x000000E1;
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NRF_TEMP_regs.T1 = 0x000000F9;
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NRF_TEMP_regs.T2 = 0x00000010;
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NRF_TEMP_regs.T3 = 0x00000026;
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NRF_TEMP_regs.T4 = 0x0000003F;
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#endif
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TEMP_hw_started = false;
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TEMP_INTEN = 0;
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Timer_TEMP = TIME_NEVER;
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}
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NSI_TASK(nhw_temp_init, HW_INIT, 100);
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/**
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* TASK_START triggered handler
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*/
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void nhw_TEMP_TASK_START(void) {
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if (TEMP_hw_started) {
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return;
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}
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TEMP_hw_started = true;
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Timer_TEMP = nsi_hws_get_time() + NHW_TEMP_t_TEMP;
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nsi_hws_find_next_event();
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}
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/**
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* TASK_STOP triggered handler
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*/
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void nhw_TEMP_TASK_STOP(void) {
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TEMP_hw_started = false;
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Timer_TEMP = TIME_NEVER;
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nsi_hws_find_next_event();
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}
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static void nhw_TEMP_eval_interrupt(uint inst) {
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static bool temp_int_line[NHW_TEMP_TOTAL_INST]; /* Is the TEMP currently driving its interrupt line high */
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/* Mapping of peripheral instance to {int controller instance, int number} */
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static struct nhw_irq_mapping nhw_temp_irq_map[NHW_TEMP_TOTAL_INST] = NHW_TEMP_INT_MAP;
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bool new_int_line = false;
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NHW_CHECK_INTERRUPT_si(TEMP, DATARDY, TEMP_INTEN)
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hw_irq_ctrl_toggle_level_irq_line_if(&temp_int_line[inst],
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new_int_line,
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&nhw_temp_irq_map[inst]);
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}
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NHW_SIDEEFFECTS_INTSET_si(TEMP, NRF_TEMP_regs., TEMP_INTEN)
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NHW_SIDEEFFECTS_INTCLR_si(TEMP, NRF_TEMP_regs., TEMP_INTEN)
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NHW_SIDEEFFECTS_EVENTS(TEMP)
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NHW_SIDEEFFECTS_TASKS_si(TEMP, START)
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NHW_SIDEEFFECTS_TASKS_si(TEMP, STOP)
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#if (NHW_HAS_DPPI)
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NHW_SIDEEFFECTS_SUBSCRIBE_si(TEMP, START)
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NHW_SIDEEFFECTS_SUBSCRIBE_si(TEMP, STOP)
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#endif /* NHW_HAS_DPPI */
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NHW_SIGNAL_EVENT_si(TEMP, DATARDY)
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/**
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* Time has come when the temperature measurement is ready
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*/
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static void nhw_temp_timer_triggered(void) {
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NRF_TEMP_regs.TEMP = temperature*(1 << NHW_TEMP_FBITS) + bs_random_uniformRi(-1,1);
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TEMP_hw_started = false;
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Timer_TEMP = TIME_NEVER;
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nsi_hws_find_next_event();
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nhw_TEMP_signal_EVENTS_DATARDY(0);
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}
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NSI_HW_EVENT(Timer_TEMP, nhw_temp_timer_triggered, 50);
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@ -0,0 +1,27 @@
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/*
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* Copyright (c) 2020 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _NRF_HW_MODEL_TEMP_H
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#define _NRF_HW_MODEL_TEMP_H
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#ifdef __cplusplus
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extern "C"{
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#endif
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void nhw_TEMP_regw_sideeffects_TASKS_START(void);
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void nhw_TEMP_regw_sideeffects_TASKS_STOP(void);
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void nhw_TEMP_regw_sideeffects_INTENSET(void);
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void nhw_TEMP_regw_sideeffects_INTENCLEAR(void);
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void nhw_TEMP_TASK_START(void);
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void nhw_TEMP_TASK_STOP(void);
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void nhw_TEMP_regw_sideeffects_SUBSCRIBE_START(unsigned int inst);
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void nhw_TEMP_regw_sideeffects_SUBSCRIBE_STOP(unsigned int inst);
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void nhw_TEMP_regw_sideeffects_EVENTS_all(unsigned int inst);
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#ifdef __cplusplus
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}
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#endif
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#endif
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@ -142,6 +142,8 @@
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#define NHW_TEMP_TOTAL_INST 1
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#define NHW_TEMP_0 0
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#define NHW_TEMP_INT_MAP {{0 , 12}} /*Only core,TEMP_IRQn*/
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#define NHW_TEMP_t_TEMP 36 /* microseconds */
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#define NHW_TEMP_FBITS 2 /* fractional bits => 0.25C resolution */
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#define NHW_TIMER_TOTAL_INST 5
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#define NHW_TIMER_0 0
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#define NHW_SWI_NET2 2
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#define NHW_SWI_NET3 3
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#define NHW_TEMP_TOTAL_INST 1
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#define NHW_TEMP_NET0 0
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#define NHW_TEMP_INT_MAP {{1 , 16}} /*Net core,TEMP_IRQn*/
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#define NHW_TEMP_DPPI_MAP {1} /*Network core*/
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#define NHW_TEMP_t_TEMP 36 /* microseconds */
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#define NHW_TEMP_FBITS 2 /* fractional bits => 0.25C resolution */
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#define NHW_TIMER_TOTAL_INST 6
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#define NHW_TIMER_APP0 0
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#define NHW_TIMER_APP1 1
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@ -2491,6 +2491,267 @@ typedef struct { /*!< (@ 0x41011000) RTC0_NS Stru
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#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
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/* =========================================================================================================================== */
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/* ================ TEMP ================ */
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/* =========================================================================================================================== */
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/**
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* @brief Temperature Sensor (TEMP)
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*/
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typedef struct { /*!< (@ 0x41010000) TEMP_NS Structure */
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__OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */
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__OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */
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__IM uint32_t RESERVED[30];
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__IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */
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__IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */
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__IM uint32_t RESERVED1[30];
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__IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */
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__IM uint32_t RESERVED2[31];
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__IOM uint32_t PUBLISH_DATARDY; /*!< (@ 0x00000180) Publish configuration for event DATARDY */
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__IM uint32_t RESERVED3[96];
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__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
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__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
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__IM uint32_t RESERVED4[127];
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__IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */
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__IM uint32_t RESERVED5[5];
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__IOM uint32_t A0; /*!< (@ 0x00000520) Slope of first piecewise linear function */
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__IOM uint32_t A1; /*!< (@ 0x00000524) Slope of second piecewise linear function */
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__IOM uint32_t A2; /*!< (@ 0x00000528) Slope of third piecewise linear function */
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__IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of fourth piecewise linear function */
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__IOM uint32_t A4; /*!< (@ 0x00000530) Slope of fifth piecewise linear function */
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__IOM uint32_t A5; /*!< (@ 0x00000534) Slope of sixth piecewise linear function */
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__IM uint32_t RESERVED6[2];
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__IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of first piecewise linear function */
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__IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of second piecewise linear function */
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__IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of third piecewise linear function */
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__IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of fourth piecewise linear function */
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__IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of fifth piecewise linear function */
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__IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of sixth piecewise linear function */
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__IM uint32_t RESERVED7[2];
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__IOM uint32_t T0; /*!< (@ 0x00000560) Endpoint of first piecewise linear function */
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__IOM uint32_t T1; /*!< (@ 0x00000564) Endpoint of second piecewise linear function */
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__IOM uint32_t T2; /*!< (@ 0x00000568) Endpoint of third piecewise linear function */
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__IOM uint32_t T3; /*!< (@ 0x0000056C) Endpoint of fourth piecewise linear function */
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__IOM uint32_t T4; /*!< (@ 0x00000570) Endpoint of fifth piecewise linear function */
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} NRF_TEMP_Type; /*!< Size = 1396 (0x574) */
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/* Peripheral: TEMP */
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/* Description: Temperature Sensor */
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/* Register: TEMP_TASKS_START */
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/* Description: Start temperature measurement */
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/* Bit 0 : Start temperature measurement */
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#define TEMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
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#define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
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#define TEMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
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/* Register: TEMP_TASKS_STOP */
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/* Description: Stop temperature measurement */
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/* Bit 0 : Stop temperature measurement */
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#define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
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#define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
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#define TEMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
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/* Register: TEMP_SUBSCRIBE_START */
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/* Description: Subscribe configuration for task START */
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/* Bit 31 : */
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#define TEMP_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
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#define TEMP_SUBSCRIBE_START_EN_Msk (0x1UL << TEMP_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
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#define TEMP_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
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#define TEMP_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
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/* Bits 7..0 : DPPI channel that task START will subscribe to */
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#define TEMP_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
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#define TEMP_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TEMP_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
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/* Register: TEMP_SUBSCRIBE_STOP */
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/* Description: Subscribe configuration for task STOP */
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/* Bit 31 : */
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#define TEMP_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
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#define TEMP_SUBSCRIBE_STOP_EN_Msk (0x1UL << TEMP_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
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#define TEMP_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
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#define TEMP_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
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/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
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#define TEMP_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
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#define TEMP_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TEMP_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
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/* Register: TEMP_EVENTS_DATARDY */
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/* Description: Temperature measurement complete, data ready */
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/* Bit 0 : Temperature measurement complete, data ready */
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#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field. */
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#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of EVENTS_DATARDY field. */
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#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_NotGenerated (0UL) /*!< Event not generated */
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#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Generated (1UL) /*!< Event generated */
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/* Register: TEMP_PUBLISH_DATARDY */
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/* Description: Publish configuration for event DATARDY */
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/* Bit 31 : */
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#define TEMP_PUBLISH_DATARDY_EN_Pos (31UL) /*!< Position of EN field. */
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#define TEMP_PUBLISH_DATARDY_EN_Msk (0x1UL << TEMP_PUBLISH_DATARDY_EN_Pos) /*!< Bit mask of EN field. */
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#define TEMP_PUBLISH_DATARDY_EN_Disabled (0UL) /*!< Disable publishing */
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#define TEMP_PUBLISH_DATARDY_EN_Enabled (1UL) /*!< Enable publishing */
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/* Bits 7..0 : DPPI channel that event DATARDY will publish to. */
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#define TEMP_PUBLISH_DATARDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
|
||||
#define TEMP_PUBLISH_DATARDY_CHIDX_Msk (0xFFUL << TEMP_PUBLISH_DATARDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
|
||||
|
||||
/* Register: TEMP_INTENSET */
|
||||
/* Description: Enable interrupt */
|
||||
|
||||
/* Bit 0 : Write '1' to enable interrupt for event DATARDY */
|
||||
#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
|
||||
#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
|
||||
#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
|
||||
#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
|
||||
#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */
|
||||
|
||||
/* Register: TEMP_INTENCLR */
|
||||
/* Description: Disable interrupt */
|
||||
|
||||
/* Bit 0 : Write '1' to disable interrupt for event DATARDY */
|
||||
#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
|
||||
#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
|
||||
#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
|
||||
#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
|
||||
#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */
|
||||
|
||||
/* Register: TEMP_TEMP */
|
||||
/* Description: Temperature in degC (0.25deg steps) */
|
||||
|
||||
/* Bits 31..0 : Temperature in degC (0.25deg steps) */
|
||||
#define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */
|
||||
#define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */
|
||||
|
||||
/* Register: TEMP_A0 */
|
||||
/* Description: Slope of first piecewise linear function */
|
||||
|
||||
/* Bits 11..0 : Slope of first piecewise linear function */
|
||||
#define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */
|
||||
#define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */
|
||||
|
||||
/* Register: TEMP_A1 */
|
||||
/* Description: Slope of second piecewise linear function */
|
||||
|
||||
/* Bits 11..0 : Slope of second piecewise linear function */
|
||||
#define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */
|
||||
#define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */
|
||||
|
||||
/* Register: TEMP_A2 */
|
||||
/* Description: Slope of third piecewise linear function */
|
||||
|
||||
/* Bits 11..0 : Slope of third piecewise linear function */
|
||||
#define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */
|
||||
#define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */
|
||||
|
||||
/* Register: TEMP_A3 */
|
||||
/* Description: Slope of fourth piecewise linear function */
|
||||
|
||||
/* Bits 11..0 : Slope of fourth piecewise linear function */
|
||||
#define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */
|
||||
#define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */
|
||||
|
||||
/* Register: TEMP_A4 */
|
||||
/* Description: Slope of fifth piecewise linear function */
|
||||
|
||||
/* Bits 11..0 : Slope of fifth piecewise linear function */
|
||||
#define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */
|
||||
#define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */
|
||||
|
||||
/* Register: TEMP_A5 */
|
||||
/* Description: Slope of sixth piecewise linear function */
|
||||
|
||||
/* Bits 11..0 : Slope of sixth piecewise linear function */
|
||||
#define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */
|
||||
#define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */
|
||||
|
||||
/* Register: TEMP_B0 */
|
||||
/* Description: y-intercept of first piecewise linear function */
|
||||
|
||||
/* Bits 11..0 : y-intercept of first piecewise linear function */
|
||||
#define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */
|
||||
#define TEMP_B0_B0_Msk (0xFFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */
|
||||
|
||||
/* Register: TEMP_B1 */
|
||||
/* Description: y-intercept of second piecewise linear function */
|
||||
|
||||
/* Bits 11..0 : y-intercept of second piecewise linear function */
|
||||
#define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */
|
||||
#define TEMP_B1_B1_Msk (0xFFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */
|
||||
|
||||
/* Register: TEMP_B2 */
|
||||
/* Description: y-intercept of third piecewise linear function */
|
||||
|
||||
/* Bits 11..0 : y-intercept of third piecewise linear function */
|
||||
#define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */
|
||||
#define TEMP_B2_B2_Msk (0xFFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */
|
||||
|
||||
/* Register: TEMP_B3 */
|
||||
/* Description: y-intercept of fourth piecewise linear function */
|
||||
|
||||
/* Bits 11..0 : y-intercept of fourth piecewise linear function */
|
||||
#define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */
|
||||
#define TEMP_B3_B3_Msk (0xFFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */
|
||||
|
||||
/* Register: TEMP_B4 */
|
||||
/* Description: y-intercept of fifth piecewise linear function */
|
||||
|
||||
/* Bits 11..0 : y-intercept of fifth piecewise linear function */
|
||||
#define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */
|
||||
#define TEMP_B4_B4_Msk (0xFFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */
|
||||
|
||||
/* Register: TEMP_B5 */
|
||||
/* Description: y-intercept of sixth piecewise linear function */
|
||||
|
||||
/* Bits 11..0 : y-intercept of sixth piecewise linear function */
|
||||
#define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */
|
||||
#define TEMP_B5_B5_Msk (0xFFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */
|
||||
|
||||
/* Register: TEMP_T0 */
|
||||
/* Description: Endpoint of first piecewise linear function */
|
||||
|
||||
/* Bits 7..0 : Endpoint of first piecewise linear function */
|
||||
#define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */
|
||||
#define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */
|
||||
|
||||
/* Register: TEMP_T1 */
|
||||
/* Description: Endpoint of second piecewise linear function */
|
||||
|
||||
/* Bits 7..0 : Endpoint of second piecewise linear function */
|
||||
#define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */
|
||||
#define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
|
||||
|
||||
/* Register: TEMP_T2 */
|
||||
/* Description: Endpoint of third piecewise linear function */
|
||||
|
||||
/* Bits 7..0 : Endpoint of third piecewise linear function */
|
||||
#define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */
|
||||
#define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */
|
||||
|
||||
/* Register: TEMP_T3 */
|
||||
/* Description: Endpoint of fourth piecewise linear function */
|
||||
|
||||
/* Bits 7..0 : Endpoint of fourth piecewise linear function */
|
||||
#define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */
|
||||
#define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */
|
||||
|
||||
/* Register: TEMP_T4 */
|
||||
/* Description: Endpoint of fifth piecewise linear function */
|
||||
|
||||
/* Bits 7..0 : Endpoint of fifth piecewise linear function */
|
||||
#define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */
|
||||
#define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */
|
||||
|
||||
|
||||
|
||||
/* =========================================================================================================================== */
|
||||
/* ================ TIMER ================ */
|
||||
|
|
|
|||
|
|
@ -1,158 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/*
|
||||
* TEMP - Temperature sensor
|
||||
* https://infocenter.nordicsemi.com/topic/ps_nrf52833/temp.html?cp=4_1_0_5_25
|
||||
*
|
||||
* A very simple and rough model
|
||||
*
|
||||
* Notes:
|
||||
* * At this point the device is always at 25 C
|
||||
* * The measurement result will just be 25 +- 0.25 C
|
||||
* * There is no per device variability
|
||||
* * There is no modeling of possible calibration errors or inaccuracies due to no non-linearities compensation
|
||||
*/
|
||||
|
||||
#include "NHW_common_types.h"
|
||||
#include "NHW_config.h"
|
||||
#include "NRF_TEMP.h"
|
||||
#include <string.h>
|
||||
#include <stdbool.h>
|
||||
#include "nsi_hw_scheduler.h"
|
||||
#include "NHW_peri_types.h"
|
||||
#include "NRF_PPI.h"
|
||||
#include "irq_ctrl.h"
|
||||
#include "bs_rand_main.h"
|
||||
#include "nsi_tasks.h"
|
||||
#include "nsi_hws_models_if.h"
|
||||
|
||||
NRF_TEMP_Type NRF_TEMP_regs;
|
||||
/* Mapping of peripheral instance to {int controller instance, int number} */
|
||||
static struct nhw_irq_mapping nhw_temp_irq_map[NHW_TEMP_TOTAL_INST] = NHW_TEMP_INT_MAP;
|
||||
|
||||
static bs_time_t Timer_TEMP = TIME_NEVER; //Time when the next temperature measurement will be ready
|
||||
|
||||
static bool TEMP_hw_started = false;
|
||||
static bool TEMP_INTEN = false; //interrupt enable
|
||||
#define T_TEMP 36 /* microseconds */
|
||||
#define TEMP_FBITS 2 /* fractional bits */
|
||||
|
||||
static double temperature = 25.0; /* Actual temperature the device is at */
|
||||
|
||||
/**
|
||||
* Initialize the TEMP model
|
||||
*/
|
||||
static void nrf_temp_init(void) {
|
||||
memset(&NRF_TEMP_regs, 0, sizeof(NRF_TEMP_regs));
|
||||
NRF_TEMP_regs.A0 = 0x00000326;
|
||||
NRF_TEMP_regs.A1 = 0x00000348;
|
||||
NRF_TEMP_regs.A2 = 0x000003AA;
|
||||
NRF_TEMP_regs.A3 = 0x0000040E;
|
||||
NRF_TEMP_regs.A4 = 0x000004BD;
|
||||
NRF_TEMP_regs.A5 = 0x000005A3;
|
||||
NRF_TEMP_regs.B0 = 0x00003FEF;
|
||||
NRF_TEMP_regs.B1 = 0x00003FBE;
|
||||
NRF_TEMP_regs.B2 = 0x00003FBE;
|
||||
NRF_TEMP_regs.B3 = 0x00000012;
|
||||
NRF_TEMP_regs.B4 = 0x00000124;
|
||||
NRF_TEMP_regs.B5 = 0x0000027C;
|
||||
NRF_TEMP_regs.T0 = 0x000000E2;
|
||||
NRF_TEMP_regs.T1 = 0x00000000;
|
||||
NRF_TEMP_regs.T2 = 0x00000019;
|
||||
NRF_TEMP_regs.T3 = 0x0000003C;
|
||||
NRF_TEMP_regs.T4 = 0x00000050;
|
||||
|
||||
TEMP_hw_started = false;
|
||||
TEMP_INTEN = false;
|
||||
Timer_TEMP = TIME_NEVER;
|
||||
}
|
||||
|
||||
NSI_TASK(nrf_temp_init, HW_INIT, 100);
|
||||
|
||||
/**
|
||||
* TASK_START triggered handler
|
||||
*/
|
||||
void nrf_temp_task_start(void) {
|
||||
if (TEMP_hw_started) {
|
||||
return;
|
||||
}
|
||||
TEMP_hw_started = true;
|
||||
Timer_TEMP = nsi_hws_get_time() + T_TEMP;
|
||||
nsi_hws_find_next_event();
|
||||
}
|
||||
|
||||
/**
|
||||
* TASK_STOP triggered handler
|
||||
*/
|
||||
void nrf_temp_task_stop(void) {
|
||||
TEMP_hw_started = false;
|
||||
Timer_TEMP = TIME_NEVER;
|
||||
nsi_hws_find_next_event();
|
||||
}
|
||||
|
||||
void nrf_temp_regw_sideeffects_TASK_START(void) {
|
||||
|
||||
NRF_TEMP_regs.TASKS_START &= 1;
|
||||
|
||||
if ( NRF_TEMP_regs.TASKS_START ) {
|
||||
NRF_TEMP_regs.TASKS_START = 0;
|
||||
nrf_temp_task_start();
|
||||
}
|
||||
}
|
||||
|
||||
void nrf_temp_regw_sideeffects_TASK_STOP(void) {
|
||||
|
||||
NRF_TEMP_regs.TASKS_STOP &= 1;
|
||||
|
||||
if ( NRF_TEMP_regs.TASKS_STOP ) {
|
||||
NRF_TEMP_regs.TASKS_STOP = 0;
|
||||
nrf_temp_task_stop();
|
||||
}
|
||||
}
|
||||
|
||||
void nrf_temp_regw_sideeffects_INTENSET(void) {
|
||||
|
||||
NRF_TEMP_regs.INTENSET &= 1;
|
||||
|
||||
if ( NRF_TEMP_regs.INTENSET ) {
|
||||
TEMP_INTEN = true;
|
||||
}
|
||||
}
|
||||
|
||||
void nrf_temp_regw_sideeffects_INTENCLEAR(void) {
|
||||
|
||||
NRF_TEMP_regs.INTENCLR &= 1;
|
||||
|
||||
if ( NRF_TEMP_regs.INTENCLR ) {
|
||||
TEMP_INTEN = false;
|
||||
NRF_TEMP_regs.INTENSET = 0;
|
||||
NRF_TEMP_regs.INTENCLR = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Time has come when the temperature measurement is ready
|
||||
*/
|
||||
static void nrf_temp_timer_triggered(void) {
|
||||
|
||||
NRF_TEMP_regs.TEMP = temperature*(1 << TEMP_FBITS) + bs_random_uniformRi(-1,1);
|
||||
|
||||
TEMP_hw_started = false;
|
||||
Timer_TEMP = TIME_NEVER;
|
||||
nsi_hws_find_next_event();
|
||||
|
||||
NRF_TEMP_regs.EVENTS_DATARDY = 1;
|
||||
nrf_ppi_event(TEMP_EVENTS_DATARDY);
|
||||
|
||||
int inst = 0;
|
||||
if ( TEMP_INTEN ){
|
||||
hw_irq_ctrl_set_irq(nhw_temp_irq_map[inst].cntl_inst,
|
||||
nhw_temp_irq_map[inst].int_nbr);
|
||||
}
|
||||
}
|
||||
|
||||
NSI_HW_EVENT(Timer_TEMP, nrf_temp_timer_triggered, 50);
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef _NRF_HW_MODEL_TEMP_H
|
||||
#define _NRF_HW_MODEL_TEMP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"{
|
||||
#endif
|
||||
|
||||
void nrf_temp_regw_sideeffects_TASK_START(void);
|
||||
void nrf_temp_regw_sideeffects_TASK_STOP(void);
|
||||
void nrf_temp_regw_sideeffects_INTENSET(void);
|
||||
void nrf_temp_regw_sideeffects_INTENCLEAR(void);
|
||||
void nrf_temp_task_start(void);
|
||||
void nrf_temp_task_stop(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -7,18 +7,16 @@
|
|||
*/
|
||||
#include "hal/nrf_temp.h"
|
||||
#include "bs_tracing.h"
|
||||
#include "NRF_TEMP.h"
|
||||
#include "NHW_TEMP.h"
|
||||
|
||||
void nrf_temp_task_trigger(NRF_TEMP_Type * p_reg, nrf_temp_task_t temp_task)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)temp_task)) = 0x1UL;
|
||||
|
||||
if ( temp_task == NRF_TEMP_TASK_START ) {
|
||||
NRF_TEMP_regs.TASKS_START = 1;
|
||||
nrf_temp_regw_sideeffects_TASK_START();
|
||||
nhw_TEMP_regw_sideeffects_TASKS_START();
|
||||
} else if ( temp_task == NRF_TEMP_TASK_STOP ) {
|
||||
NRF_TEMP_regs.TASKS_STOP = 1;
|
||||
nrf_temp_regw_sideeffects_TASK_STOP();
|
||||
nhw_TEMP_regw_sideeffects_TASKS_STOP();
|
||||
} else {
|
||||
bs_trace_error_line_time("Not supported task started in %s\n", __func__);
|
||||
}
|
||||
|
|
@ -27,11 +25,50 @@ void nrf_temp_task_trigger(NRF_TEMP_Type * p_reg, nrf_temp_task_t temp_task)
|
|||
void nrf_temp_int_enable(NRF_TEMP_Type * p_reg, uint32_t mask)
|
||||
{
|
||||
NRF_TEMP_regs.INTENSET = mask;
|
||||
nrf_temp_regw_sideeffects_INTENSET();
|
||||
nhw_TEMP_regw_sideeffects_INTENSET();
|
||||
}
|
||||
|
||||
void nrf_temp_int_disable(NRF_TEMP_Type * p_reg, uint32_t mask)
|
||||
{
|
||||
NRF_TEMP_regs.INTENCLR = mask;
|
||||
nrf_temp_regw_sideeffects_INTENCLEAR();
|
||||
nhw_TEMP_regw_sideeffects_INTENCLEAR();
|
||||
}
|
||||
|
||||
void nrf_temp_event_clear(NRF_TEMP_Type * p_reg, nrf_temp_event_t event)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
|
||||
nhw_TEMP_regw_sideeffects_EVENTS_all(0);
|
||||
}
|
||||
|
||||
#if defined(DPPI_PRESENT)
|
||||
|
||||
static void nrf_temp_subscribe_common(NRF_TEMP_Type * p_reg,
|
||||
nrf_temp_task_t task)
|
||||
{
|
||||
if (task == NRF_TEMP_TASK_START) {
|
||||
nhw_TEMP_regw_sideeffects_SUBSCRIBE_START(0);
|
||||
} else if ( task == NRF_TEMP_TASK_STOP ) {
|
||||
nhw_TEMP_regw_sideeffects_SUBSCRIBE_STOP(0);
|
||||
} else {
|
||||
bs_trace_error_line_time("Attempted to subscribe to an not-supported task in the nrf_temp (%i)\n",
|
||||
task);
|
||||
}
|
||||
}
|
||||
|
||||
void nrf_temp_subscribe_set(NRF_TEMP_Type * p_reg,
|
||||
nrf_temp_task_t task,
|
||||
uint8_t channel)
|
||||
{
|
||||
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
|
||||
((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
|
||||
nrf_temp_subscribe_common(p_reg, task);
|
||||
}
|
||||
|
||||
void nrf_temp_subscribe_clear(NRF_TEMP_Type * p_reg,
|
||||
nrf_temp_task_t task)
|
||||
{
|
||||
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
|
||||
nrf_temp_subscribe_common(p_reg, task);
|
||||
}
|
||||
|
||||
#endif /* defined(DPPI_PRESENT) */
|
||||
|
|
|
|||
|
|
@ -143,8 +143,9 @@ extern NRF_CCM_Type NRF_CCM_regs;
|
|||
extern NRF_DPPIC_Type NRF_DPPIC_regs[];
|
||||
#undef NRF_DPPIC_NS_BASE
|
||||
#define NRF_DPPIC_NS_BASE (&NRF_DPPIC_regs[NHW_DPPI_NET_0])
|
||||
extern NRF_TEMP_Type NRF_TEMP_regs;
|
||||
#undef NRF_TEMP_NS_BASE
|
||||
#define NRF_TEMP_NS_BASE NULL
|
||||
#define NRF_TEMP_NS_BASE (&NRF_TEMP_regs)
|
||||
extern NRF_RTC_Type NRF_RTC_regs[];
|
||||
#undef NRF_RTC0_NS_BASE
|
||||
#define NRF_RTC0_NS_BASE (&NRF_RTC_regs[NHW_RTC_NET0])
|
||||
|
|
|
|||
Loading…
Reference in New Issue