AES_CCM: Switched to level interrupts, readied for nrf53
* Switched to level interrupts * Added DPPI connections * Added nrf53 glue and config * HAL: Added event and subscription overrides * Used code templates for common logic Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This commit is contained in:
Alberto Escolar Piedras
parent
eaa89dab76
commit
6ef00694e4
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@ -10,6 +10,7 @@ src/HW_models/NRF_RADIO_utils.c
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src/HW_models/trivial_xo.c
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src/HW_models/fake_timer.c
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src/HW_models/NRF_RADIO.c
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src/HW_models/NHW_AES_CCM.c
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src/HW_models/NHW_AES_ECB.c
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src/HW_models/crc.c
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src/HW_models/irq_ctrl.c
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@ -18,7 +19,6 @@ src/HW_models/bstest_ticker.c
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src/HW_models/NRF_NVMC.c
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src/HW_models/NRF_GPIO.c
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src/HW_models/NRF_TEMP.c
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src/HW_models/NRF_AES_CCM.c
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src/HW_models/NRF_RADIO_tasks_regs.c
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src/HW_models/NHW_TIMER.c
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src/HW_models/bs_compat.c
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@ -7,6 +7,7 @@ src/HW_models/irq_ctrl.c
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src/HW_models/bstest_ticker.c
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src/HW_models/bs_compat.c
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src/HW_models/NHW_AAR.c
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src/HW_models/NHW_AES_CCM.c
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src/HW_models/NHW_AES_ECB.c
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src/HW_models/NHW_DPPI.c
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src/HW_models/NHW_CLOCK.c
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@ -1,5 +1,6 @@
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src/nrfx/drivers/nrfx_common.c
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src/nrfx/hal/nrf_aar.c
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src/nrfx/hal/nrf_ccm.c
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src/nrfx/hal/nrf_clock.c
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src/nrfx/hal/nrf_dppi.c
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src/nrfx/hal/nrf_ecb.c
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@ -8,6 +8,7 @@
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/*
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* CCM - AES CCM mode encryption
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* https://infocenter.nordicsemi.com/topic/ps_nrf52833/ccm.html?cp=5_1_0_5_3
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* https://infocenter.nordicsemi.com/topic/ps_nrf5340/ccm.html?cp=4_0_0_6_4
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*
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* Notes:
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*
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@ -29,30 +30,33 @@
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*
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* 3. TASKS_STOP is not really supported
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*
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* 4. TASK_RATEOVERRIDE and RATEOVERRIDE are not supported
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* 4. TASK_RATEOVERRIDE and RATEOVERRIDE are not supported (just ignored)
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*/
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#include "NHW_common_types.h"
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#include "NHW_config.h"
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#include "NRF_AES_CCM.h"
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#include "NHW_templates.h"
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#include "NHW_AES_CCM.h"
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#include <string.h>
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#include <stdbool.h>
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#include "nsi_hw_scheduler.h"
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#include "NHW_peri_types.h"
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#include "NRF_PPI.h"
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#include "NHW_xPPI.h"
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#include "irq_ctrl.h"
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#include "bs_tracing.h"
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#include "BLECrypt_if.h"
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#include "nsi_tasks.h"
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NRF_CCM_Type NRF_CCM_regs;
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/* Mapping of peripheral instance to {int controller instance, int number} */
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static struct nhw_irq_mapping nhw_ccm_irq_map[NHW_CCM_TOTAL_INST] = NHW_CCM_INT_MAP;
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#if (NHW_HAS_DPPI)
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/* Mapping of peripheral instance to DPPI instance */
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static uint nhw_CCM_dppi_map[NHW_CCM_TOTAL_INST] = NHW_CCM_DPPI_MAP;
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#endif
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static uint32_t CCM_INTEN; //interrupt enable
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static bool decryption_ongoing;
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static void nrf_aes_ccm_init(void) {
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static void nhw_aes_ccm_init(void) {
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memset(&NRF_CCM_regs, 0, sizeof(NRF_CCM_regs));
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NRF_CCM_regs.MODE = 0x01;
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NRF_CCM_regs.HEADERMASK= 0xE3;
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@ -61,10 +65,34 @@ static void nrf_aes_ccm_init(void) {
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decryption_ongoing = false;
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}
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NSI_TASK(nrf_aes_ccm_init, HW_INIT, 100);
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NSI_TASK(nhw_aes_ccm_init, HW_INIT, 100);
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void nrf_ccm_TASK_CRYPT(void);
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static void signal_EVENTS_ENDCRYPT(void);
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static void nhw_CCM_eval_interrupt(uint inst) {
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static bool ccm_int_line[NHW_CCM_TOTAL_INST]; /* Is the CCM currently driving its interrupt line high */
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/* Mapping of peripheral instance to {int controller instance, int number} */
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static struct nhw_irq_mapping nhw_ccm_irq_map[NHW_CCM_TOTAL_INST] = NHW_CCM_INT_MAP;
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bool new_int_line = false;
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NHW_CHECK_INTERRUPT_si(CCM, ENDKSGEN, CCM_INTEN)
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NHW_CHECK_INTERRUPT_si(CCM, ENDCRYPT, CCM_INTEN)
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NHW_CHECK_INTERRUPT_si(CCM, ERROR, CCM_INTEN)
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hw_irq_ctrl_toggle_level_irq_line_if(&ccm_int_line[inst],
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new_int_line,
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&nhw_ccm_irq_map[inst]);
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}
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NHW_SIGNAL_EVENT_si(CCM, ENDKSGEN)
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NHW_SIGNAL_EVENT_si(CCM, ENDCRYPT)
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//Unused so far in this model: NHW_SIGNAL_EVENT_si(CCM, ERROR)
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static void signal_EVENTS_ENDKSGEN(void) {
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nhw_CCM_signal_EVENTS_ENDKSGEN(0);
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if (NRF_CCM_regs.SHORTS & CCM_SHORTS_ENDKSGEN_CRYPT_Msk) {
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nhw_CCM_TASK_CRYPT();
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}
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}
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#define IV_LEN 8
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#define NONCE_LEN 13
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@ -91,7 +119,6 @@ static void nonce_calc(
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memcpy(&ccm_nonce[NONCE_LEN - IV_LEN], iv, IV_LEN);
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}
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static void nrf_ccm_encrypt_tx(void) {
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const uint8_t* cnfptr;
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const uint8_t* sk;
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@ -134,7 +161,7 @@ static void nrf_ccm_encrypt_tx(void) {
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ccm_nonce
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);
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signal_EVENTS_ENDCRYPT();
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nhw_CCM_signal_EVENTS_ENDCRYPT(0);
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}
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static void nrf_ccm_decrypt_rx(bool crc_error) {
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@ -152,7 +179,7 @@ static void nrf_ccm_decrypt_rx(bool crc_error) {
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if (crc_error) {
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NRF_CCM_regs.MICSTATUS = 0;
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signal_EVENTS_ENDCRYPT();
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nhw_CCM_signal_EVENTS_ENDCRYPT(0);
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return;
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}
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@ -189,45 +216,10 @@ static void nrf_ccm_decrypt_rx(bool crc_error) {
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NRF_CCM_regs.MICSTATUS = !mic_error;
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signal_EVENTS_ENDCRYPT();
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nhw_CCM_signal_EVENTS_ENDCRYPT(0);
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}
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static void signal_EVENTS_ENDKSGEN(void) {
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NRF_CCM_regs.EVENTS_ENDKSGEN = 1;
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nrf_ppi_event(CCM_EVENTS_ENDKSGEN);
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int inst = 0;
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if (CCM_INTEN & CCM_INTENSET_ENDKSGEN_Msk) {
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hw_irq_ctrl_set_irq(nhw_ccm_irq_map[inst].cntl_inst,
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nhw_ccm_irq_map[inst].int_nbr);
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}
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if (NRF_CCM_regs.SHORTS & CCM_SHORTS_ENDKSGEN_CRYPT_Msk) {
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nrf_ccm_TASK_CRYPT();
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}
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}
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static void signal_EVENTS_ENDCRYPT(void) {
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NRF_CCM_regs.EVENTS_ENDCRYPT = 1;
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nrf_ppi_event(CCM_EVENTS_ENDCRYPT);
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int inst = 0;
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if (CCM_INTEN & CCM_INTENSET_ENDCRYPT_Msk) {
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hw_irq_ctrl_set_irq(nhw_ccm_irq_map[inst].cntl_inst,
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nhw_ccm_irq_map[inst].int_nbr);
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}
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}
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/* static void signal_EVENTS_ERROR(){
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NRF_CCM_regs.EVENTS_ERROR = 1;
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NRF_PPI_Event(CCM_EVENTS_ERROR);
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if (CCM_INTEN & CCM_INTENSET_ERROR_Msk) {
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hw_irq_ctrl_set_irq(NRF5_IRQ_CCM_AAR_IRQn);
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}
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} */
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void nrf_ccm_TASK_KSGEN(void) {
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void nhw_CCM_TASK_KSGEN(void) {
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if (NRF_CCM_regs.ENABLE != CCM_ENABLE_ENABLE_Enabled) {
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return;
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}
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@ -235,7 +227,7 @@ void nrf_ccm_TASK_KSGEN(void) {
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signal_EVENTS_ENDKSGEN();
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}
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void nrf_ccm_TASK_CRYPT(void) {
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void nhw_CCM_TASK_CRYPT(void) {
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if (NRF_CCM_regs.ENABLE != CCM_ENABLE_ENABLE_Enabled) {
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return;
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}
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@ -248,54 +240,34 @@ void nrf_ccm_TASK_CRYPT(void) {
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}
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}
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void nrf_ccm_TASK_STOP(void) {
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void nhw_CCM_TASK_STOP(void) {
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bs_trace_warning_line_time("CCM: TASK_STOP functionality is not implemented\n");
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decryption_ongoing = false;
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}
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void nrf_ccm_TASK_RATEOVERRIDE(void) {
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void nhw_CCM_TASK_RATEOVERRIDE(void) {
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/* We ignore the RATEOVERRIDE task */
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bs_trace_warning_line_time("%s ignored\n", __func__);
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}
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NHW_SIDEEFFECTS_INTSET_si(CCM, NRF_CCM_regs., CCM_INTEN)
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NHW_SIDEEFFECTS_INTCLR_si(CCM, NRF_CCM_regs., CCM_INTEN)
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void nrf_ccm_regw_sideeffects_INTENSET(void) {
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if (NRF_CCM_regs.INTENSET) {
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CCM_INTEN |= NRF_CCM_regs.INTENSET;
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NRF_CCM_regs.INTENSET = CCM_INTEN;
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}
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}
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NHW_SIDEEFFECTS_EVENTS(CCM)
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void nrf_ccm_regw_sideeffects_INTENCLR(void) {
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if (NRF_CCM_regs.INTENCLR) {
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CCM_INTEN &= ~NRF_CCM_regs.INTENCLR;
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NRF_CCM_regs.INTENSET = CCM_INTEN;
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NRF_CCM_regs.INTENCLR = 0;
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}
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}
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NHW_SIDEEFFECTS_TASKS_si(CCM, KSGEN)
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NHW_SIDEEFFECTS_TASKS_si(CCM, CRYPT)
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NHW_SIDEEFFECTS_TASKS_si(CCM, STOP)
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NHW_SIDEEFFECTS_TASKS_si(CCM, RATEOVERRIDE)
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void nrf_ccm_regw_sideeffects_TASKS_KSGEN(void) {
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if (NRF_CCM_regs.TASKS_KSGEN) {
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NRF_CCM_regs.TASKS_KSGEN = 0;
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nrf_ccm_TASK_KSGEN();
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}
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}
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#if (NHW_HAS_DPPI)
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NHW_SIDEEFFECTS_SUBSCRIBE_si(CCM, KSGEN)
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NHW_SIDEEFFECTS_SUBSCRIBE_si(CCM, CRYPT)
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NHW_SIDEEFFECTS_SUBSCRIBE_si(CCM, STOP)
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NHW_SIDEEFFECTS_SUBSCRIBE_si(CCM, RATEOVERRIDE)
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#endif /* NHW_HAS_DPPI */
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void nrf_ccm_regw_sideeffects_TASKS_CRYPT(void) {
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if (NRF_CCM_regs.TASKS_CRYPT) {
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NRF_CCM_regs.TASKS_CRYPT = 0;
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nrf_ccm_TASK_CRYPT();
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}
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}
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void nrf_ccm_regw_sideeffects_TASKS_STOP(void) {
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if (NRF_CCM_regs.TASKS_STOP) {
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NRF_CCM_regs.TASKS_STOP = 0;
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nrf_ccm_TASK_STOP();
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bs_trace_warning_line_time("CCM: TASK_STOP functionality is not implemented\n");
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}
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}
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void nrf_ccm_radio_received_packet(bool crc_error) {
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void nhw_ccm_radio_received_packet(bool crc_error) {
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if (!decryption_ongoing) {
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return;
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}
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@ -0,0 +1,35 @@
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/*
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* Copyright (c) 2017 Oticon A/S
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* Copyright (c) 2023 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _NRF_HW_MODEL_NHW_AES_CCM_H
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#define _NRF_HW_MODEL_NHW_AES_CCM_H
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#include <stdbool.h>
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#ifdef __cplusplus
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extern "C"{
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#endif
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void nhw_CCM_TASK_KSGEN(void);
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void nhw_CCM_TASK_CRYPT(void);
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void nhw_CCM_TASK_STOP(void);
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void nhw_CCM_TASK_RATEOVERRIDE(void);
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void nhw_ccm_radio_received_packet(bool crc_error);
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void nhw_CCM_regw_sideeffects_INTENSET(void);
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void nhw_CCM_regw_sideeffects_INTENCLR(void);
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void nhw_CCM_regw_sideeffects_TASKS_KSGEN(void);
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void nhw_CCM_regw_sideeffects_TASKS_CRYPT(void);
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void nhw_CCM_regw_sideeffects_TASKS_STOP(void);
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void nhw_CCM_regw_sideeffects_EVENTS_all(unsigned int inst);
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void nhw_CCM_regw_sideeffects_SUBSCRIBE_KSGEN(unsigned int inst);
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void nhw_CCM_regw_sideeffects_SUBSCRIBE_CRYPT(unsigned int inst);
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void nhw_CCM_regw_sideeffects_SUBSCRIBE_STOP(unsigned int inst);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _NRF_HW_MODEL_NHW_AES_CCM_H */
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@ -186,6 +186,11 @@
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#define NHW_AAR_DPPI_MAP {1}
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#define NHW_AAR_t_AAR 6
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#define NHW_CCM_TOTAL_INST 1
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#define NHW_CCM_NET0 0
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#define NHW_CCM_INT_MAP {{1 , 14}} /*Net core,AAR_CCM*/
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#define NHW_CCM_DPPI_MAP {1}
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#define NHW_CLKPWR_TOTAL_INST 2
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#define NHW_CLKPWR_APP0 0
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#define NHW_CLKPWR_NET0 1
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@ -340,6 +340,367 @@ typedef struct { /*!< (@ 0x4100E000) AAR_NS Struc
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/* =========================================================================================================================== */
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/* ================ CCM ================ */
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/* =========================================================================================================================== */
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/**
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* @brief AES CCM mode encryption (CCM)
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*/
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typedef struct { /*!< (@ 0x4100E000) CCM_NS Structure */
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__OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of keystream. This operation
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will stop by itself when completed. */
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__OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will
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stop by itself when completed. */
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__OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */
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__OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with
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the contents of the RATEOVERRIDE register
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for any ongoing encryption/decryption */
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__IM uint32_t RESERVED[28];
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__IOM uint32_t SUBSCRIBE_KSGEN; /*!< (@ 0x00000080) Subscribe configuration for task KSGEN */
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__IOM uint32_t SUBSCRIBE_CRYPT; /*!< (@ 0x00000084) Subscribe configuration for task CRYPT */
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__IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000088) Subscribe configuration for task STOP */
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__IOM uint32_t SUBSCRIBE_RATEOVERRIDE; /*!< (@ 0x0000008C) Subscribe configuration for task RATEOVERRIDE */
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__IM uint32_t RESERVED1[28];
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__IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Keystream generation complete */
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__IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */
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__IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */
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__IM uint32_t RESERVED2[29];
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__IOM uint32_t PUBLISH_ENDKSGEN; /*!< (@ 0x00000180) Publish configuration for event ENDKSGEN */
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__IOM uint32_t PUBLISH_ENDCRYPT; /*!< (@ 0x00000184) Publish configuration for event ENDCRYPT */
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__IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x00000188) Deprecated register - Publish configuration for
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event ERROR */
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__IM uint32_t RESERVED3[29];
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__IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
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__IM uint32_t RESERVED4[64];
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__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
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__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
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__IM uint32_t RESERVED5[61];
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__IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */
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__IM uint32_t RESERVED6[63];
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__IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */
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__IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */
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__IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding the AES key
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and the NONCE vector */
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__IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */
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__IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */
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__IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */
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__IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of keystream generated when MODE.LENGTH
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= Extended */
|
||||
__IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */
|
||||
__IOM uint32_t HEADERMASK; /*!< (@ 0x00000520) Header (S0) mask. */
|
||||
} NRF_CCM_Type; /*!< Size = 1316 (0x524) */
|
||||
|
||||
|
||||
/* Peripheral: CCM */
|
||||
/* Description: AES CCM mode encryption */
|
||||
|
||||
/* Register: CCM_TASKS_KSGEN */
|
||||
/* Description: Start generation of keystream. This operation will stop by itself when completed. */
|
||||
|
||||
/* Bit 0 : Start generation of keystream. This operation will stop by itself when completed. */
|
||||
#define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */
|
||||
#define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */
|
||||
#define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL) /*!< Trigger task */
|
||||
|
||||
/* Register: CCM_TASKS_CRYPT */
|
||||
/* Description: Start encryption/decryption. This operation will stop by itself when completed. */
|
||||
|
||||
/* Bit 0 : Start encryption/decryption. This operation will stop by itself when completed. */
|
||||
#define CCM_TASKS_CRYPT_TASKS_CRYPT_Pos (0UL) /*!< Position of TASKS_CRYPT field. */
|
||||
#define CCM_TASKS_CRYPT_TASKS_CRYPT_Msk (0x1UL << CCM_TASKS_CRYPT_TASKS_CRYPT_Pos) /*!< Bit mask of TASKS_CRYPT field. */
|
||||
#define CCM_TASKS_CRYPT_TASKS_CRYPT_Trigger (1UL) /*!< Trigger task */
|
||||
|
||||
/* Register: CCM_TASKS_STOP */
|
||||
/* Description: Stop encryption/decryption */
|
||||
|
||||
/* Bit 0 : Stop encryption/decryption */
|
||||
#define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
|
||||
#define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
|
||||
#define CCM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
|
||||
|
||||
/* Register: CCM_TASKS_RATEOVERRIDE */
|
||||
/* Description: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */
|
||||
|
||||
/* Bit 0 : Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */
|
||||
#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL) /*!< Position of TASKS_RATEOVERRIDE field. */
|
||||
#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos) /*!< Bit mask of TASKS_RATEOVERRIDE field. */
|
||||
#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (1UL) /*!< Trigger task */
|
||||
|
||||
/* Register: CCM_SUBSCRIBE_KSGEN */
|
||||
/* Description: Subscribe configuration for task KSGEN */
|
||||
|
||||
/* Bit 31 : */
|
||||
#define CCM_SUBSCRIBE_KSGEN_EN_Pos (31UL) /*!< Position of EN field. */
|
||||
#define CCM_SUBSCRIBE_KSGEN_EN_Msk (0x1UL << CCM_SUBSCRIBE_KSGEN_EN_Pos) /*!< Bit mask of EN field. */
|
||||
#define CCM_SUBSCRIBE_KSGEN_EN_Disabled (0UL) /*!< Disable subscription */
|
||||
#define CCM_SUBSCRIBE_KSGEN_EN_Enabled (1UL) /*!< Enable subscription */
|
||||
|
||||
/* Bits 7..0 : DPPI channel that task KSGEN will subscribe to */
|
||||
#define CCM_SUBSCRIBE_KSGEN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
|
||||
#define CCM_SUBSCRIBE_KSGEN_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_KSGEN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
|
||||
|
||||
/* Register: CCM_SUBSCRIBE_CRYPT */
|
||||
/* Description: Subscribe configuration for task CRYPT */
|
||||
|
||||
/* Bit 31 : */
|
||||
#define CCM_SUBSCRIBE_CRYPT_EN_Pos (31UL) /*!< Position of EN field. */
|
||||
#define CCM_SUBSCRIBE_CRYPT_EN_Msk (0x1UL << CCM_SUBSCRIBE_CRYPT_EN_Pos) /*!< Bit mask of EN field. */
|
||||
#define CCM_SUBSCRIBE_CRYPT_EN_Disabled (0UL) /*!< Disable subscription */
|
||||
#define CCM_SUBSCRIBE_CRYPT_EN_Enabled (1UL) /*!< Enable subscription */
|
||||
|
||||
/* Bits 7..0 : DPPI channel that task CRYPT will subscribe to */
|
||||
#define CCM_SUBSCRIBE_CRYPT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
|
||||
#define CCM_SUBSCRIBE_CRYPT_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_CRYPT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
|
||||
|
||||
/* Register: CCM_SUBSCRIBE_STOP */
|
||||
/* Description: Subscribe configuration for task STOP */
|
||||
|
||||
/* Bit 31 : */
|
||||
#define CCM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
|
||||
#define CCM_SUBSCRIBE_STOP_EN_Msk (0x1UL << CCM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
|
||||
#define CCM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
|
||||
#define CCM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
|
||||
|
||||
/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
|
||||
#define CCM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
|
||||
#define CCM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
|
||||
|
||||
/* Register: CCM_SUBSCRIBE_RATEOVERRIDE */
|
||||
/* Description: Subscribe configuration for task RATEOVERRIDE */
|
||||
|
||||
/* Bit 31 : */
|
||||
#define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Pos (31UL) /*!< Position of EN field. */
|
||||
#define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Msk (0x1UL << CCM_SUBSCRIBE_RATEOVERRIDE_EN_Pos) /*!< Bit mask of EN field. */
|
||||
#define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Disabled (0UL) /*!< Disable subscription */
|
||||
#define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Enabled (1UL) /*!< Enable subscription */
|
||||
|
||||
/* Bits 7..0 : DPPI channel that task RATEOVERRIDE will subscribe to */
|
||||
#define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
|
||||
#define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
|
||||
|
||||
/* Register: CCM_EVENTS_ENDKSGEN */
|
||||
/* Description: Keystream generation complete */
|
||||
|
||||
/* Bit 0 : Keystream generation complete */
|
||||
#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */
|
||||
#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */
|
||||
#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL) /*!< Event not generated */
|
||||
#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Generated (1UL) /*!< Event generated */
|
||||
|
||||
/* Register: CCM_EVENTS_ENDCRYPT */
|
||||
/* Description: Encrypt/decrypt complete */
|
||||
|
||||
/* Bit 0 : Encrypt/decrypt complete */
|
||||
#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos (0UL) /*!< Position of EVENTS_ENDCRYPT field. */
|
||||
#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Msk (0x1UL << CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos) /*!< Bit mask of EVENTS_ENDCRYPT field. */
|
||||
#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_NotGenerated (0UL) /*!< Event not generated */
|
||||
#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Generated (1UL) /*!< Event generated */
|
||||
|
||||
/* Register: CCM_EVENTS_ERROR */
|
||||
/* Description: Deprecated register - CCM error event */
|
||||
|
||||
/* Bit 0 : Deprecated field - CCM error event */
|
||||
#define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
|
||||
#define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
|
||||
#define CCM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
|
||||
#define CCM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
|
||||
|
||||
/* Register: CCM_PUBLISH_ENDKSGEN */
|
||||
/* Description: Publish configuration for event ENDKSGEN */
|
||||
|
||||
/* Bit 31 : */
|
||||
#define CCM_PUBLISH_ENDKSGEN_EN_Pos (31UL) /*!< Position of EN field. */
|
||||
#define CCM_PUBLISH_ENDKSGEN_EN_Msk (0x1UL << CCM_PUBLISH_ENDKSGEN_EN_Pos) /*!< Bit mask of EN field. */
|
||||
#define CCM_PUBLISH_ENDKSGEN_EN_Disabled (0UL) /*!< Disable publishing */
|
||||
#define CCM_PUBLISH_ENDKSGEN_EN_Enabled (1UL) /*!< Enable publishing */
|
||||
|
||||
/* Bits 7..0 : DPPI channel that event ENDKSGEN will publish to. */
|
||||
#define CCM_PUBLISH_ENDKSGEN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
|
||||
#define CCM_PUBLISH_ENDKSGEN_CHIDX_Msk (0xFFUL << CCM_PUBLISH_ENDKSGEN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
|
||||
|
||||
/* Register: CCM_PUBLISH_ENDCRYPT */
|
||||
/* Description: Publish configuration for event ENDCRYPT */
|
||||
|
||||
/* Bit 31 : */
|
||||
#define CCM_PUBLISH_ENDCRYPT_EN_Pos (31UL) /*!< Position of EN field. */
|
||||
#define CCM_PUBLISH_ENDCRYPT_EN_Msk (0x1UL << CCM_PUBLISH_ENDCRYPT_EN_Pos) /*!< Bit mask of EN field. */
|
||||
#define CCM_PUBLISH_ENDCRYPT_EN_Disabled (0UL) /*!< Disable publishing */
|
||||
#define CCM_PUBLISH_ENDCRYPT_EN_Enabled (1UL) /*!< Enable publishing */
|
||||
|
||||
/* Bits 7..0 : DPPI channel that event ENDCRYPT will publish to. */
|
||||
#define CCM_PUBLISH_ENDCRYPT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
|
||||
#define CCM_PUBLISH_ENDCRYPT_CHIDX_Msk (0xFFUL << CCM_PUBLISH_ENDCRYPT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
|
||||
|
||||
/* Register: CCM_PUBLISH_ERROR */
|
||||
/* Description: Deprecated register - Publish configuration for event ERROR */
|
||||
|
||||
/* Bit 31 : */
|
||||
#define CCM_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */
|
||||
#define CCM_PUBLISH_ERROR_EN_Msk (0x1UL << CCM_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */
|
||||
#define CCM_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */
|
||||
#define CCM_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */
|
||||
|
||||
/* Bits 7..0 : DPPI channel that event ERROR will publish to. */
|
||||
#define CCM_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
|
||||
#define CCM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << CCM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
|
||||
|
||||
/* Register: CCM_SHORTS */
|
||||
/* Description: Shortcuts between local events and tasks */
|
||||
|
||||
/* Bit 0 : Shortcut between event ENDKSGEN and task CRYPT */
|
||||
#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
|
||||
#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
|
||||
#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
|
||||
#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
|
||||
|
||||
/* Register: CCM_INTENSET */
|
||||
/* Description: Enable interrupt */
|
||||
|
||||
/* Bit 2 : Deprecated intsetfield - Write '1' to enable interrupt for event ERROR */
|
||||
#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
|
||||
#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
|
||||
#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
|
||||
#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
|
||||
#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
|
||||
|
||||
/* Bit 1 : Write '1' to enable interrupt for event ENDCRYPT */
|
||||
#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
|
||||
#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
|
||||
#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
|
||||
#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
|
||||
#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
|
||||
|
||||
/* Bit 0 : Write '1' to enable interrupt for event ENDKSGEN */
|
||||
#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
|
||||
#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
|
||||
#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
|
||||
#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
|
||||
#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
|
||||
|
||||
/* Register: CCM_INTENCLR */
|
||||
/* Description: Disable interrupt */
|
||||
|
||||
/* Bit 2 : Deprecated intclrfield - Write '1' to disable interrupt for event ERROR */
|
||||
#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
|
||||
#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
|
||||
#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
|
||||
#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
|
||||
#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
|
||||
|
||||
/* Bit 1 : Write '1' to disable interrupt for event ENDCRYPT */
|
||||
#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
|
||||
#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
|
||||
#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
|
||||
#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
|
||||
#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
|
||||
|
||||
/* Bit 0 : Write '1' to disable interrupt for event ENDKSGEN */
|
||||
#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
|
||||
#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
|
||||
#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
|
||||
#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
|
||||
#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
|
||||
|
||||
/* Register: CCM_MICSTATUS */
|
||||
/* Description: MIC check result */
|
||||
|
||||
/* Bit 0 : The result of the MIC check performed during the previous decryption operation */
|
||||
#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
|
||||
#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
|
||||
#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */
|
||||
#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */
|
||||
|
||||
/* Register: CCM_ENABLE */
|
||||
/* Description: Enable */
|
||||
|
||||
/* Bits 1..0 : Enable or disable CCM */
|
||||
#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
|
||||
#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
|
||||
#define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
|
||||
#define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
|
||||
|
||||
/* Register: CCM_MODE */
|
||||
/* Description: Operation mode */
|
||||
|
||||
/* Bit 24 : Packet length configuration */
|
||||
#define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */
|
||||
#define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
|
||||
#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. */
|
||||
#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. */
|
||||
|
||||
/* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */
|
||||
#define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */
|
||||
#define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */
|
||||
#define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */
|
||||
#define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */
|
||||
#define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 kbps */
|
||||
#define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 kbps */
|
||||
|
||||
/* Bit 0 : The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered. */
|
||||
#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
|
||||
#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
|
||||
#define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */
|
||||
#define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */
|
||||
|
||||
/* Register: CCM_CNFPTR */
|
||||
/* Description: Pointer to data structure holding the AES key and the NONCE vector */
|
||||
|
||||
/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see table CCM data structure overview) */
|
||||
#define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */
|
||||
#define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */
|
||||
|
||||
/* Register: CCM_INPTR */
|
||||
/* Description: Input pointer */
|
||||
|
||||
/* Bits 31..0 : Input pointer */
|
||||
#define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */
|
||||
#define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */
|
||||
|
||||
/* Register: CCM_OUTPTR */
|
||||
/* Description: Output pointer */
|
||||
|
||||
/* Bits 31..0 : Output pointer */
|
||||
#define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */
|
||||
#define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */
|
||||
|
||||
/* Register: CCM_SCRATCHPTR */
|
||||
/* Description: Pointer to data area used for temporary storage */
|
||||
|
||||
/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during keystream generation,
|
||||
MIC generation and encryption/decryption. */
|
||||
#define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
|
||||
#define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
|
||||
|
||||
/* Register: CCM_MAXPACKETSIZE */
|
||||
/* Description: Length of keystream generated when MODE.LENGTH = Extended */
|
||||
|
||||
/* Bits 7..0 : Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted. */
|
||||
#define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */
|
||||
#define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */
|
||||
|
||||
/* Register: CCM_RATEOVERRIDE */
|
||||
/* Description: Data rate override setting. */
|
||||
|
||||
/* Bits 1..0 : Data rate override setting */
|
||||
#define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */
|
||||
#define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */
|
||||
#define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */
|
||||
#define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */
|
||||
#define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 kbps */
|
||||
#define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 kbps */
|
||||
|
||||
/* Register: CCM_HEADERMASK */
|
||||
/* Description: Header (S0) mask. */
|
||||
|
||||
/* Bits 7..0 : Header (S0) mask */
|
||||
#define CCM_HEADERMASK_HEADERMASK_Pos (0UL) /*!< Position of HEADERMASK field. */
|
||||
#define CCM_HEADERMASK_HEADERMASK_Msk (0xFFUL << CCM_HEADERMASK_HEADERMASK_Pos) /*!< Bit mask of HEADERMASK field. */
|
||||
|
||||
|
||||
|
||||
/* =========================================================================================================================== */
|
||||
/* ================ CLOCK ================ */
|
||||
/* =========================================================================================================================== */
|
||||
|
|
|
|||
|
|
@ -1,30 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Oticon A/S
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef _NRF_HW_MODEL_AES_CCM_H
|
||||
#define _NRF_HW_MODEL_AES_CCM_H
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"{
|
||||
#endif
|
||||
|
||||
void nrf_ccm_TASK_KSGEN(void);
|
||||
void nrf_ccm_TASK_CRYPT(void);
|
||||
void nrf_ccm_TASK_STOP(void);
|
||||
void nrf_ccm_TASK_RATEOVERRIDE(void);
|
||||
void nrf_ccm_radio_received_packet(bool crc_error);
|
||||
void nrf_ccm_regw_sideeffects_INTENSET(void);
|
||||
void nrf_ccm_regw_sideeffects_INTENCLR(void);
|
||||
void nrf_ccm_regw_sideeffects_TASKS_KSGEN(void);
|
||||
void nrf_ccm_regw_sideeffects_TASKS_CRYPT(void);
|
||||
void nrf_ccm_regw_sideeffects_TASKS_STOP(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -22,7 +22,7 @@
|
|||
#include <string.h>
|
||||
#include "NHW_peri_types.h"
|
||||
#include "NHW_AAR.h"
|
||||
#include "NRF_AES_CCM.h"
|
||||
#include "NHW_AES_CCM.h"
|
||||
#include "NRF_GPIOTE.h"
|
||||
#include "NHW_RNG.h"
|
||||
#include "NRF_PPI.h"
|
||||
|
|
@ -227,7 +227,7 @@ static const ppi_tasks_table_t ppi_tasks_table[]={ //just the ones we may use
|
|||
{ (void*)&NRF_AAR_regs.TASKS_START , nhw_AAR_TASK_START},
|
||||
|
||||
//CCM
|
||||
{ (void*)&NRF_CCM_regs.TASKS_CRYPT , nrf_ccm_TASK_CRYPT},
|
||||
{ (void*)&NRF_CCM_regs.TASKS_CRYPT , nhw_CCM_TASK_CRYPT},
|
||||
|
||||
//PPI:
|
||||
{ (void*)&NRF_PPI_regs.TASKS_CHG[0].EN, nrf_ppi_TASK_CHG0_EN},
|
||||
|
|
@ -581,11 +581,11 @@ static void set_fixed_channel_routes(void) {
|
|||
|
||||
// 24 RADIO->EVENTS_READY CCM->TASKS_KSGEN
|
||||
ppi_evt_to_ch[RADIO_EVENTS_READY].channels_mask |= ( 1 << 24 );
|
||||
ppi_ch_tasks[24].tep_f = nrf_ccm_TASK_KSGEN; //CCM->TASKS_KSGEN
|
||||
ppi_ch_tasks[24].tep_f = nhw_CCM_TASK_KSGEN; //CCM->TASKS_KSGEN
|
||||
|
||||
// 25 RADIO->EVENTS_ADDRESS CCM->TASKS_CRYPT
|
||||
ppi_evt_to_ch[RADIO_EVENTS_ADDRESS].channels_mask |= ( 1 << 25 );
|
||||
ppi_ch_tasks[25].tep_f = nrf_ccm_TASK_CRYPT; //CCM->TASKS_CRYPT
|
||||
ppi_ch_tasks[25].tep_f = nhw_CCM_TASK_CRYPT; //CCM->TASKS_CRYPT
|
||||
|
||||
// 26 RADIO->EVENTS_ADDRESS TIMER0->TASKS_CAPTURE[1]
|
||||
ppi_evt_to_ch[RADIO_EVENTS_ADDRESS].channels_mask |= ( 1 << 26 );
|
||||
|
|
|
|||
|
|
@ -151,8 +151,7 @@
|
|||
#include "NHW_peri_types.h"
|
||||
#include "NRF_RADIO.h"
|
||||
#include "nsi_hw_scheduler.h"
|
||||
#include "NRF_PPI.h"
|
||||
#include "NRF_AES_CCM.h"
|
||||
#include "NHW_AES_CCM.h"
|
||||
#include "irq_ctrl.h"
|
||||
#include "NRF_HWLowL.h"
|
||||
#include "crc.h"
|
||||
|
|
@ -812,7 +811,7 @@ static void Rx_handle_end_response(bs_time_t end_time) {
|
|||
NRF_RADIO_regs.CRCSTATUS = 1;
|
||||
}
|
||||
|
||||
nrf_ccm_radio_received_packet(!rx_status.CRC_OK);
|
||||
nhw_ccm_radio_received_packet(!rx_status.CRC_OK);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1011,7 +1010,7 @@ static void Rx_Addr_received(void) {
|
|||
|
||||
//We do what would correspond to Rx_handle_end_response() as it won't get called
|
||||
NRF_RADIO_regs.RXCRC = nrfra_get_rx_crc_value(rx_buf, rx_status.rx_resp.packet_size);
|
||||
nrf_ccm_radio_received_packet(!rx_status.CRC_OK);
|
||||
nhw_ccm_radio_received_packet(!rx_status.CRC_OK);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Oticon A/S
|
||||
* Copyright (c) 2023 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -7,19 +8,18 @@
|
|||
*/
|
||||
#include "hal/nrf_ccm.h"
|
||||
#include "bs_tracing.h"
|
||||
#include "NRF_AES_CCM.h"
|
||||
#include "NHW_AES_CCM.h"
|
||||
|
||||
void nrf_ccm_task_trigger(NRF_CCM_Type * p_reg, nrf_ccm_task_t task)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
|
||||
|
||||
if ( task == NRF_CCM_TASK_KSGEN ) {
|
||||
p_reg->TASKS_KSGEN = 1;
|
||||
nrf_ccm_regw_sideeffects_TASKS_KSGEN();
|
||||
nhw_CCM_regw_sideeffects_TASKS_KSGEN();
|
||||
} else if ( task == NRF_CCM_TASK_CRYPT ) {
|
||||
p_reg->TASKS_CRYPT = 1;
|
||||
nrf_ccm_regw_sideeffects_TASKS_CRYPT();
|
||||
nhw_CCM_regw_sideeffects_TASKS_CRYPT();
|
||||
} else if ( task == NRF_CCM_TASK_STOP ) {
|
||||
p_reg->TASKS_STOP = 1;
|
||||
nrf_ccm_regw_sideeffects_TASKS_STOP();
|
||||
nhw_CCM_regw_sideeffects_TASKS_STOP();
|
||||
} else {
|
||||
bs_trace_error_line_time("Not supported task started in nrf_ccm\n");
|
||||
}
|
||||
|
|
@ -28,12 +28,52 @@ void nrf_ccm_task_trigger(NRF_CCM_Type * p_reg, nrf_ccm_task_t task)
|
|||
void nrf_ccm_int_enable(NRF_CCM_Type * p_reg, uint32_t mask)
|
||||
{
|
||||
p_reg->INTENSET = mask;
|
||||
nrf_ccm_regw_sideeffects_INTENSET();
|
||||
nhw_CCM_regw_sideeffects_INTENSET();
|
||||
}
|
||||
|
||||
void nrf_ccm_int_disable(NRF_CCM_Type * p_reg, uint32_t mask)
|
||||
{
|
||||
p_reg->INTENCLR = mask;
|
||||
nrf_ccm_regw_sideeffects_INTENCLR();
|
||||
nhw_CCM_regw_sideeffects_INTENCLR();
|
||||
}
|
||||
|
||||
void nrf_ccm_event_clear(NRF_CCM_Type * p_reg, nrf_ccm_event_t event)
|
||||
{
|
||||
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
|
||||
nhw_CCM_regw_sideeffects_EVENTS_all(0);
|
||||
}
|
||||
|
||||
#if defined(DPPI_PRESENT)
|
||||
|
||||
static void nrf_ccm_subscribe_common(NRF_CCM_Type * p_reg,
|
||||
nrf_ccm_task_t task)
|
||||
{
|
||||
if (task == NRF_CCM_TASK_KSGEN) {
|
||||
nhw_CCM_regw_sideeffects_SUBSCRIBE_KSGEN(0);
|
||||
} else if ( task == NRF_CCM_TASK_CRYPT ) {
|
||||
nhw_CCM_regw_sideeffects_SUBSCRIBE_CRYPT(0);
|
||||
} else if ( task == NRF_CCM_TASK_STOP ) {
|
||||
nhw_CCM_regw_sideeffects_SUBSCRIBE_STOP(0);
|
||||
} else {
|
||||
bs_trace_error_line_time("Attempted to subscribe to an not-supported task in the nrf_ccm (%i)\n",
|
||||
task);
|
||||
}
|
||||
}
|
||||
|
||||
void nrf_ccm_subscribe_set(NRF_CCM_Type * p_reg,
|
||||
nrf_ccm_task_t task,
|
||||
uint8_t channel)
|
||||
{
|
||||
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
|
||||
((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
|
||||
nrf_ccm_subscribe_common(p_reg, task);
|
||||
}
|
||||
|
||||
void nrf_ccm_subscribe_clear(NRF_CCM_Type * p_reg,
|
||||
nrf_ccm_task_t task)
|
||||
{
|
||||
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
|
||||
nrf_ccm_subscribe_common(p_reg, task);
|
||||
}
|
||||
|
||||
#endif /* defined(DPPI_PRESENT) */
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Oticon A/S
|
||||
* Copyright (c) 2020 Nordic Semiconductor ASA
|
||||
* Copyright (c) 2020-2023 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -137,8 +137,9 @@ extern NRF_ECB_Type NRF_ECB_regs;
|
|||
extern NRF_AAR_Type NRF_AAR_regs;
|
||||
#undef NRF_AAR_NS_BASE
|
||||
#define NRF_AAR_NS_BASE (&NRF_AAR_regs)
|
||||
extern NRF_CCM_Type NRF_CCM_regs;
|
||||
#undef NRF_CCM_NS_BASE
|
||||
#define NRF_CCM_NS_BASE NULL
|
||||
#define NRF_CCM_NS_BASE (&NRF_CCM_regs)
|
||||
extern NRF_DPPIC_Type NRF_DPPIC_regs[];
|
||||
#undef NRF_DPPIC_NS_BASE
|
||||
#define NRF_DPPIC_NS_BASE (&NRF_DPPIC_regs[NHW_DPPI_NET_0])
|
||||
|
|
|
|||
Loading…
Reference in New Issue