hal_openisa

Commit Graph

Author	SHA1	Message	Date
Maureen Helm	40d049f69c	openisa: Make openisa hal a zephyr_library Stops leaking long source paths in build directories and makes them deterministic. When building samples/hello_world for rv32m1_vega_ri5cy, this changes the build directories from: build/ └── zephyr └── CMakeFiles └── zephyr.dir └── home └── maureen └── zephyrproject └── modules └── hal └── openisa └── vega_sdk_riscv └── devices └── RV32M1 └── drivers ├── fsl_clock.c.obj └── fsl_lpuart.c.obj to: build/ └── modules └── openisa └── lib..__modules__hal__openisa.a Signed-off-by: Maureen Helm <maureen.helm@nxp.com>	2020-06-10 12:42:14 -05:00
Marti Bolivar	35efa78dc8	soc: riscv32: add RV32M1 SoC as openisa_rv32m1 The OpenISA RV32M1 SoC has four CPU cores. Two of these are RISC-V 32-bit cores, which are named "RI5CY" and "ZERO-RISCY". (The other two cores are ARM Cortex-M0+ and -M4.) This patch adds basic SoC enablement for the RISC-V cores: - basic dtsi, to be extended as additional drivers are added - SoC definition in soc/riscv32/openisa_rv32m1 for RI5CY / ZERO-RISCY - system timer driver for RI5CY, based on LPTMR0 peripheral The timer driver will be generalized a bit soon once proper multi-level interrupt support is available. Emphasis is on supporting the RI5CY core as the more capable of the two; the ZERO-RISCY SoC definitions are a good starting point, but additional work setting up a dtsi and initial drivers is needed to support that core. Signed-off-by: Marti Bolivar <marti@foundries.io> Signed-off-by: Michael Scott <mike@foundries.io>	2019-01-25 11:59:46 -05:00

Author

SHA1

Message

Date

Maureen Helm

40d049f69c

openisa: Make openisa hal a zephyr_library

Stops leaking long source paths in build directories and makes them
deterministic.

When building samples/hello_world for rv32m1_vega_ri5cy, this changes
the build directories from:

build/
└── zephyr
    └── CMakeFiles
        └── zephyr.dir
            └── home
                └── maureen
                    └── zephyrproject
                        └── modules
                            └── hal
                                └── openisa
                                    └── vega_sdk_riscv
                                        └── devices
                                            └── RV32M1
                                                └── drivers
                                                    ├── fsl_clock.c.obj
                                                    └── fsl_lpuart.c.obj
to:

build/
└── modules
    └── openisa
        └── lib..__modules__hal__openisa.a

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>

2020-06-10 12:42:14 -05:00

Marti Bolivar

35efa78dc8

soc: riscv32: add RV32M1 SoC as openisa_rv32m1

The OpenISA RV32M1 SoC has four CPU cores. Two of these are RISC-V
32-bit cores, which are named "RI5CY" and "ZERO-RISCY". (The other two
cores are ARM Cortex-M0+ and -M4.) This patch adds basic SoC
enablement for the RISC-V cores:

- basic dtsi, to be extended as additional drivers are added
- SoC definition in soc/riscv32/openisa_rv32m1 for RI5CY / ZERO-RISCY
- system timer driver for RI5CY, based on LPTMR0 peripheral

The timer driver will be generalized a bit soon once proper
multi-level interrupt support is available.

Emphasis is on supporting the RI5CY core as the more capable of the
two; the ZERO-RISCY SoC definitions are a good starting point, but
additional work setting up a dtsi and initial drivers is needed to
support that core.

Signed-off-by: Marti Bolivar <marti@foundries.io>
Signed-off-by: Michael Scott <mike@foundries.io>

2019-01-25 11:59:46 -05:00

2 Commits