When -ffreestanding is not enabled, and GCC is able to use it's
knowledge of memset semantics, it sometimes gets it wrong, as in this
case. I'm not quite sure what is confusing it here, but the code sure
looks correct.
Signed-off-by: Keith Packard <keithp@keithp.com>
Sorts hal drivers alphabetically in the CMakeLists.txt file. Fixes
whitespace issues while we're here.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Add BLE specific CAUv3 firmware d_ip_ahb_cau3_syn.02.00.07.21.ver05
and the corresponding driver.
This driver implements functions for AES-CCM encrypt/decrypt and
Resolvable Private Address (RPA) handling.
Signed-off-by: Virgil Cervicescu <virgil.cervicescu@nxp.com>
Add the necessary files to enable the configuration of the
GenFSK LL, as it's present in the Vega RISCV platform.
The memory map for the RV32M1 ri5cy core has been updated
with the XCVR registers and additional defines, as they
were included in the SDK for the zero-riscy core. The
location of file that includes the added defines is here:
vega_sdk_riscv/devices/RV32M1/RV32M1_zero_riscy.h
The baseline for the updates done in this commit are
based on SDK Release Version 2.2.0.
Signed-off-by: Radu Alexe <radu.alexe@nxp.com>
Signed-off-by: David Leach <david.leach@nxp.com>
Signed-off-by: Ionut Ursescu <ionut.ursescu@nxp.com>
Add driver and device tree binding for the Low Power Inter-Integrated
Circuit (LPI2C) controllers found in the RV32M1 RI5CY SoC.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Rename reserved function names in drivers/ subdirectory. Update
function macros concatenatenating function names with '##'. As
there is a conflict between the existing gpio_sch_manage_callback()
and _gpio_sch_manage_callback() names, leave the latter unmodified.
Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
The OpenISA RV32M1 SoC has four CPU cores. Two of these are RISC-V
32-bit cores, which are named "RI5CY" and "ZERO-RISCY". (The other two
cores are ARM Cortex-M0+ and -M4.) This patch adds basic SoC
enablement for the RISC-V cores:
- basic dtsi, to be extended as additional drivers are added
- SoC definition in soc/riscv32/openisa_rv32m1 for RI5CY / ZERO-RISCY
- system timer driver for RI5CY, based on LPTMR0 peripheral
The timer driver will be generalized a bit soon once proper
multi-level interrupt support is available.
Emphasis is on supporting the RI5CY core as the more capable of the
two; the ZERO-RISCY SoC definitions are a good starting point, but
additional work setting up a dtsi and initial drivers is needed to
support that core.
Signed-off-by: Marti Bolivar <marti@foundries.io>
Signed-off-by: Michael Scott <mike@foundries.io>
This provides a HAL for the OpenISA RV32M1 SoC.
Origin: open-isa-rv32m1 GitHub organization
URL: https://github.com/open-isa-rv32m1/rv32m1_sdk_riscv
Revision: 365b1060f0947d5250c07b3eebdbc9e54cd0246e
Maintained-by: External
License: BSD-3-Clause
Signed-off-by: Marti Bolivar <marti@foundries.io>
Ryan McClelland