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modules: microchip: mec1501: Add missing ADC register field defines 

Origin
    MCHP
      https://github.com/MicrochipTech/hal_microchip

Status:
    version: 1.2.0

Add missing ADC register field defines for control and others.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
This commit is contained in:
Scott Worley 2021-04-26 13:10:04 -04:00 committed by Anas Nashif
parent f6999e83f9
commit a1bba228fd
1 changed files with 27 additions and 10 deletions
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37
mec/mec1501/component/adc.h
View File

@ -66,29 +66,46 @@
#define MCHP_ADC_RPT_DONE_NVIC_DIRECT 79u
/* Eight ADC channels numbered 0 - 7 */
#define MCHP_ADC_MAX_CHAN 8
#define MCHP_ADC_MAX_CHAN 8u
#define MCHP_ADC_MAX_CHAN_MASK 0x07u
/* Control register */
#define MCHP_ADC_CTRL_REG_OFS 0
#define MCHP_ADC_CTRL_REG_OFS 0u
#define MCHP_ADC_CTRL_REG_MASK 0xDFu
#define MCHP_ADC_CTRL_REG_RW_MASK 0x1Fu
#define MCHP_ADC_CTRL_REG_RW1C_MASK 0xC0u
#define MCHP_ADC_CTRL_ACTV BIT(0)
#define MCHP_ADC_CTRL_START_SNGL BIT(1)
#define MCHP_ADC_CTRL_START_RPT BIT(2)
#define MCHP_ADC_CTRL_PWRSV_DIS BIT(3)
#define MCHP_ADC_CTRL_SRST BIT(4)
#define MCHP_ADC_CTRL_RPT_DONE_STS BIT(6) /* R/W1C */
#define MCHP_ADC_CTRL_SNGL_DONE_STS BIT(7) /* R/W1C */
/* Delay register */
#define MCHP_ADC_DELAY_REG_OFS 4
/* Delay register. Start and repeat delays in units of 40 us */
#define MCHP_ADC_DELAY_REG_OFS 4u
#define MCHP_ADC_DELAY_REG_MASK 0xFFFFFFFFu
#define MCHP_ADC_DELAY_START_POS 0u
#define MCHP_ADC_DELAY_START_MASK 0xFFFFu
#define MCHP_ADC_DELAY_RPT_POS 16u
#define MCHP_ADC_DELAY_RPT_MASK 0xFFFF0000u
/* Status register */
#define MCHP_ADC_STATUS_REG_OFS 8
/* Status register. 0 <= n < MCHP_ADC_MAX_CHAN */
#define MCHP_ADC_STATUS_REG_OFS 8u
#define MCHP_ADC_STATUS_REG_MASK 0xFFFFu
#define MCHP_ADC_STATUS_CHAN(n) BIT(n)
/* Single Conversion Select register */
#define MCHP_ADC_SCS_REG_OFS 0x0C
#define MCHP_ADC_SCS_REG_OFS 0x0Cu
#define MCHP_ADC_SCS_REG_MASK 0xffu
#define MCHP_ADC_SCS_CH_0_7 0xffu
#define MCHP_ADC_SCS_CH(n) (1ul << ((n) & 0x07))
#define MCHP_ADC_SCS_CH(n) (1ul << ((n) & 0x07))
/* Repeat Conversion Select register */
#define MCHP_ADC_RCS_REG_OFS 0x10
#define MCHP_ADC_RCS_REG_OFS 0x10u
#define MCHP_ADC_RCS_REG_MASK 0xffu
#define MCHP_ADC_RCS_CH_0_7 0xffu
#define MCHP_ADC_RCS_CH(n) (1ul << ((n) & 0x07))
#define MCHP_ADC_RCS_CH(n) (1ul << ((n) & 0x07))
/* Channel reading registers */
#define MCHP_ADC_RDCH_REG_MASK 0xFFFul