modules: microchip: mec1501 ECIA register structure update
Origin:
MCHP
https://github.com/MicrochipTech/hal_microchip
Status:
version: 1.2.0
Update ECIA register structure allowing access by named GIRQxy
or GIRQ array access.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
This commit is contained in:
Scott Worley
Anas Nashif
parent
ba967b6a4b
commit
f6999e83f9
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@ -750,9 +750,6 @@ enum MCHP_GIRQ_IDS {
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/* Masks for blocks with multiple instances or sources */
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#define MCHP_GPIO_0240_0276_GIRQ_MASK 0x397Fu
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/**
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* @brief EC Interrupt Aggregator (ECIA)
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*/
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#define MCHP_GIRQ_START_NUM 8u
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#define MCHP_GIRQ_LAST_NUM 26u
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#define MCHP_GIRQ_IDX(girq) ((uint32_t)(girq) - 8ul)
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@ -760,67 +757,40 @@ enum MCHP_GIRQ_IDS {
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#define MCHP_GIRQ_IDX_MAX 19u
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#define MCHP_MAX_NVIC_IDX 6u
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/* size = 0x14(20) bytes */
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/** @brief ECIA GIRQn register block. Size = 0x14(20) bytes */
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typedef struct girq_regs
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{
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__IOM uint32_t SRC;
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__IOM uint32_t EN_SET;
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__IOM uint32_t RESULT;
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__IOM uint32_t EN_CLR;
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__IOM uint32_t SRC; /* R/W1C source status bits */
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__IOM uint32_t EN_SET; /* R/W1S Write 1 to set enable(s) */
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__IOM uint32_t RESULT; /* R/O equals SRC AND EN_SET */
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__IOM uint32_t EN_CLR; /* R/W1S Write 1 to clear enable(s) */
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uint8_t RSVD1[4];
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} GIRQ_Type;
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#if 0
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typedef struct ecia_regs
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{ /*!< (@ 0x4000E000) ECIA Structure */
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GIRQ_Type GIRQ08; /*!< (@ 0x0000) GIRQ08 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ09; /*!< (@ 0x0014) GIRQ09 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ10; /*!< (@ 0x0028) GIRQ10 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ11; /*!< (@ 0x003C) GIRQ11 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ12; /*!< (@ 0x0050) GIRQ12 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ13; /*!< (@ 0x0064) GIRQ13 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ14; /*!< (@ 0x0078) GIRQ14 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ15; /*!< (@ 0x008C) GIRQ15 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ16; /*!< (@ 0x00A0) GIRQ16 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ17; /*!< (@ 0x00B4) GIRQ17 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ18; /*!< (@ 0x00C8) GIRQ18 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ19; /*!< (@ 0x00DC) GIRQ19 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ20; /*!< (@ 0x00F0) GIRQ20 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ21; /*!< (@ 0x0104) GIRQ21 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ22; /*!< (@ 0x0118) GIRQ22 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ23; /*!< (@ 0x012C) GIRQ23 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ24; /*!< (@ 0x0140) GIRQ24 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ25; /*!< (@ 0x0154) GIRQ25 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ26; /*!< (@ 0x0168) GIRQ26 Source, Enable Set, Result, Enable Clear, Reserved */
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uint8_t RSVD2[(0x0200ul - 0x017Cul)]; /* offsets 0x017C - 0x1FF */
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__IOM uint32_t BLK_EN_SET; /*! (@ 0x00000200) Aggregated GIRQ output Enable Set */
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__IOM uint32_t BLK_EN_CLR; /*! (@ 0x00000204) Aggregated GIRQ output Enable Clear */
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__IM uint32_t BLK_ACTIVE; /*! (@ 0x00000204) GIRQ Active bitmap (RO) */
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} ECIA_Type;
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#else
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/** @brief EC Interrupt Aggregator (ECIA) */
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typedef struct ecia_regs
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{ /*!< (@ 0x4000E000) ECIA Structure */
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union {
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struct {
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GIRQ_Type GIRQ08; /*!< (@ 0x0000) GIRQ08 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ09; /*!< (@ 0x0014) GIRQ09 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ10; /*!< (@ 0x0028) GIRQ10 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ11; /*!< (@ 0x003C) GIRQ11 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ12; /*!< (@ 0x0050) GIRQ12 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ13; /*!< (@ 0x0064) GIRQ13 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ14; /*!< (@ 0x0078) GIRQ14 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ15; /*!< (@ 0x008C) GIRQ15 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ16; /*!< (@ 0x00A0) GIRQ16 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ17; /*!< (@ 0x00B4) GIRQ17 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ18; /*!< (@ 0x00C8) GIRQ18 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ19; /*!< (@ 0x00DC) GIRQ19 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ20; /*!< (@ 0x00F0) GIRQ20 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ21; /*!< (@ 0x0104) GIRQ21 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ22; /*!< (@ 0x0118) GIRQ22 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ23; /*!< (@ 0x012C) GIRQ23 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ24; /*!< (@ 0x0140) GIRQ24 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ25; /*!< (@ 0x0154) GIRQ25 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ26; /*!< (@ 0x0168) GIRQ26 Source, Enable Set, Result, Enable Clear, Reserved */
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GIRQ_Type GIRQ08; /*!< (@ 0x0000) GIRQ08 registers */
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GIRQ_Type GIRQ09; /*!< (@ 0x0014) GIRQ09 registers */
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GIRQ_Type GIRQ10; /*!< (@ 0x0028) GIRQ10 registers */
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GIRQ_Type GIRQ11; /*!< (@ 0x003C) GIRQ11 registers */
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GIRQ_Type GIRQ12; /*!< (@ 0x0050) GIRQ12 registers */
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GIRQ_Type GIRQ13; /*!< (@ 0x0064) GIRQ13 registers */
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GIRQ_Type GIRQ14; /*!< (@ 0x0078) GIRQ14 registers */
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GIRQ_Type GIRQ15; /*!< (@ 0x008C) GIRQ15 registers */
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GIRQ_Type GIRQ16; /*!< (@ 0x00A0) GIRQ16 registers */
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GIRQ_Type GIRQ17; /*!< (@ 0x00B4) GIRQ17 registers */
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GIRQ_Type GIRQ18; /*!< (@ 0x00C8) GIRQ18 registers */
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GIRQ_Type GIRQ19; /*!< (@ 0x00DC) GIRQ19 registers */
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GIRQ_Type GIRQ20; /*!< (@ 0x00F0) GIRQ20 registers */
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GIRQ_Type GIRQ21; /*!< (@ 0x0104) GIRQ21 registers */
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GIRQ_Type GIRQ22; /*!< (@ 0x0118) GIRQ22 registers */
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GIRQ_Type GIRQ23; /*!< (@ 0x012C) GIRQ23 registers */
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GIRQ_Type GIRQ24; /*!< (@ 0x0140) GIRQ24 registers */
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GIRQ_Type GIRQ25; /*!< (@ 0x0154) GIRQ25 registers */
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GIRQ_Type GIRQ26; /*!< (@ 0x0168) GIRQ26 registers */
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};
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GIRQ_Type GIRQ[19];
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};
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@ -829,9 +799,8 @@ typedef struct ecia_regs
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__IOM uint32_t BLK_EN_CLR; /*! (@ 0x00000204) Aggregated GIRQ output Enable Clear */
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__IM uint32_t BLK_ACTIVE; /*! (@ 0x00000204) GIRQ Active bitmap (RO) */
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} ECIA_Type;
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#endif
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#endif // #ifndef _ECIA_H
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#endif /* #ifndef _ECIA_H */
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/* end ecia.h */
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/** @}
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*/
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