289 lines
9.4 KiB
C
289 lines
9.4 KiB
C
/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <string.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_image_format.h"
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#include "flash_qio_mode.h"
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#include "esp_rom_efuse.h"
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#include "esp_rom_gpio.h"
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#include "esp_rom_sys.h"
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#include "esp_rom_uart.h"
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#include "esp_efuse.h"
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#include "bootloader_init.h"
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#include "bootloader_mem.h"
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#include "bootloader_clock.h"
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#include "bootloader_flash_config.h"
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#include "bootloader_flash.h"
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#include "bootloader_flash_priv.h"
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#include "bootloader_soc.h"
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#include "soc/cpu.h"
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#include "soc/dport_reg.h"
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#include "soc/efuse_reg.h"
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#include "soc/rtc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/extmem_reg.h"
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#include "soc/io_mux_reg.h"
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#include "soc/assist_debug_reg.h"
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#include "bootloader_wdt.h"
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#include "hal/wdt_hal.h"
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#include "esp32s3/rom/cache.h"
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#include "esp32s3/rom/ets_sys.h"
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#include "esp32s3/rom/spi_flash.h"
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#include "esp32s3/rom/uart.h"
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#include "esp_log.h"
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#include "mcuboot_config/mcuboot_config.h"
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static const char *TAG = "boot.esp32s3";
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extern esp_image_header_t WORD_ALIGNED_ATTR bootloader_image_hdr;
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static void bootloader_reset_mmu(void)
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{
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Cache_Suspend_DCache();
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Cache_Invalidate_DCache_All();
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Cache_MMU_Init();
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REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_CORE0_BUS);
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REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_CORE1_BUS);
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}
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static void update_flash_config(const esp_image_header_t *bootloader_hdr)
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{
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uint32_t size;
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switch (bootloader_hdr->spi_size) {
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case ESP_IMAGE_FLASH_SIZE_1MB:
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size = 1;
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break;
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case ESP_IMAGE_FLASH_SIZE_2MB:
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size = 2;
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break;
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case ESP_IMAGE_FLASH_SIZE_4MB:
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size = 4;
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break;
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case ESP_IMAGE_FLASH_SIZE_8MB:
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size = 8;
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break;
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case ESP_IMAGE_FLASH_SIZE_16MB:
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size = 16;
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break;
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default:
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size = 2;
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}
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uint32_t autoload = Cache_Suspend_DCache();
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// Set flash chip size
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esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);
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Cache_Resume_DCache(autoload);
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}
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void IRAM_ATTR bootloader_configure_spi_pins(int drv)
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{
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const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
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uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
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uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
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uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
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uint8_t d_gpio_num = SPI_D_GPIO_NUM;
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uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
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uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
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uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
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if (spiconfig == 0) {
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} else {
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clk_gpio_num = spiconfig & 0x3f;
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q_gpio_num = (spiconfig >> 6) & 0x3f;
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d_gpio_num = (spiconfig >> 12) & 0x3f;
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cs0_gpio_num = (spiconfig >> 18) & 0x3f;
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hd_gpio_num = (spiconfig >> 24) & 0x3f;
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wp_gpio_num = wp_pin;
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}
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esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
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esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
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esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
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esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
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if (hd_gpio_num <= MAX_PAD_GPIO_NUM) {
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esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
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}
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if (wp_gpio_num <= MAX_PAD_GPIO_NUM) {
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esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
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}
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}
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static void IRAM_ATTR bootloader_init_flash_configure(void)
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{
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bootloader_flash_dummy_config(&bootloader_image_hdr);
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bootloader_flash_cs_timing_config();
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}
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static esp_err_t bootloader_init_spi_flash(void)
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{
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bootloader_init_flash_configure();
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#ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
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const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
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if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) {
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ESP_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig");
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return ESP_FAIL;
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}
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#endif
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bootloader_flash_unlock();
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update_flash_config(&bootloader_image_hdr);
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//ensure the flash is write-protected
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bootloader_enable_wp();
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return ESP_OK;
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}
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static void bootloader_init_uart_console(void)
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{
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const int uart_num = 0;
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esp_rom_install_uart_printf();
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esp_rom_uart_tx_wait_idle(0);
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uint32_t clock_hz = UART_CLK_FREQ_ROM;
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esp_rom_uart_set_clock_baudrate(uart_num, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
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}
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static void wdt_reset_cpu0_info_enable(void)
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{
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REG_SET_BIT(SYSTEM_CPU_PERI_CLK_EN_REG, SYSTEM_CLK_EN_ASSIST_DEBUG);
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REG_CLR_BIT(SYSTEM_CPU_PERI_RST_EN_REG, SYSTEM_RST_EN_ASSIST_DEBUG);
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REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE_REG, 1);
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REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_RECORDING_REG, 1);
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}
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#if MCUBOOT_LOG_LEVEL >= MCUBOOT_LOG_LEVEL_DEBUG
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static void wdt_reset_info_dump(int cpu)
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{
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uint32_t inst = 0, pid = 0, stat = 0, data = 0, pc = 0,
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lsstat = 0, lsaddr = 0, lsdata = 0, dstat = 0;
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const char *cpu_name = cpu ? "APP" : "PRO";
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stat = 0xdeadbeef;
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pid = 0;
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if (cpu == 0) {
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inst = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_REG);
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dstat = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_REG);
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data = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_REG);
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pc = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG);
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lsstat = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_REG);
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lsaddr = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_REG);
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lsdata = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_REG);
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} else {
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inst = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_REG);
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dstat = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_REG);
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data = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_REG);
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pc = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_REG);
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lsstat = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_REG);
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lsaddr = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_REG);
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lsdata = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_REG);
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}
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ESP_LOGD(TAG, "WDT reset info: %s CPU STATUS 0x%08x", cpu_name, stat);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PID 0x%08x", cpu_name, pid);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGINST 0x%08x", cpu_name, inst);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGSTATUS 0x%08x", cpu_name, dstat);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGDATA 0x%08x", cpu_name, data);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGPC 0x%08x", cpu_name, pc);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0STAT 0x%08x", cpu_name, lsstat);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0ADDR 0x%08x", cpu_name, lsaddr);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0DATA 0x%08x", cpu_name, lsdata);
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}
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#endif
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static void bootloader_check_wdt_reset(void)
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{
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int wdt_rst = 0;
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soc_reset_reason_t rst_reas[2];
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rst_reas[0] = esp_rom_get_reset_reason(0);
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rst_reas[1] = esp_rom_get_reset_reason(1);
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if (rst_reas[0] == RESET_REASON_CORE_RTC_WDT || rst_reas[0] == RESET_REASON_CORE_MWDT0 || rst_reas[0] == RESET_REASON_CORE_MWDT1 ||
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rst_reas[0] == RESET_REASON_CPU0_MWDT0 || rst_reas[0] == RESET_REASON_CPU0_RTC_WDT) {
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ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
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wdt_rst = 1;
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}
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if (rst_reas[1] == RESET_REASON_CORE_RTC_WDT || rst_reas[1] == RESET_REASON_CORE_MWDT0 || rst_reas[1] == RESET_REASON_CORE_MWDT1 ||
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rst_reas[1] == RESET_REASON_CPU1_MWDT1 || rst_reas[1] == RESET_REASON_CPU1_RTC_WDT) {
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ESP_LOGW(TAG, "APP CPU has been reset by WDT.");
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wdt_rst = 1;
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}
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if (wdt_rst) {
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#if MCUBOOT_LOG_LEVEL >= MCUBOOT_LOG_LEVEL_DEBUG
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// if reset by WDT dump info from trace port
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wdt_reset_info_dump(0);
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wdt_reset_info_dump(1);
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#endif
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}
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wdt_reset_cpu0_info_enable();
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}
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static void bootloader_super_wdt_auto_feed(void)
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{
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REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, RTC_CNTL_SWD_WKEY_VALUE);
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REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN);
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REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, 0);}
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static inline void bootloader_ana_reset_config(void)
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{
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//Enable WDT, BOR, and GLITCH reset
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bootloader_ana_super_wdt_reset_config(true);
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bootloader_ana_bod_reset_config(true);
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bootloader_ana_clock_glitch_reset_config(true);
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}
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esp_err_t bootloader_init(void)
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{
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esp_err_t ret = ESP_OK;
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bootloader_ana_reset_config();
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bootloader_super_wdt_auto_feed();
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// protect memory region
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bootloader_init_mem();
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/* check that static RAM is after the stack */
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#ifndef NDEBUG
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{
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assert(&_bss_start <= &_bss_end);
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assert(&_data_start <= &_data_end);
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}
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#endif
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// clear bss section
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bootloader_clear_bss_section();
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// reset MMU
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bootloader_reset_mmu();
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// config clock
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bootloader_clock_configure();
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/* initialize uart console, from now on, we can use ets_printf */
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bootloader_init_uart_console();
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// Check and run XMC startup flow
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if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) {
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goto err;
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}
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// read bootloader header
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if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {
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goto err;
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}
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// read chip revision and check if it's compatible to bootloader
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if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) {
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goto err;
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}
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// initialize spi flash
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if ((ret = bootloader_init_spi_flash()) != ESP_OK) {
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goto err;
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}
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// check whether a WDT reset happend
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bootloader_check_wdt_reset();
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// config WDT
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bootloader_config_wdt();
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err:
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return ret;
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}
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