213 lines
6.2 KiB
C
213 lines
6.2 KiB
C
/*
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* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <string.h>
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#include <errno.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_image_format.h"
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#include "esp_rom_efuse.h"
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#include "esp_rom_gpio.h"
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#include "esp_rom_uart.h"
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#include "esp_rom_sys.h"
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#include "bootloader_init.h"
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#include "bootloader_common.h"
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#include "bootloader_clock.h"
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#include "bootloader_flash_config.h"
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#include "bootloader_mem.h"
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#include "bootloader_flash.h"
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#include "bootloader_flash_priv.h"
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#include "regi2c_ctrl.h"
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#include "soc/extmem_reg.h"
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#include "soc/io_mux_reg.h"
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#include "soc/efuse_reg.h"
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#include "soc/rtc.h"
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#include "esp32c3/rom/cache.h"
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#include "esp32c3/rom/spi_flash.h"
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#include "bootloader_wdt.h"
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#include "hal/wdt_hal.h"
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extern esp_image_header_t WORD_ALIGNED_ATTR bootloader_image_hdr;
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void IRAM_ATTR bootloader_configure_spi_pins(int drv)
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{
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const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
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uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
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uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
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uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
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uint8_t d_gpio_num = SPI_D_GPIO_NUM;
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uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
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uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
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uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
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if (spiconfig != 0) {
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clk_gpio_num = spiconfig & 0x3f;
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q_gpio_num = (spiconfig >> 6) & 0x3f;
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d_gpio_num = (spiconfig >> 12) & 0x3f;
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cs0_gpio_num = (spiconfig >> 18) & 0x3f;
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hd_gpio_num = (spiconfig >> 24) & 0x3f;
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wp_gpio_num = wp_pin;
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}
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esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
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esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
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esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
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esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
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if (hd_gpio_num <= MAX_PAD_GPIO_NUM) {
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esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
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}
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if (wp_gpio_num <= MAX_PAD_GPIO_NUM) {
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esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
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}
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}
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static void bootloader_reset_mmu(void)
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{
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Cache_Suspend_ICache();
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Cache_Invalidate_ICache_All();
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Cache_MMU_Init();
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REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS);
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REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS);
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}
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static void update_flash_config(const esp_image_header_t *bootloader_hdr)
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{
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uint32_t size;
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switch (bootloader_hdr->spi_size) {
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case ESP_IMAGE_FLASH_SIZE_1MB:
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size = 1;
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break;
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case ESP_IMAGE_FLASH_SIZE_2MB:
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size = 2;
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break;
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case ESP_IMAGE_FLASH_SIZE_4MB:
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size = 4;
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break;
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case ESP_IMAGE_FLASH_SIZE_8MB:
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size = 8;
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break;
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case ESP_IMAGE_FLASH_SIZE_16MB:
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size = 16;
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break;
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default:
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size = 2;
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}
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uint32_t autoload = Cache_Suspend_ICache();
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// Set flash chip size
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esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);
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Cache_Resume_ICache(autoload);
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}
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static void IRAM_ATTR bootloader_init_flash_configure(void)
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{
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bootloader_flash_dummy_config(&bootloader_image_hdr);
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bootloader_flash_cs_timing_config();
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}
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static void bootloader_spi_flash_resume(void)
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{
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bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0);
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esp_rom_spiflash_wait_idle(&g_rom_flashchip);
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}
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static esp_err_t bootloader_init_spi_flash(void)
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{
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bootloader_init_flash_configure();
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bootloader_spi_flash_resume();
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esp_rom_spiflash_unlock();
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update_flash_config(&bootloader_image_hdr);
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return ESP_OK;
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}
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static inline void bootloader_hardware_init(void)
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{
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// This check is always included in the bootloader so it can
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// print the minimum revision error message later in the boot
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if (bootloader_common_get_chip_revision() < 3) {
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REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_IPH, 1);
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REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 12);
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}
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}
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static inline void bootloader_glitch_reset_disable(void)
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{
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/*
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For origin chip & ECO1: only support swt reset;
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For ECO2: fix brownout reset bug, support swt & brownout reset;
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For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset.
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*/
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uint8_t chip_version = bootloader_common_get_chip_revision();
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if (chip_version < 2) {
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REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, RTC_CNTL_FIB_SUPER_WDT_RST);
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} else if (chip_version == 2) {
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REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, RTC_CNTL_FIB_SUPER_WDT_RST | RTC_CNTL_FIB_BOR_RST);
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}
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}
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static void bootloader_super_wdt_auto_feed(void)
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{
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REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, RTC_CNTL_SWD_WKEY_VALUE);
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REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN);
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REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, 0);
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}
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static void bootloader_init_uart_console(void)
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{
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const int uart_num = 0;
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esp_rom_install_uart_printf();
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esp_rom_uart_tx_wait_idle(0);
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uint32_t clock_hz = UART_CLK_FREQ_ROM;
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esp_rom_uart_set_clock_baudrate(uart_num, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
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}
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esp_err_t bootloader_init(void)
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{
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esp_err_t ret = ESP_OK;
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bootloader_hardware_init();
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bootloader_glitch_reset_disable();
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bootloader_super_wdt_auto_feed();
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// protect memory region
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bootloader_init_mem();
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/* check that static RAM is after the stack */
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assert(&_bss_start <= &_bss_end);
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assert(&_data_start <= &_data_end);
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// clear bss section
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bootloader_clear_bss_section();
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// reset MMU
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bootloader_reset_mmu();
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// config clock
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bootloader_clock_configure();
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/* initialize uart console, from now on, we can use ets_printf */
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bootloader_init_uart_console();
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// update flash ID
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bootloader_flash_update_id();
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// read bootloader header
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if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {
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goto err;
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}
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// read chip revision and check if it's compatible to bootloader
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if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) {
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goto err;
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}
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// initialize spi flash
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if ((ret = bootloader_init_spi_flash()) != ESP_OK) {
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goto err;
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}
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// config WDT
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bootloader_config_wdt();
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err:
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return ret;
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}
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