106 lines
2.2 KiB
C
106 lines
2.2 KiB
C
/*
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* Copyright (c) 2017, Xilinx Inc. and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* @file freertos/zynqmp_a53/sys.c
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* @brief machine specific system primitives implementation.
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*/
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#include <metal/compiler.h>
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#include <metal/io.h>
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#include <metal/sys.h>
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#include <stdint.h>
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#include "xil_cache.h"
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#include "xil_exception.h"
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#include "xil_mmu.h"
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#include "xreg_cortexa53.h"
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#include "xscugic.h"
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#define MB (1024 * 1024UL)
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#define GB (1024 * 1024 * 1024UL)
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void sys_irq_restore_enable(unsigned int flags)
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{
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Xil_ExceptionEnableMask(~flags);
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}
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unsigned int sys_irq_save_disable(void)
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{
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unsigned int state = mfcpsr() & XIL_EXCEPTION_ALL;
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if (state != XIL_EXCEPTION_ALL) {
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Xil_ExceptionDisableMask(XIL_EXCEPTION_ALL);
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}
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return state;
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}
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void metal_machine_cache_flush(void *addr, unsigned int len)
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{
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if (!addr && !len)
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Xil_DCacheFlush();
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else
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Xil_DCacheFlushRange((intptr_t)addr, len);
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}
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void metal_machine_cache_invalidate(void *addr, unsigned int len)
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{
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if (!addr && !len)
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Xil_DCacheInvalidate();
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else
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Xil_DCacheInvalidateRange((intptr_t)addr, len);
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}
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/**
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* @brief poll function until some event happens
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*/
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void metal_weak metal_generic_default_poll(void)
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{
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metal_asm volatile("wfi");
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}
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void *metal_machine_io_mem_map(void *va, metal_phys_addr_t pa,
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size_t size, unsigned int flags)
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{
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unsigned long section_offset;
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unsigned long ttb_addr;
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#if defined(__aarch64__)
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unsigned long ttb_size = (pa < 4*GB) ? 2*MB : 1*GB;
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#else
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unsigned long ttb_size = 1*MB;
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#endif
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if (!flags)
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return va;
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/* Ensure alignement on a section boundary */
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pa &= ~(ttb_size-1UL);
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/*
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* Loop through entire region of memory (one MMU section at a time).
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* Each section requires a TTB entry.
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*/
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for (section_offset = 0; section_offset < size; ) {
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/* Calculate translation table entry for this memory section */
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ttb_addr = (pa + section_offset);
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/* Write translation table entry value to entry address */
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Xil_SetTlbAttributes(ttb_addr, flags);
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#if defined(__aarch64__)
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/*
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* recalculate if we started below 4GB and going above in
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* 64bit mode
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*/
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if (ttb_addr >= 4*GB) {
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ttb_size = 1*GB;
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}
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#endif
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section_offset += ttb_size;
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}
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return va;
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}
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