345 lines
15 KiB
C
345 lines
15 KiB
C
/******************************************************************************
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* Filename: setup.c
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* Revised: 2020-02-14 13:45:15 +0100 (Fri, 14 Feb 2020)
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* Revision: 56765
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*
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* Description: Setup file for CC13xx/CC26xx devices.
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*
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* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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// Hardware headers
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#include "../inc/hw_types.h"
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#include "../inc/hw_memmap.h"
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#include "../inc/hw_adi.h"
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#include "../inc/hw_adi_2_refsys.h"
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#include "../inc/hw_adi_3_refsys.h"
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#include "../inc/hw_adi_4_aux.h"
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// Temporarily adding these defines as they are missing in hw_adi_4_aux.h
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#define ADI_4_AUX_O_LPMBIAS 0x0000000E
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#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M 0x0000003F
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#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S 0
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#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M 0x00000038
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#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S 3
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#include "../inc/hw_aon_ioc.h"
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#include "../inc/hw_aon_pmctl.h"
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#include "../inc/hw_aon_rtc.h"
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#include "../inc/hw_ddi_0_osc.h"
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#include "../inc/hw_ddi.h"
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#include "../inc/hw_ccfg.h"
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#include "../inc/hw_fcfg1.h"
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#include "../inc/hw_flash.h"
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#include "../inc/hw_prcm.h"
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#include "../inc/hw_vims.h"
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// Driverlib headers
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#include "aux_sysif.h"
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#include "chipinfo.h"
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#include "setup.h"
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#include "setup_rom.h"
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//*****************************************************************************
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//
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// Handle support for DriverLib in ROM:
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// This section will undo prototype renaming made in the header file
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//
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//*****************************************************************************
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#if !defined(DOXYGEN)
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#undef SetupTrimDevice
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#define SetupTrimDevice NOROM_SetupTrimDevice
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#endif
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//*****************************************************************************
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//
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// Defined CPU delay macro with microseconds as input
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// Quick check shows: (To be further investigated)
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// At 48 MHz RCOSC and VIMS.CONTROL.PREFETCH = 0, there is 5 cycles
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// At 48 MHz RCOSC and VIMS.CONTROL.PREFETCH = 1, there is 4 cycles
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// At 24 MHz RCOSC and VIMS.CONTROL.PREFETCH = 0, there is 3 cycles
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//
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//*****************************************************************************
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#define CPU_DELAY_MICRO_SECONDS( x ) \
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CPUdelay(((uint32_t)((( x ) * 48.0 ) / 5.0 )) - 1 )
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//*****************************************************************************
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//
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// Function declarations
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//
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//*****************************************************************************
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static void TrimAfterColdReset( void );
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static void TrimAfterColdResetWakeupFromShutDown( uint32_t ui32Fcfg1Revision );
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static void TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown( void );
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//*****************************************************************************
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//
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// Perform the necessary trim of the device which is not done in boot code
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//
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// This function should only execute coming from ROM boot. The current
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// implementation does not take soft reset into account. However, it does no
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// damage to execute it again. It only consumes time.
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//
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//*****************************************************************************
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void
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SetupTrimDevice(void)
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{
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uint32_t ui32Fcfg1Revision;
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uint32_t ui32AonSysResetctl;
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// Get layout revision of the factory configuration area
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// (Handle undefined revision as revision = 0)
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ui32Fcfg1Revision = HWREG(FCFG1_BASE + FCFG1_O_FCFG1_REVISION);
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if ( ui32Fcfg1Revision == 0xFFFFFFFF ) {
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ui32Fcfg1Revision = 0;
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}
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// This driverlib version and setup file is for the CC13x2, CC26x2 PG2.0 or later chips.
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// Halt if violated
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ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated();
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// Enable standby in flash bank
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HWREGBITW( FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0;
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// Select correct CACHE mode and set correct CACHE configuration
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#if ( CCFG_BASE == CCFG_BASE_DEFAULT )
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SetupSetCacheModeAccordingToCcfgSetting();
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#else
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NOROM_SetupSetCacheModeAccordingToCcfgSetting();
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#endif
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// 1. Check for powerdown
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// 2. Check for shutdown
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// 3. Assume cold reset if none of the above.
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//
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// It is always assumed that the application will freeze the latches in
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// AON_IOC when going to powerdown in order to retain the values on the IOs.
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//
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// NB. If this bit is not cleared before proceeding to powerdown, the IOs
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// will all default to the reset configuration when restarting.
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if( ! ( HWREGBITW( AON_IOC_BASE + AON_IOC_O_IOCLATCH, AON_IOC_IOCLATCH_EN_BITN )))
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{
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// NB. This should be calling a ROM implementation of required trim and
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// compensation
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// e.g. TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown()
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TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown();
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}
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// Check for shutdown
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//
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// When device is going to shutdown the hardware will automatically clear
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// the SLEEPDIS bit in the SLEEP register in the AON_PMCTL module.
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// It is left for the application to assert this bit when waking back up,
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// but not before the desired IO configuration has been re-established.
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else if( ! ( HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_SLEEPCTL, AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_BITN )))
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{
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// NB. This should be calling a ROM implementation of required trim and
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// compensation
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// e.g. TrimAfterColdResetWakeupFromShutDown() -->
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// TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown();
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TrimAfterColdResetWakeupFromShutDown(ui32Fcfg1Revision);
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TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown();
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}
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else
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{
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// Consider adding a check for soft reset to allow debugging to skip
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// this section!!!
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//
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// NB. This should be calling a ROM implementation of required trim and
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// compensation
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// e.g. TrimAfterColdReset() -->
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// TrimAfterColdResetWakeupFromShutDown() -->
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// TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown()
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TrimAfterColdReset();
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TrimAfterColdResetWakeupFromShutDown(ui32Fcfg1Revision);
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TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown();
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}
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// Set VIMS power domain control.
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// PDCTL1VIMS = 0 ==> VIMS power domain is only powered when CPU power domain is powered
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HWREG( PRCM_BASE + PRCM_O_PDCTL1VIMS ) = 0;
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// Configure optimal wait time for flash FSM in cases where flash pump
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// wakes up from sleep
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HWREG(FLASH_BASE + FLASH_O_FPAC1) = (HWREG(FLASH_BASE + FLASH_O_FPAC1) &
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~FLASH_FPAC1_PSLEEPTDIS_M) |
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(0x139<<FLASH_FPAC1_PSLEEPTDIS_S);
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// And finally at the end of the flash boot process:
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// SET BOOT_DET bits in AON_PMCTL to 3 if already found to be 1
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// Note: The BOOT_DET_x_CLR/SET bits must be manually cleared
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if ((( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) &
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( AON_PMCTL_RESETCTL_BOOT_DET_1_M | AON_PMCTL_RESETCTL_BOOT_DET_0_M )) >>
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AON_PMCTL_RESETCTL_BOOT_DET_0_S ) == 1 )
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{
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ui32AonSysResetctl = ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) &
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~( AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_M | AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_M |
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AON_PMCTL_RESETCTL_BOOT_DET_1_SET_M | AON_PMCTL_RESETCTL_BOOT_DET_0_SET_M | AON_PMCTL_RESETCTL_MCU_WARM_RESET_M ));
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HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = ui32AonSysResetctl | AON_PMCTL_RESETCTL_BOOT_DET_1_SET_M;
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HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = ui32AonSysResetctl;
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}
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// Make sure there are no ongoing VIMS mode change when leaving SetupTrimDevice()
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// (There should typically be no wait time here, but need to be sure)
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while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) {
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// Do nothing - wait for an eventual ongoing mode change to complete.
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}
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}
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//*****************************************************************************
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//
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//! \brief Trims to be applied when coming from POWER_DOWN (also called when
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//! coming from SHUTDOWN and PIN_RESET).
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//!
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//! \return None
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//
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//*****************************************************************************
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static void
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TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown( void )
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{
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// Currently no specific trim for Powerdown
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}
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//*****************************************************************************
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//
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//! \brief Trims to be applied when coming from SHUTDOWN (also called when
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//! coming from PIN_RESET).
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//!
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//! \param ui32Fcfg1Revision
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//!
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//! \return None
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//
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//*****************************************************************************
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static void
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TrimAfterColdResetWakeupFromShutDown(uint32_t ui32Fcfg1Revision)
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{
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uint32_t ccfg_ModeConfReg ;
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// Check in CCFG for alternative DCDC setting
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if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING ) == 0 ) {
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// ADI_3_REFSYS:DCDCCTL5[3] (=DITHER_EN) = CCFG_MODE_CONF_1[19] (=ALT_DCDC_DITHER_EN)
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// ADI_3_REFSYS:DCDCCTL5[2:0](=IPEAK ) = CCFG_MODE_CONF_1[18:16](=ALT_DCDC_IPEAK )
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// Using a single 4-bit masked write since layout is equal for both source and destination
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HWREGB( ADI3_BASE + ADI_O_MASK4B + ( ADI_3_REFSYS_O_DCDCCTL5 * 2 )) = ( 0xF0 |
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( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) >> CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S ));
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}
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// TBD - Temporarily removed for CC13x2 / CC26x2
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// Force DCDC to use RCOSC before starting up XOSC.
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// Clock loss detector does not use XOSC until SCLK_HF actually switches
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// and thus DCDC is not protected from clock loss on XOSC in that time frame.
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// The force must be released when the switch to XOSC has happened. This is done
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// in OSCHfSourceSwitch().
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HWREG(AUX_DDI0_OSC_BASE + DDI_O_MASK16B + (DDI_0_OSC_O_CTL0 << 1) + 4) = DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M | (DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M >> 16);
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// Dummy read to ensure that the write has propagated
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HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0);
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// read the MODE_CONF register in CCFG
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ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF );
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// First part of trim done after cold reset and wakeup from shutdown:
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// -Adjust the VDDR_TRIM_SLEEP value.
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// -Configure DCDC.
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SetupAfterColdResetWakeupFromShutDownCfg1( ccfg_ModeConfReg );
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// Addition to the CC1352 boost mode for HWREV >= 2.0
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// The combination VDDR_EXT_LOAD=0 and VDDS_BOD_LEVEL=1 is defined to select boost mode
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if ((( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_EXT_LOAD ) == 0 ) &&
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(( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDS_BOD_LEVEL ) != 0 ) )
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{
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HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL3 ) = ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST ;
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}
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// Second part of trim done after cold reset and wakeup from shutdown:
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// -Configure XOSC.
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#if ( CCFG_BASE == CCFG_BASE_DEFAULT )
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SetupAfterColdResetWakeupFromShutDownCfg2( ui32Fcfg1Revision, ccfg_ModeConfReg );
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#else
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NOROM_SetupAfterColdResetWakeupFromShutDownCfg2( ui32Fcfg1Revision, ccfg_ModeConfReg );
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#endif
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{
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uint32_t trimReg ;
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uint32_t ui32TrimValue ;
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//--- Propagate the LPM_BIAS trim ---
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trimReg = HWREG( FCFG1_BASE + FCFG1_O_DAC_BIAS_CNF );
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ui32TrimValue = (( trimReg & FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_M ) >>
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FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_S ) ;
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HWREGB( AUX_ADI4_BASE + ADI_4_AUX_O_LPMBIAS ) = (( ui32TrimValue << ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S ) &
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ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M ) ;
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// Set LPM_BIAS_BACKUP_EN according to FCFG1 configuration
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if ( trimReg & FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN ) {
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HWREGB( ADI3_BASE + ADI_O_SET + ADI_3_REFSYS_O_AUX_DEBUG ) = ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN;
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} else {
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HWREGB( ADI3_BASE + ADI_O_CLR + ADI_3_REFSYS_O_AUX_DEBUG ) = ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN;
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}
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// Set LPM_BIAS_WIDTH_TRIM according to FCFG1 configuration
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{
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uint32_t widthTrim = (( trimReg & FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_M ) >> FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_S );
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HWREGH( AUX_ADI4_BASE + ADI_O_MASK8B + ( ADI_4_AUX_O_COMP * 2 )) = // Set LPM_BIAS_WIDTH_TRIM = 3
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(( ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M << 8 ) | // Set mask (bits to be written) in [15:8]
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( widthTrim << ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S ) ); // Set value (in correct bit pos) in [7:0]
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}
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}
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// Third part of trim done after cold reset and wakeup from shutdown:
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// -Configure HPOSC.
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// -Setup the LF clock.
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#if ( CCFG_BASE == CCFG_BASE_DEFAULT )
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SetupAfterColdResetWakeupFromShutDownCfg3( ccfg_ModeConfReg );
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#else
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NOROM_SetupAfterColdResetWakeupFromShutDownCfg3( ccfg_ModeConfReg );
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#endif
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// Set AUX into power down active mode
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AUXSYSIFOpModeChange( AUX_SYSIF_OPMODE_TARGET_PDA );
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// Disable EFUSE clock
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HWREGBITW( FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_EFUSECLK_BITN ) = 1;
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}
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//*****************************************************************************
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//
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//! \brief Trims to be applied when coming from PIN_RESET.
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//!
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//! \return None
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//
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//*****************************************************************************
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static void
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TrimAfterColdReset( void )
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{
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// Currently no specific trim for Cold Reset
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}
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