648 lines
21 KiB
C
648 lines
21 KiB
C
/******************************************************************************
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* Filename: prcm.c
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* Revised: 2020-02-14 11:30:20 +0100 (Fri, 14 Feb 2020)
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* Revision: 56760
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*
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* Description: Driver for the PRCM.
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*
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* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#include "prcm.h"
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//*****************************************************************************
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//
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// Handle support for DriverLib in ROM:
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// This section will undo prototype renaming made in the header file
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//
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//*****************************************************************************
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#if !defined(DOXYGEN)
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#undef PRCMInfClockConfigureSet
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#define PRCMInfClockConfigureSet NOROM_PRCMInfClockConfigureSet
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#undef PRCMInfClockConfigureGet
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#define PRCMInfClockConfigureGet NOROM_PRCMInfClockConfigureGet
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#undef PRCMAudioClockConfigSet
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#define PRCMAudioClockConfigSet NOROM_PRCMAudioClockConfigSet
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#undef PRCMAudioClockConfigSetOverride
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#define PRCMAudioClockConfigSetOverride NOROM_PRCMAudioClockConfigSetOverride
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#undef PRCMAudioClockInternalSource
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#define PRCMAudioClockInternalSource NOROM_PRCMAudioClockInternalSource
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#undef PRCMAudioClockExternalSource
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#define PRCMAudioClockExternalSource NOROM_PRCMAudioClockExternalSource
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#undef PRCMPowerDomainOn
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#define PRCMPowerDomainOn NOROM_PRCMPowerDomainOn
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#undef PRCMPowerDomainOff
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#define PRCMPowerDomainOff NOROM_PRCMPowerDomainOff
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#undef PRCMPeripheralRunEnable
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#define PRCMPeripheralRunEnable NOROM_PRCMPeripheralRunEnable
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#undef PRCMPeripheralRunDisable
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#define PRCMPeripheralRunDisable NOROM_PRCMPeripheralRunDisable
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#undef PRCMPeripheralSleepEnable
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#define PRCMPeripheralSleepEnable NOROM_PRCMPeripheralSleepEnable
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#undef PRCMPeripheralSleepDisable
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#define PRCMPeripheralSleepDisable NOROM_PRCMPeripheralSleepDisable
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#undef PRCMPeripheralDeepSleepEnable
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#define PRCMPeripheralDeepSleepEnable NOROM_PRCMPeripheralDeepSleepEnable
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#undef PRCMPeripheralDeepSleepDisable
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#define PRCMPeripheralDeepSleepDisable NOROM_PRCMPeripheralDeepSleepDisable
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#undef PRCMPowerDomainStatus
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#define PRCMPowerDomainStatus NOROM_PRCMPowerDomainStatus
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#undef PRCMDeepSleep
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#define PRCMDeepSleep NOROM_PRCMDeepSleep
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#endif
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//*****************************************************************************
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//
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// Arrays that maps the "peripheral set" number (which is stored in
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// bits[11:8] of the PRCM_PERIPH_* defines) to the PRCM register that
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// contains the relevant bit for that peripheral.
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//
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//*****************************************************************************
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// Run mode registers
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static const uint32_t g_pui32RCGCRegs[] =
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{
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PRCM_O_GPTCLKGR , // Index 0
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PRCM_O_SSICLKGR , // Index 1
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PRCM_O_UARTCLKGR , // Index 2
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PRCM_O_I2CCLKGR , // Index 3
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PRCM_O_SECDMACLKGR , // Index 4
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PRCM_O_GPIOCLKGR , // Index 5
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PRCM_O_I2SCLKGR // Index 6
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};
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// Sleep mode registers
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static const uint32_t g_pui32SCGCRegs[] =
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{
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PRCM_O_GPTCLKGS , // Index 0
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PRCM_O_SSICLKGS , // Index 1
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PRCM_O_UARTCLKGS , // Index 2
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PRCM_O_I2CCLKGS , // Index 3
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PRCM_O_SECDMACLKGS , // Index 4
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PRCM_O_GPIOCLKGS , // Index 5
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PRCM_O_I2SCLKGS // Index 6
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};
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// Deep sleep mode registers
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static const uint32_t g_pui32DCGCRegs[] =
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{
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PRCM_O_GPTCLKGDS , // Index 0
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PRCM_O_SSICLKGDS , // Index 1
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PRCM_O_UARTCLKGDS , // Index 2
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PRCM_O_I2CCLKGDS , // Index 3
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PRCM_O_SECDMACLKGDS , // Index 4
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PRCM_O_GPIOCLKGDS , // Index 5
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PRCM_O_I2SCLKGDS // Index 6
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};
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//*****************************************************************************
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//
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// This macro extracts the array index out of the peripheral number
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//
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//*****************************************************************************
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#define PRCM_PERIPH_INDEX(a) (((a) >> 8) & 0xf)
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//*****************************************************************************
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//
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// This macro extracts the peripheral instance number and generates bit mask
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//
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//*****************************************************************************
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#define PRCM_PERIPH_MASKBIT(a) (0x00000001 << ((a) & 0x1f))
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//*****************************************************************************
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//
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// Configure the infrastructure clock.
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//
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//*****************************************************************************
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void
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PRCMInfClockConfigureSet(uint32_t ui32ClkDiv, uint32_t ui32PowerMode)
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{
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uint32_t ui32Divisor;
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// Check the arguments.
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ASSERT((ui32ClkDiv == PRCM_CLOCK_DIV_1) ||
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(ui32ClkDiv == PRCM_CLOCK_DIV_2) ||
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(ui32ClkDiv == PRCM_CLOCK_DIV_8) ||
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(ui32ClkDiv == PRCM_CLOCK_DIV_32));
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ASSERT((ui32PowerMode == PRCM_RUN_MODE) ||
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(ui32PowerMode == PRCM_SLEEP_MODE) ||
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(ui32PowerMode == PRCM_DEEP_SLEEP_MODE));
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ui32Divisor = 0;
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// Find the correct division factor.
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if(ui32ClkDiv == PRCM_CLOCK_DIV_1)
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{
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ui32Divisor = 0x0;
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}
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else if(ui32ClkDiv == PRCM_CLOCK_DIV_2)
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{
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ui32Divisor = 0x1;
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}
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else if(ui32ClkDiv == PRCM_CLOCK_DIV_8)
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{
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ui32Divisor = 0x2;
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}
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else if(ui32ClkDiv == PRCM_CLOCK_DIV_32)
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{
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ui32Divisor = 0x3;
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}
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// Determine the correct power mode set the division factor accordingly.
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if(ui32PowerMode == PRCM_RUN_MODE)
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{
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HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR) = ui32Divisor;
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}
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else if(ui32PowerMode == PRCM_SLEEP_MODE)
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{
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HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS) = ui32Divisor;
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}
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else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE)
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{
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HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS) = ui32Divisor;
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}
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}
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//*****************************************************************************
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//
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// Use this function to get the infrastructure clock configuration
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//
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//*****************************************************************************
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uint32_t
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PRCMInfClockConfigureGet(uint32_t ui32PowerMode)
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{
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uint32_t ui32ClkDiv;
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uint32_t ui32Divisor;
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// Check the arguments.
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ASSERT((ui32PowerMode == PRCM_RUN_MODE) ||
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(ui32PowerMode == PRCM_SLEEP_MODE) ||
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(ui32PowerMode == PRCM_DEEP_SLEEP_MODE));
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ui32ClkDiv = 0;
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ui32Divisor = 0;
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// Determine the correct power mode.
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if(ui32PowerMode == PRCM_RUN_MODE)
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{
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ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR);
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}
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else if(ui32PowerMode == PRCM_SLEEP_MODE)
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{
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ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS);
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}
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else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE)
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{
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ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS);
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}
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// Find the correct division factor.
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if(ui32ClkDiv == 0x0)
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{
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ui32Divisor = PRCM_CLOCK_DIV_1;
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}
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else if(ui32ClkDiv == 0x1)
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{
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ui32Divisor = PRCM_CLOCK_DIV_2;
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}
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else if(ui32ClkDiv == 0x2)
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{
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ui32Divisor = PRCM_CLOCK_DIV_8;
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}
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else if(ui32ClkDiv == 0x3)
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{
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ui32Divisor = PRCM_CLOCK_DIV_32;
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}
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// Return the clock division factor.
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return ui32Divisor;
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}
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//*****************************************************************************
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//
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// Configure the audio clock generation
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//
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//*****************************************************************************
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void
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PRCMAudioClockConfigSet(uint32_t ui32ClkConfig, uint32_t ui32SampleRate)
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{
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uint32_t ui32Reg;
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uint32_t ui32MstDiv;
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uint32_t ui32BitDiv;
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uint32_t ui32WordDiv;
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// Check the arguments.
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ASSERT(!(ui32ClkConfig & (PRCM_I2SCLKCTL_WCLK_PHASE_M | PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M)));
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ASSERT((ui32SampleRate == I2S_SAMPLE_RATE_16K) ||
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(ui32SampleRate == I2S_SAMPLE_RATE_24K) ||
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(ui32SampleRate == I2S_SAMPLE_RATE_32K) ||
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(ui32SampleRate == I2S_SAMPLE_RATE_48K));
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ui32MstDiv = 0;
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ui32BitDiv = 0;
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ui32WordDiv = 0;
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// Make sure the audio clock generation is disabled before reconfiguring.
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PRCMAudioClockDisable();
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// Define the clock division factors for the audio interface.
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switch(ui32SampleRate)
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{
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case I2S_SAMPLE_RATE_16K :
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ui32MstDiv = 6;
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ui32BitDiv = 60;
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ui32WordDiv = 25;
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break;
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case I2S_SAMPLE_RATE_24K :
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ui32MstDiv = 4;
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ui32BitDiv = 40;
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ui32WordDiv = 25;
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break;
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case I2S_SAMPLE_RATE_32K :
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ui32MstDiv = 3;
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ui32BitDiv = 30;
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ui32WordDiv = 25;
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break;
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case I2S_SAMPLE_RATE_48K :
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ui32MstDiv = 2;
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ui32BitDiv = 20;
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ui32WordDiv = 25;
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break;
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}
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// Make sure to compensate the Frame clock division factor if using single
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// phase format.
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if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE)
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{
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ui32WordDiv -= 1;
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}
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// Write the clock division factors.
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HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv;
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HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv;
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HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv;
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// Configure the Word clock format and polarity.
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ui32Reg = HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M |
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PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M);
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HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig;
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}
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//*****************************************************************************
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//
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// Configure the audio clock generation with manual setting of clock divider.
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//
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//*****************************************************************************
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void
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PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui32MstDiv,
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uint32_t ui32BitDiv, uint32_t ui32WordDiv)
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{
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uint32_t ui32Reg;
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// Check the arguments.
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ASSERT(!(ui32ClkConfig & (PRCM_I2SCLKCTL_WCLK_PHASE_M | PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M)));
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// Make sure the audio clock generation is disabled before reconfiguring.
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PRCMAudioClockDisable();
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// Make sure to compensate the Frame clock division factor if using single
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// phase format.
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if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE)
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{
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ui32WordDiv -= 1;
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}
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// Write the clock division factors.
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HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv;
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HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv;
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HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv;
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// Configure the Word clock format and polarity.
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ui32Reg = HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M |
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PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M);
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HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig;
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}
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//*****************************************************************************
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//
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// Configure the audio clocks for I2S module
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//
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//*****************************************************************************
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void
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PRCMAudioClockConfigOverride(uint8_t ui8SamplingEdge,
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uint8_t ui8WCLKPhase,
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uint32_t ui32MstDiv,
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uint32_t ui32BitDiv,
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uint32_t ui32WordDiv)
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{
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// Check the arguments.
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ASSERT( ui8BitsPerSample == PRCM_WCLK_SINGLE_PHASE
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|| ui8BitsPerSample == PRCM_WCLK_DUAL_PHASE
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|| ui8BitsPerSample == PRCM_WCLK_USER_DEF);
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// Make sure the audio clock generation is disabled before reconfiguring.
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PRCMAudioClockDisable();
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// Make sure to compensate the Frame clock division factor if using single
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// phase format.
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if((ui8WCLKPhase) == PRCM_WCLK_SINGLE_PHASE)
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{
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ui32WordDiv -= 1;
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}
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// Write the clock division factors.
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HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv;
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HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv;
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HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv;
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// Configure the Word clock format and polarity and enable it.
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HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = (ui8SamplingEdge << PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_S) |
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(ui8WCLKPhase << PRCM_I2SCLKCTL_WCLK_PHASE_S ) |
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(1 << PRCM_I2SCLKCTL_EN_S );
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}
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//*****************************************************************************
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//
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// Configure the clocks as "internally generated".
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//
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//*****************************************************************************
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void PRCMAudioClockInternalSource(void)
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{
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HWREGBITW(PRCM_BASE + PRCM_O_I2SBCLKSEL, PRCM_I2SBCLKSEL_SRC_BITN) = 1;
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}
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//*****************************************************************************
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//
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// Configure the clocks as "externally generated".
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//
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//*****************************************************************************
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void PRCMAudioClockExternalSource(void)
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{
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HWREGBITW(PRCM_BASE + PRCM_O_I2SBCLKSEL, PRCM_I2SBCLKSEL_SRC_BITN) = 0;
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}
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//*****************************************************************************
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//
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// Turn power on in power domains in the MCU domain
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//
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//*****************************************************************************
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void
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PRCMPowerDomainOn(uint32_t ui32Domains)
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{
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// Check the arguments.
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ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) ||
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(ui32Domains & PRCM_DOMAIN_SERIAL) ||
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(ui32Domains & PRCM_DOMAIN_PERIPH) ||
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(ui32Domains & PRCM_DOMAIN_CPU) ||
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(ui32Domains & PRCM_DOMAIN_VIMS));
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// Assert the request to power on the right domains.
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if(ui32Domains & PRCM_DOMAIN_RFCORE)
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{
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HWREG(PRCM_BASE + PRCM_O_PDCTL0RFC ) = 1;
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}
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if(ui32Domains & PRCM_DOMAIN_SERIAL)
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{
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HWREG(PRCM_BASE + PRCM_O_PDCTL0SERIAL) = 1;
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}
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if(ui32Domains & PRCM_DOMAIN_PERIPH)
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{
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HWREG(PRCM_BASE + PRCM_O_PDCTL0PERIPH) = 1;
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}
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if(ui32Domains & PRCM_DOMAIN_VIMS)
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{
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HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS ) = 1;
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}
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if(ui32Domains & PRCM_DOMAIN_CPU)
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{
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HWREG(PRCM_BASE + PRCM_O_PDCTL1CPU ) = 1;
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}
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}
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//*****************************************************************************
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//
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// Turn off a specific power domain
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//
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//*****************************************************************************
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void
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PRCMPowerDomainOff(uint32_t ui32Domains)
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{
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// Check the arguments.
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ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) ||
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(ui32Domains & PRCM_DOMAIN_SERIAL) ||
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(ui32Domains & PRCM_DOMAIN_PERIPH) ||
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(ui32Domains & PRCM_DOMAIN_CPU) ||
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(ui32Domains & PRCM_DOMAIN_VIMS));
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// Assert the request to power off the right domains.
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if(ui32Domains & PRCM_DOMAIN_RFCORE)
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{
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HWREG(PRCM_BASE + PRCM_O_PDCTL0RFC ) = 0;
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}
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if(ui32Domains & PRCM_DOMAIN_SERIAL)
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{
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HWREG(PRCM_BASE + PRCM_O_PDCTL0SERIAL) = 0;
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}
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if(ui32Domains & PRCM_DOMAIN_PERIPH)
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{
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HWREG(PRCM_BASE + PRCM_O_PDCTL0PERIPH) = 0;
|
|
}
|
|
if(ui32Domains & PRCM_DOMAIN_VIMS)
|
|
{
|
|
// Write bits ui32Domains[17:16] to the VIMS_MODE alias register.
|
|
// PRCM_DOMAIN_VIMS sets VIMS_MODE=0b00, PRCM_DOMAIN_VIMS_OFF_NO_WAKEUP sets VIMS_MODE=0b10.
|
|
ASSERT(!(ui32Domains & 0x00010000));
|
|
HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS ) = ( ui32Domains >> 16 ) & 3;
|
|
}
|
|
if(ui32Domains & PRCM_DOMAIN_CPU)
|
|
{
|
|
HWREG(PRCM_BASE + PRCM_O_PDCTL1CPU ) = 0;
|
|
}
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Enables a peripheral in Run mode
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
PRCMPeripheralRunEnable(uint32_t ui32Peripheral)
|
|
{
|
|
// Check the arguments.
|
|
ASSERT(PRCMPeripheralValid(ui32Peripheral));
|
|
|
|
// Enable module in Run Mode.
|
|
HWREG(PRCM_BASE + g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |=
|
|
PRCM_PERIPH_MASKBIT(ui32Peripheral);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Disables a peripheral in Run mode
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
PRCMPeripheralRunDisable(uint32_t ui32Peripheral)
|
|
{
|
|
// Check the arguments.
|
|
ASSERT(PRCMPeripheralValid(ui32Peripheral));
|
|
|
|
// Disable module in Run Mode.
|
|
HWREG(PRCM_BASE + g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &=
|
|
~PRCM_PERIPH_MASKBIT(ui32Peripheral);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Enables a peripheral in sleep mode
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
PRCMPeripheralSleepEnable(uint32_t ui32Peripheral)
|
|
{
|
|
// Check the arguments.
|
|
ASSERT(PRCMPeripheralValid(ui32Peripheral));
|
|
|
|
// Enable this peripheral in sleep mode.
|
|
HWREG(PRCM_BASE + g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |=
|
|
PRCM_PERIPH_MASKBIT(ui32Peripheral);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Disables a peripheral in sleep mode
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
PRCMPeripheralSleepDisable(uint32_t ui32Peripheral)
|
|
{
|
|
// Check the arguments.
|
|
ASSERT(PRCMPeripheralValid(ui32Peripheral));
|
|
|
|
// Disable this peripheral in sleep mode
|
|
HWREG(PRCM_BASE + g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &=
|
|
~PRCM_PERIPH_MASKBIT(ui32Peripheral);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Enables a peripheral in deep-sleep mode
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
PRCMPeripheralDeepSleepEnable(uint32_t ui32Peripheral)
|
|
{
|
|
// Check the arguments.
|
|
ASSERT(PRCMPeripheralValid(ui32Peripheral));
|
|
|
|
// Enable this peripheral in deep-sleep mode.
|
|
HWREG(PRCM_BASE + g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |=
|
|
PRCM_PERIPH_MASKBIT(ui32Peripheral);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Disables a peripheral in deep-sleep mode
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
PRCMPeripheralDeepSleepDisable(uint32_t ui32Peripheral)
|
|
{
|
|
// Check the arguments.
|
|
ASSERT(PRCMPeripheralValid(ui32Peripheral));
|
|
|
|
// Disable this peripheral in Deep Sleep mode.
|
|
HWREG(PRCM_BASE + g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &=
|
|
~PRCM_PERIPH_MASKBIT(ui32Peripheral);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Get the status for a specific power domain
|
|
//
|
|
//*****************************************************************************
|
|
uint32_t
|
|
PRCMPowerDomainStatus(uint32_t ui32Domains)
|
|
{
|
|
bool bStatus;
|
|
uint32_t ui32StatusRegister0;
|
|
uint32_t ui32StatusRegister1;
|
|
|
|
// Check the arguments.
|
|
ASSERT((ui32Domains & (PRCM_DOMAIN_RFCORE |
|
|
PRCM_DOMAIN_SERIAL |
|
|
PRCM_DOMAIN_PERIPH)));
|
|
|
|
bStatus = true;
|
|
ui32StatusRegister0 = HWREG(PRCM_BASE + PRCM_O_PDSTAT0);
|
|
ui32StatusRegister1 = HWREG(PRCM_BASE + PRCM_O_PDSTAT1);
|
|
|
|
// Return the correct power status.
|
|
if(ui32Domains & PRCM_DOMAIN_RFCORE)
|
|
{
|
|
bStatus = bStatus &&
|
|
((ui32StatusRegister0 & PRCM_PDSTAT0_RFC_ON) ||
|
|
(ui32StatusRegister1 & PRCM_PDSTAT1_RFC_ON));
|
|
}
|
|
if(ui32Domains & PRCM_DOMAIN_SERIAL)
|
|
{
|
|
bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_SERIAL_ON);
|
|
}
|
|
if(ui32Domains & PRCM_DOMAIN_PERIPH)
|
|
{
|
|
bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_PERIPH_ON);
|
|
}
|
|
|
|
// Return the status.
|
|
return (bStatus ? PRCM_DOMAIN_POWER_ON : PRCM_DOMAIN_POWER_OFF);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Put the processor into deep-sleep mode
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
PRCMDeepSleep(void)
|
|
{
|
|
// Enable deep-sleep.
|
|
HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP;
|
|
|
|
// Wait for an interrupt.
|
|
CPUwfi();
|
|
|
|
// Disable deep-sleep so that a future sleep will work correctly.
|
|
HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP);
|
|
}
|