47 lines
2.0 KiB
C
47 lines
2.0 KiB
C
/*
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* ==========================================================
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*
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* Copyright (C) 2020 QuickLogic Corporation
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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* http://www.apache.org/licenses/LICENSE-2.0
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* File : eoss3_hal_fpga_sdma_reg.h
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* Purpose :
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*
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* ===========================================================
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*
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*/
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#ifndef HAL_EOSS3_HAL_FPGA_SDMA_REG_H_
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#define HAL_EOSS3_HAL_FPGA_SDMA_REG_H_
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#define FB_FSDMA_BASE (FPGA_PERIPH_BASE + 0x10000)
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#define FB_SDMA ((FSDMA_TypeDef *) FB_FSDMA_BASE)
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#define FSDMA_CH0_DATA_REGISTER (FB_FSDMA_BASE + 0x1000)
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#define FSDMA_CH1_DATA_REGISTER (FB_FSDMA_BASE + 0x2000)
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#define FSDMA_CH2_DATA_REGISTER (FB_FSDMA_BASE + 0x3000)
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#define FSDMA_CH3_DATA_REGISTER (FB_FSDMA_BASE + 0x4000)
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/* FPGA SDMA register definitions. */
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typedef struct
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{
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__IO uint32_t FSDMA_ENR; /*0x0 */ //DMA Enable Register
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__IO uint32_t FSDMA_SR; /*0x4 */ // DMA status Register
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__IO uint32_t FSDMA_INTEN; /*0x8 */ //DMA Interrupt Enable Register
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} FSDMA_TypeDef;
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#define FSDMA_CHANNEL_EN(ch) (0x1 << ch) //DMA Channel Enable
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#define FSDMA_CHANNEL_INTR_CLR(ch) (0x1 << ch) //DMA Interrupt Status [Read - Status, Write - clearing interrupt]
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#define FSDMA_CHANNEL_INTR_EN(ch) (0x1 << ch) //DMA Interrupt Enable at IP level [NVIC level enabling is seperate from this]
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#define FSDMA_CHANNEL_POS(ch) (ch) // Get Channel Position value
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#endif //HAL_EOSS3_HAL_FPGA_SDMA_REG_H_
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