117 lines
4.6 KiB
C
117 lines
4.6 KiB
C
/*
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* ==========================================================
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*
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* Copyright (C) 2020 QuickLogic Corporation
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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* http://www.apache.org/licenses/LICENSE-2.0
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* File : eoss3_hal_fpga_gpio.h
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* Purpose :
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*
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* ===========================================================
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*
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*/
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#ifndef __EOSS3_HAL_FPGA_GPIO_H
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#define __EOSS3_HAL_FPGA_GPIO_H
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#include "eoss3_dev.h"
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#include "eoss3_hal_def.h"
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#define xCUR_BOARD
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* FPGA July 28 release for REV01
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Pin Name PAD Number
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SIN (UART RXD) PAD[45]
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SOUT (UART TXD) PAD[44]
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I2C_SCL (LCD) PAD[6]
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I2C_SDA (LCD) PAD[7]
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GPIO_PIN[0] PAD[3]
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GPIO_PIN[1] PAD[11]
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GPIO_PIN[2] PAD[19]
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GPIO_PIN[3] PAD[43]
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GPIO_PIN[4] PAD[8]
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GPIO_PIN[5] PAD[41]
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GPIO_PIN[6] PAD[9]
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GPIO_PIN[7] PAD[13]
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GPIO_PIN[8] PAD[10]
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GPIO_PIN[9] PAD[17]
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GPIO_PIN[10] PAD[18]
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GPIO_PIN[11] PAD[23]
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GPIO_PIN[12] PAD[20]
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GPIO_PIN[13] PAD[21]
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GPIO_PIN[14] PAD[22]
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GPIO_PIN[15] PAD[16]
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GPIO_PIN[16] PAD[26]
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GPIO_PIN[17] PAD[27]
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GPIO_PIN[18] PAD[42]
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GPIO_PIN[19] PAD[12]
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GPIO_PIN[20] PAD[40]
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GPIO_PIN[21] PAD[2]
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I2C_SCL_SEN (HRM) PAD[29]
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I2C_SDA_SEN (HRM) PAD[28]
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CLK_4MHZ_IN PAD[30]
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CLK_1MHZ_OUT PAD[31]
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*/
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// REV00 // REV01
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#define FB_GPIO_0 0 // PAD3 // PAD[3]
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#define FB_GPIO_1 1 // PAD6 // PAD[11]
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#define FB_GPIO_2 2 // PAD8 // PAD[19]
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#define FB_GPIO_3 3 // PAD9 // PAD[43]
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#define FB_GPIO_4 4 // PAD10 // PAD[8]
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#define FB_GPIO_5 5 // PAD11 // PAD[41]
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#define FB_GPIO_6 6 // PAD12 // PAD[9]
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#define FB_GPIO_7 7 // PAD13 // PAD[13]
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#define FB_GPIO_8 8 // PAD23 // PAD[10]
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#define FB_GPIO_9 9 // PAD17 // PAD[17]
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#define FB_GPIO_10 10 // PAD18 // PAD[18]
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#define FB_GPIO_11 11 // PAD19 // PAD[23]
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#define FB_GPIO_12 12 // PAD20 // PAD[20]
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#define FB_GPIO_13 13 // PAD21 // PAD[21]
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#define FB_GPIO_14 14 // PAD22 // PAD[22]
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#define FB_GPIO_15 15 // PAD16 // PAD[16]
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#define FB_GPIO_16 16 // PAD26 // PAD[26]
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#define FB_GPIO_17 17 // PAD27 // PAD[27]
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#define FB_GPIO_18 18 // SFBIO[10] // PAD[42]
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#define FB_GPIO_19 19 // SFBIO[11] // PAD[12]
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#define FB_GPIO_20 20 // PAD7 // PAD[40]
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#define FB_GPIO_21 21 // PAD2 // PAD[2]
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/*! \fn HAL_StatusTypeDef HAL_FB_GPIO_Read(uint8_t ucGpioIndex, uint8_t *ucGpioVal)
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\brief fpga GPIO read function to read pad status. Before using this function
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given pad needs to be initalized.
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\param ucGpioIndex - GPIO index that needs to be read.
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\param *ucGpioVal - GPIO status read, return value pointer.
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*/
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HAL_StatusTypeDef HAL_FB_GPIO_Read(uint8_t ucGpioIndex, uint8_t *ucGpioVal);
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/*! \fn HAL_StatusTypeDef HAL_FB_GPIO_Write(uint8_t ucGpioIndex, uint8_t ucGpioVal)
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\brief fpga GPIO write function to read pad status. Before using this function
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given pad needs to be initalized.
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\param ucGpioIndex - GPIO index that needs to be read.
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\param ucGpioVal - GPIO status that nees to be written.
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*/
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HAL_StatusTypeDef HAL_FB_GPIO_Write(uint8_t ucGpioIndex, uint8_t ucGpioVal);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __EOSS3_HAL_FPGA_GPIO_H */
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