516 lines
20 KiB
ArmAsm
516 lines
20 KiB
ArmAsm
;/******************************************************************************
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; * @file startup_M480.s
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; * @version V1.00
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; * @brief CMSIS Cortex-M4 Core Device Startup File for M480
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; *
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; * SPDX-License-Identifier: Apache-2.0
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; * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
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;*****************************************************************************/
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;/*
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;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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;*/
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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IF :LNOT: :DEF: Stack_Size
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Stack_Size EQU 0x00000800
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ENDIF
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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IF :LNOT: :DEF: Heap_Size
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Heap_Size EQU 0x00000100
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ENDIF
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD BOD_IRQHandler ; 0: Brown Out detection
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DCD IRC_IRQHandler ; 1: Internal RC
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DCD PWRWU_IRQHandler ; 2: Power down wake up
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DCD RAMPE_IRQHandler ; 3: RAM parity error
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DCD CKFAIL_IRQHandler ; 4: Clock detection fail
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DCD Default_Handler ; 5: Reserved
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DCD RTC_IRQHandler ; 6: Real Time Clock
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DCD TAMPER_IRQHandler ; 7: Tamper detection
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DCD WDT_IRQHandler ; 8: Watchdog timer
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DCD WWDT_IRQHandler ; 9: Window watchdog timer
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DCD EINT0_IRQHandler ; 10: External Input 0
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DCD EINT1_IRQHandler ; 11: External Input 1
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DCD EINT2_IRQHandler ; 12: External Input 2
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DCD EINT3_IRQHandler ; 13: External Input 3
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DCD EINT4_IRQHandler ; 14: External Input 4
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DCD EINT5_IRQHandler ; 15: External Input 5
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DCD GPA_IRQHandler ; 16: GPIO Port A
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DCD GPB_IRQHandler ; 17: GPIO Port B
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DCD GPC_IRQHandler ; 18: GPIO Port C
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DCD GPD_IRQHandler ; 19: GPIO Port D
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DCD GPE_IRQHandler ; 20: GPIO Port E
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DCD GPF_IRQHandler ; 21: GPIO Port F
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DCD QSPI0_IRQHandler ; 22: QSPI0
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DCD SPI0_IRQHandler ; 23: SPI0
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DCD BRAKE0_IRQHandler ; 24:
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DCD EPWM0P0_IRQHandler ; 25:
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DCD EPWM0P1_IRQHandler ; 26:
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DCD EPWM0P2_IRQHandler ; 27:
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DCD BRAKE1_IRQHandler ; 28:
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DCD EPWM1P0_IRQHandler ; 29:
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DCD EPWM1P1_IRQHandler ; 30:
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DCD EPWM1P2_IRQHandler ; 31:
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DCD TMR0_IRQHandler ; 32: Timer 0
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DCD TMR1_IRQHandler ; 33: Timer 1
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DCD TMR2_IRQHandler ; 34: Timer 2
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DCD TMR3_IRQHandler ; 35: Timer 3
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DCD UART0_IRQHandler ; 36: UART0
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DCD UART1_IRQHandler ; 37: UART1
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DCD I2C0_IRQHandler ; 38: I2C0
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DCD I2C1_IRQHandler ; 39: I2C1
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DCD PDMA_IRQHandler ; 40: Peripheral DMA
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DCD DAC_IRQHandler ; 41: DAC
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DCD EADC00_IRQHandler ; 42: EADC0 interrupt source 0
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DCD EADC01_IRQHandler ; 43: EADC0 interrupt source 1
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DCD ACMP01_IRQHandler ; 44: ACMP0 and ACMP1
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DCD Default_Handler ; 45: Reserved
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DCD EADC02_IRQHandler ; 46: EADC0 interrupt source 2
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DCD EADC03_IRQHandler ; 47: EADC0 interrupt source 3
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DCD UART2_IRQHandler ; 48: UART2
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DCD UART3_IRQHandler ; 49: UART3
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DCD QSPI1_IRQHandler ; 50: QSPI1
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DCD SPI1_IRQHandler ; 51: SPI1
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DCD SPI2_IRQHandler ; 52: SPI2
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DCD USBD_IRQHandler ; 53: USB device
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DCD OHCI_IRQHandler ; 54: OHCI
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DCD USBOTG_IRQHandler ; 55: USB OTG
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DCD CAN0_IRQHandler ; 56: CAN0
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DCD CAN1_IRQHandler ; 57: CAN1
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DCD SC0_IRQHandler ; 58:
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DCD SC1_IRQHandler ; 59:
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DCD SC2_IRQHandler ; 60:
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DCD Default_Handler ; 61:
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DCD SPI3_IRQHandler ; 62: SPI3
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DCD Default_Handler ; 63:
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DCD SDH0_IRQHandler ; 64: SDH0
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DCD USBD20_IRQHandler ; 65: USBD20
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DCD EMAC_TX_IRQHandler ; 66: EMAC_TX
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DCD EMAC_RX_IRQHandler ; 67: EMAX_RX
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DCD I2S0_IRQHandler ; 68: I2S0
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DCD Default_Handler ; 69: ToDo: Add description to this Interrupt
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DCD OPA0_IRQHandler ; 70: OPA0
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DCD CRYPTO_IRQHandler ; 71: CRYPTO
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DCD GPG_IRQHandler ; 72:
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DCD EINT6_IRQHandler ; 73:
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DCD UART4_IRQHandler ; 74: UART4
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DCD UART5_IRQHandler ; 75: UART5
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DCD USCI0_IRQHandler ; 76: USCI0
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DCD USCI1_IRQHandler ; 77: USCI1
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DCD BPWM0_IRQHandler ; 78: BPWM0
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DCD BPWM1_IRQHandler ; 79: BPWM1
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DCD SPIM_IRQHandler ; 80: SPIM
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DCD CCAP_IRQHandler ; 81: CCAP
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DCD I2C2_IRQHandler ; 82: I2C2
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DCD Default_Handler ; 83:
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DCD QEI0_IRQHandler ; 84: QEI0
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DCD QEI1_IRQHandler ; 85: QEI1
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DCD ECAP0_IRQHandler ; 86: ECAP0
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DCD ECAP1_IRQHandler ; 87: ECAP1
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DCD GPH_IRQHandler ; 88:
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DCD EINT7_IRQHandler ; 89:
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DCD SDH1_IRQHandler ; 90: SDH1
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DCD Default_Handler ; 91:
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DCD EHCI_IRQHandler ; 92: EHCI
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DCD USBOTG20_IRQHandler ; 93:
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DCD Default_Handler ; 94:
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DCD Default_Handler ; 95:
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DCD Default_Handler ; 96:
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DCD Default_Handler ; 97:
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DCD Default_Handler ; 98:
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DCD Default_Handler ; 99:
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DCD Default_Handler ; 100:
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DCD TRNG_IRQHandler ; 101: TRNG
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DCD UART6_IRQHandler ; 102: UART6
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DCD UART7_IRQHandler ; 103: UART7
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DCD EADC10_IRQHandler ; 104: EADC1 interrupt source 0
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DCD EADC11_IRQHandler ; 105: EADC1 interrupt source 1
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DCD EADC12_IRQHandler ; 106: EADC1 interrupt source 2
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DCD EADC13_IRQHandler ; 107: EADC1 interrupt source 3
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DCD CAN2_IRQHandler ; 108: CAN2
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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; Unlock Register
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LDR R0, =0x40000100
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LDR R1, =0x59
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STR R1, [R0]
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LDR R1, =0x16
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STR R1, [R0]
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LDR R1, =0x88
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STR R1, [R0]
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IF :LNOT: :DEF: ENABLE_SPIM_CACHE
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LDR R0, =0x40000200 ; R0 = Clock Controller Register Base Address
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LDR R1, [R0,#0x4] ; R1 = 0x40000204 (AHBCLK)
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ORR R1, R1, #0x4000
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STR R1, [R0,#0x4] ; CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk;
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LDR R0, =0x40007000 ; R0 = SPIM Register Base Address
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LDR R1, [R0,#4] ; R1 = SPIM->CTL1
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ORR R1, R1,#2 ; R1 |= SPIM_CTL1_CACHEOFF_Msk
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STR R1, [R0,#4] ; _SPIM_DISABLE_CACHE()
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LDR R1, [R0,#4] ; R1 = SPIM->CTL1
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ORR R1, R1, #4 ; R1 |= SPIM_CTL1_CCMEN_Msk
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STR R1, [R0,#4] ; _SPIM_ENABLE_CCM()
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ENDIF
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LDR R0, =SystemInit
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BLX R0
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; Init POR
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; LDR R2, =0x40000024
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; LDR R1, =0x00005AA5
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; STR R1, [R2]
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; Lock
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LDR R0, =0x40000100
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LDR R1, =0
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STR R1, [R0]
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler\
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PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler\
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PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT BOD_IRQHandler [WEAK]
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EXPORT IRC_IRQHandler [WEAK]
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EXPORT PWRWU_IRQHandler [WEAK]
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EXPORT RAMPE_IRQHandler [WEAK]
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EXPORT CKFAIL_IRQHandler [WEAK]
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EXPORT RTC_IRQHandler [WEAK]
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EXPORT TAMPER_IRQHandler [WEAK]
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EXPORT WDT_IRQHandler [WEAK]
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EXPORT WWDT_IRQHandler [WEAK]
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EXPORT EINT0_IRQHandler [WEAK]
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EXPORT EINT1_IRQHandler [WEAK]
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EXPORT EINT2_IRQHandler [WEAK]
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EXPORT EINT3_IRQHandler [WEAK]
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EXPORT EINT4_IRQHandler [WEAK]
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EXPORT EINT5_IRQHandler [WEAK]
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EXPORT GPA_IRQHandler [WEAK]
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EXPORT GPB_IRQHandler [WEAK]
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EXPORT GPC_IRQHandler [WEAK]
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EXPORT GPD_IRQHandler [WEAK]
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EXPORT GPE_IRQHandler [WEAK]
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EXPORT GPF_IRQHandler [WEAK]
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EXPORT QSPI0_IRQHandler [WEAK]
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EXPORT SPI0_IRQHandler [WEAK]
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EXPORT BRAKE0_IRQHandler [WEAK]
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EXPORT EPWM0P0_IRQHandler [WEAK]
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EXPORT EPWM0P1_IRQHandler [WEAK]
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EXPORT EPWM0P2_IRQHandler [WEAK]
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EXPORT BRAKE1_IRQHandler [WEAK]
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EXPORT EPWM1P0_IRQHandler [WEAK]
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EXPORT EPWM1P1_IRQHandler [WEAK]
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EXPORT EPWM1P2_IRQHandler [WEAK]
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EXPORT TMR0_IRQHandler [WEAK]
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EXPORT TMR1_IRQHandler [WEAK]
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EXPORT TMR2_IRQHandler [WEAK]
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EXPORT TMR3_IRQHandler [WEAK]
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EXPORT UART0_IRQHandler [WEAK]
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EXPORT UART1_IRQHandler [WEAK]
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EXPORT I2C0_IRQHandler [WEAK]
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EXPORT I2C1_IRQHandler [WEAK]
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EXPORT PDMA_IRQHandler [WEAK]
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EXPORT DAC_IRQHandler [WEAK]
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EXPORT EADC00_IRQHandler [WEAK]
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EXPORT EADC01_IRQHandler [WEAK]
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EXPORT ACMP01_IRQHandler [WEAK]
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EXPORT EADC02_IRQHandler [WEAK]
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EXPORT EADC03_IRQHandler [WEAK]
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EXPORT UART2_IRQHandler [WEAK]
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EXPORT UART3_IRQHandler [WEAK]
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EXPORT QSPI1_IRQHandler [WEAK]
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EXPORT SPI1_IRQHandler [WEAK]
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EXPORT SPI2_IRQHandler [WEAK]
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EXPORT USBD_IRQHandler [WEAK]
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EXPORT OHCI_IRQHandler [WEAK]
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EXPORT USBOTG_IRQHandler [WEAK]
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EXPORT CAN0_IRQHandler [WEAK]
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EXPORT CAN1_IRQHandler [WEAK]
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EXPORT SC0_IRQHandler [WEAK]
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EXPORT SC1_IRQHandler [WEAK]
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EXPORT SC2_IRQHandler [WEAK]
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EXPORT SPI3_IRQHandler [WEAK]
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EXPORT SDH0_IRQHandler [WEAK]
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EXPORT USBD20_IRQHandler [WEAK]
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EXPORT EMAC_TX_IRQHandler [WEAK]
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EXPORT EMAC_RX_IRQHandler [WEAK]
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EXPORT I2S0_IRQHandler [WEAK]
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EXPORT OPA0_IRQHandler [WEAK]
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EXPORT CRYPTO_IRQHandler [WEAK]
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EXPORT GPG_IRQHandler [WEAK]
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EXPORT EINT6_IRQHandler [WEAK]
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EXPORT UART4_IRQHandler [WEAK]
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EXPORT UART5_IRQHandler [WEAK]
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EXPORT USCI0_IRQHandler [WEAK]
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EXPORT USCI1_IRQHandler [WEAK]
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EXPORT BPWM0_IRQHandler [WEAK]
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EXPORT BPWM1_IRQHandler [WEAK]
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EXPORT SPIM_IRQHandler [WEAK]
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EXPORT CCAP_IRQHandler [WEAK]
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EXPORT I2C2_IRQHandler [WEAK]
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EXPORT QEI0_IRQHandler [WEAK]
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EXPORT QEI1_IRQHandler [WEAK]
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EXPORT ECAP0_IRQHandler [WEAK]
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EXPORT ECAP1_IRQHandler [WEAK]
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EXPORT GPH_IRQHandler [WEAK]
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EXPORT EINT7_IRQHandler [WEAK]
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EXPORT SDH1_IRQHandler [WEAK]
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EXPORT EHCI_IRQHandler [WEAK]
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EXPORT USBOTG20_IRQHandler [WEAK]
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EXPORT TRNG_IRQHandler [WEAK]
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EXPORT UART6_IRQHandler [WEAK]
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EXPORT UART7_IRQHandler [WEAK]
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EXPORT EADC10_IRQHandler [WEAK]
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EXPORT EADC11_IRQHandler [WEAK]
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EXPORT EADC12_IRQHandler [WEAK]
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EXPORT EADC13_IRQHandler [WEAK]
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EXPORT CAN2_IRQHandler [WEAK]
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Default__IRQHandler
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BOD_IRQHandler
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IRC_IRQHandler
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PWRWU_IRQHandler
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RAMPE_IRQHandler
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CKFAIL_IRQHandler
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RTC_IRQHandler
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TAMPER_IRQHandler
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WDT_IRQHandler
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WWDT_IRQHandler
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EINT0_IRQHandler
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EINT1_IRQHandler
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EINT2_IRQHandler
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EINT3_IRQHandler
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EINT4_IRQHandler
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EINT5_IRQHandler
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GPA_IRQHandler
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GPB_IRQHandler
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GPC_IRQHandler
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GPD_IRQHandler
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GPE_IRQHandler
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GPF_IRQHandler
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QSPI0_IRQHandler
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SPI0_IRQHandler
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BRAKE0_IRQHandler
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EPWM0P0_IRQHandler
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EPWM0P1_IRQHandler
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EPWM0P2_IRQHandler
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BRAKE1_IRQHandler
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EPWM1P0_IRQHandler
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EPWM1P1_IRQHandler
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EPWM1P2_IRQHandler
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TMR0_IRQHandler
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TMR1_IRQHandler
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TMR2_IRQHandler
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TMR3_IRQHandler
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UART0_IRQHandler
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UART1_IRQHandler
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I2C0_IRQHandler
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I2C1_IRQHandler
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PDMA_IRQHandler
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DAC_IRQHandler
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EADC00_IRQHandler
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EADC01_IRQHandler
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ACMP01_IRQHandler
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EADC02_IRQHandler
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EADC03_IRQHandler
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UART2_IRQHandler
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UART3_IRQHandler
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QSPI1_IRQHandler
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SPI1_IRQHandler
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SPI2_IRQHandler
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USBD_IRQHandler
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OHCI_IRQHandler
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USBOTG_IRQHandler
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CAN0_IRQHandler
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CAN1_IRQHandler
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SC0_IRQHandler
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SC1_IRQHandler
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SC2_IRQHandler
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SPI3_IRQHandler
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SDH0_IRQHandler
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USBD20_IRQHandler
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EMAC_TX_IRQHandler
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EMAC_RX_IRQHandler
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I2S0_IRQHandler
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OPA0_IRQHandler
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CRYPTO_IRQHandler
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GPG_IRQHandler
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EINT6_IRQHandler
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UART4_IRQHandler
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UART5_IRQHandler
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USCI0_IRQHandler
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USCI1_IRQHandler
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BPWM0_IRQHandler
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BPWM1_IRQHandler
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SPIM_IRQHandler
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CCAP_IRQHandler
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I2C2_IRQHandler
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QEI0_IRQHandler
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QEI1_IRQHandler
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ECAP0_IRQHandler
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ECAP1_IRQHandler
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GPH_IRQHandler
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EINT7_IRQHandler
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SDH1_IRQHandler
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EHCI_IRQHandler
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USBOTG20_IRQHandler
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TRNG_IRQHandler
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UART6_IRQHandler
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UART7_IRQHandler
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EADC10_IRQHandler
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EADC11_IRQHandler
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EADC12_IRQHandler
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EADC13_IRQHandler
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CAN2_IRQHandler
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B .
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ENDP
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ALIGN
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; User Initial Stack & Heap
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap PROC
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LDR R0, = Heap_Mem
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LDR R1, =(Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ENDP
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ALIGN
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ENDIF
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END
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;/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
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