184 lines
12 KiB
C
184 lines
12 KiB
C
/**************************************************************************//**
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* @file wdt_reg.h
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* @version V1.00
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* @brief WDT register definition header file
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*
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* SPDX-License-Identifier: Apache-2.0
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* @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __WDT_REG_H__
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#define __WDT_REG_H__
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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/**
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@addtogroup REGISTER Control Register
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@{
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*/
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/**
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@addtogroup WDT Watch Dog Timer Controller(WDT)
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Memory Mapped Structure for WDT Controller
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@{ */
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typedef struct
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{
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/**
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* @var WDT_T::CTL
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* Offset: 0x00 WDT Control Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |RSTCNT |Reset WDT Up Counter (Write Protect)
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* | | |0 = No effect.
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* | | |1 = Reset the internal 18-bit WDT up counter value.
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* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
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* | | |Note2: This bit will be automatically cleared by hardware.
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* |[1] |RSTEN |WDT Time-out Reset Enable Control (Write Protect)
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* | | |Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.
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* | | |0 = WDT time-out reset function Disabled.
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* | | |1 = WDT time-out reset function Enabled.
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* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
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* |[2] |RSTF |WDT Time-out Reset Flag
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* | | |This bit indicates the system has been reset by WDT time-out reset or not.
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* | | |0 = WDT time-out reset did not occur.
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* | | |1 = WDT time-out reset occurred.
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* | | |Note: This bit is cleared by writing 1 to it.
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* |[3] |IF |WDT Time-out Interrupt Flag
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* | | |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval
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* | | |0 = WDT time-out interrupt did not occur.
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* | | |1 = WDT time-out interrupt occurred.
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* | | |Note: This bit is cleared by writing 1 to it.
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* |[4] |WKEN |WDT Time-out Wake-up Function Control (Write Protect)
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* | | |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
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* | | |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated.
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* | | |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated.
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* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
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* | | |Note2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz internal low speed RC oscillator (LIRC) or LXT.
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* |[5] |WKF |WDT Time-out Wake-up Flag (Write Protect)
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* | | |This bit indicates the interrupt wake-up flag status of WDT
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* | | |0 = WDT does not cause chip wake-up.
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* | | |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated.
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* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
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* | | |Note2: This bit is cleared by writing 1 to it.
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* |[6] |INTEN |WDT Time-out Interrupt Enable Control (Write Protect)
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* | | |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.
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* | | |0 = WDT time-out interrupt Disabled.
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* | | |1 = WDT time-out interrupt Enabled.
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* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
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* |[7] |WDTEN |WDT Enable Control (Write Protect)
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* | | |0 = WDT Disabled (This action will reset the internal up counter value).
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* | | |1 = WDT Enabled.
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* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
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* | | |Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configure to 111, this bit is forced as 1 and user cannot change this bit to 0.
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* |[10:8] |TOUTSEL |WDT Time-out Interval Selection (Write Protect)
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* | | |These three bits select the time-out interval period for the WDT.
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* | | |000 = 24 * WDT_CLK.
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* | | |001 = 26 * WDT_CLK.
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* | | |010 = 28 * WDT_CLK.
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* | | |011 = 210 * WDT_CLK.
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* | | |100 = 212 * WDT_CLK.
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* | | |101 = 214 * WDT_CLK.
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* | | |110 = 216 * WDT_CLK.
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* | | |111 = 218 * WDT_CLK.
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* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
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* |[30] |SYNC |WDT Enable Control SYNC Flag Indicator (Read Only)
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* | | |If user execute enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not.
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* | | |0 = Set WDTEN bit is completed.
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* | | |1 = Set WDTEN bit is synchronizing and not become active yet..
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* | | |Note: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active.
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* |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect)
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* | | |0 = ICE debug mode acknowledgement affects WDT counting.
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* | | |WDT up counter will be held while CPU is held by ICE.
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* | | |1 = ICE debug mode acknowledgement Disabled.
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* | | |WDT up counter will keep going no matter CPU is held by ICE or not.
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* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
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* @var WDT_T::ALTCTL
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* Offset: 0x04 WDT Alternative Control Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[1:0] |RSTDSEL |WDT Reset Delay Selection (Write Protect)
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* | | |When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened
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* | | |User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.
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* | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK.
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* | | |01 = WDT Reset Delay Period is 130 * WDT_CLK.
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* | | |10 = WDT Reset Delay Period is 18 * WDT_CLK.
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* | | |11 = WDT Reset Delay Period is 3 * WDT_CLK.
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* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
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* | | |Note2: This register will be reset to 0 if WDT time-out reset happened.
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* @var WDT_T::RSTCNT
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* Offset: 0x08 WDT Reset Counter Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[31:0] |RSTCNT |WDT Reset Counter Register
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* | | |Writing 0x00005AA5 to this field will reset the internal 18-bit WDT up counter value to 0.
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* | | |Note: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active.
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* | | |Note: RSTCNT (WDT_CTL[0]) bit is a write protected bit
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* | | |RSTCNT (WDT_RSTCNT[31:0]) bits are not write protected.
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*/
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__IO uint32_t CTL; /*!< [0x0000] WDT Control Register */
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__IO uint32_t ALTCTL; /*!< [0x0004] WDT Alternative Control Register */
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__O uint32_t RSTCNT; /*!< [0x0008] WDT Reset Counter Register */
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} WDT_T;
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/**
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@addtogroup WDT_CONST WDT Bit Field Definition
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Constant Definitions for WDT Controller
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@{ */
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#define WDT_CTL_RSTCNT_Pos (0) /*!< WDT_T::CTL: RSTCNT Position */
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#define WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos) /*!< WDT_T::CTL: RSTCNT Mask */
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#define WDT_CTL_RSTEN_Pos (1) /*!< WDT_T::CTL: RSTEN Position */
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#define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT_T::CTL: RSTEN Mask */
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#define WDT_CTL_RSTF_Pos (2) /*!< WDT_T::CTL: RSTF Position */
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#define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT_T::CTL: RSTF Mask */
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#define WDT_CTL_IF_Pos (3) /*!< WDT_T::CTL: IF Position */
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#define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT_T::CTL: IF Mask */
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#define WDT_CTL_WKEN_Pos (4) /*!< WDT_T::CTL: WKEN Position */
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#define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT_T::CTL: WKEN Mask */
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#define WDT_CTL_WKF_Pos (5) /*!< WDT_T::CTL: WKF Position */
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#define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT_T::CTL: WKF Mask */
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#define WDT_CTL_INTEN_Pos (6) /*!< WDT_T::CTL: INTEN Position */
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#define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT_T::CTL: INTEN Mask */
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#define WDT_CTL_WDTEN_Pos (7) /*!< WDT_T::CTL: WDTEN Position */
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#define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT_T::CTL: WDTEN Mask */
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#define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT_T::CTL: TOUTSEL Position */
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#define WDT_CTL_TOUTSEL_Msk (0x7ul << WDT_CTL_TOUTSEL_Pos) /*!< WDT_T::CTL: TOUTSEL Mask */
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#define WDT_CTL_SYNC_Pos (30) /*!< WDT_T::CTL: SYNC Position */
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#define WDT_CTL_SYNC_Msk (0x1ul << WDT_CTL_SYNC_Pos) /*!< WDT_T::CTL: SYNC Mask */
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#define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT_T::CTL: ICEDEBUG Position */
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#define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT_T::CTL: ICEDEBUG Mask */
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#define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT_T::ALTCTL: RSTDSEL Position */
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#define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT_T::ALTCTL: RSTDSEL Mask */
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#define WDT_RSTCNT_RSTCNT_Pos (0) /*!< WDT_T::RSTCNT: RSTCNT Position */
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#define WDT_RSTCNT_RSTCNT_Msk (0xfffffffful << WDT_RSTCNT_RSTCNT_Pos) /*!< WDT_T::RSTCNT: RSTCNT Mask */
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/**@}*/ /* WDT_CONST */
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/**@}*/ /* end of WDT register group */
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/**@}*/ /* end of REGISTER group */
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#if defined ( __CC_ARM )
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#pragma no_anon_unions
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#endif
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#endif /* __WDT_REG_H__ */
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