497 lines
34 KiB
C
497 lines
34 KiB
C
/**************************************************************************//**
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* @file ccap_reg.h
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* @version V1.00
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* @brief CCAP register definition header file
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*
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* SPDX-License-Identifier: Apache-2.0
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* @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __CCAP_REG_H__
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#define __CCAP_REG_H__
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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/**
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@addtogroup REGISTER Control Register
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@{
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*/
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/**
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@addtogroup CCAP Camera Capture Interface Controller (CCAP)
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Memory Mapped Structure for CCAP Controller
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@{ */
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typedef struct {
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/**
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* @var CCAP_T::CTL
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* Offset: 0x00 Camera Capture Interface Control Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |CCAPEN |Camera Capture Interface Enable
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* | | |0 = Camera Capture Interface Disabled.
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* | | |1 = Camera Capture Interface Enabled.
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* |[3] |ADDRSW |Packet Buffer Address Switch
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* | | |0 = Packet buffer address switch Disabled.
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* | | |1 = Packet buffer address switch Enabled.
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* |[6] |PKTEN |Packet Output Enable
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* | | |0 = Packet output Disabled.
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* | | |1 = Packet output Enabled.
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* |[7] |MONO |Monochrome CMOS Sensor Select
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* | | |0 = Color CMOS Sensor.
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* | | |1 = Monochrome CMOS Sensor. The U/V components are ignored when the MONO is enabled.
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* |[16] |SHUTTER |Image Capture Interface Automatically Disable The Capture Interface After A Frame Had Been Captured
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* | | |0 = Shutter Disabled.
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* | | |1 = Shutter Enabled.
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* |[20] |UPDATE |Update Register At New Frame
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* | | |0 = Update register at new frame Disabled.
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* | | |1 = Update register at new frame Enabled (Auto clear to 0 when register updated).
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* |[24] |VPRST |Capture Interface Reset
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* | | |0 = Capture interface reset Disabled.
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* | | |1 = Capture interface reset Enabled.
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* @var CCAP_T::PAR
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* Offset: 0x04 Camera Capture Interface Parameter Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |INFMT |Sensor Input Data Format
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* | | |0 = YCbCr422.
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* | | |1 = RGB565.
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* |[1] |SENTYPE |Sensor Input Type
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* | | |0 = CCIR601.
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* | | |1 = CCIR656, VSync & Hsync embedded in the data signal.
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* |[2:3] |INDATORD |Sensor Input Data Order
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* | | |If INFMT = 0 (YCbCr),.
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* | | | Byte 0 1 2 3
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* | | |00 = Y0 U0 Y1 V0.
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* | | |01 = Y0 V0 Y1 U0.
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* | | |10 = U0 Y0 V0 Y1.
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* | | |11 = V0 Y0 U0 Y1.
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* | | |If INFMT = 1 (RGB565),.
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* | | |00 = Byte0[R[4:0] G[5:3]] Byte1[G[2:0] B[4:0]]
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* | | |01 = Byte0[B[4:0] G[5:3]] Byte1[G[2:0] R[4:0]]
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* | | |10 = Byte0[G[2:0] B[4:0]] Byte1[R[4:0] G[5:3]]
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* | | |11 = Byte0[G[2:0] R[4:0]] Byte1[B[4:0] G[5:3]]
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* |[4:5] |OUTFMT |Image Data Format Output To System Memory
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* | | |00 = YCbCr422.
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* | | |01 = Only output Y.
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* | | |10 = RGB555.
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* | | |11 = RGB565.
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* |[6] |RANGE |Scale Input YUV CCIR601 Color Range To Full Range
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* | | |0 = default.
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* | | |1 = Scale to full range.
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* |[8] |PCLKP |Sensor Pixel Clock Polarity
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* | | |0 = Input video data and signals are latched by falling edge of Pixel Clock.
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* | | |1 = Input video data and signals are latched by rising edge of Pixel Clock.
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* |[9] |HSP |Sensor Hsync Polarity
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* | | |0 = Sync Low.
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* | | |1 = Sync High.
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* |[10] |VSP |Sensor Vsync Polarity
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* | | |0 = Sync Low.
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* | | |1 = Sync High.
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* |[18] |FBB |Field By Blank
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* | | |Hardware will tag field0 or field1 by vertical blanking instead of FIELD flag in CCIR-656 mode.
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* | | |0 = Field by blank Disabled.
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* | | |1 = Field by blank Enabled.
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* @var CCAP_T::INT
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* Offset: 0x08 Camera Capture Interface Interrupt Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |VINTF |Video Frame End Interrupt
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* | | |If this bit shows 1, receiving a frame completed.
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* | | |Write 1 to clear it.
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* |[1] |MEINTF |Bus Master Transfer Error Interrupt
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* | | |If this bit shows 1, Transfer Error occurred. Write 1 to clear it.
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* |[3] |ADDRMINTF |Memory Address Match Interrupt
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* | | |If this bit shows 1, Memory Address Match Interrupt occurred.
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* | | |Write 1 to clear it.
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* |[4] |MDINTF |Motion Detection Output Finish Interrupt
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* | | |If this bit shows 1, Motion Detection Output Finish Interrupt occurred.
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* | | |Write 1 to clear it.
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* |[16] |VIEN |Video Frame End Interrupt Enable
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* | | |0 = Video frame end interrupt Disabled.
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* | | |1 = Video frame end interrupt Enabled.
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* |[17] |MEIEN |System Memory Error Interrupt Enable
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* | | |0 = System memory error interrupt Disabled.
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* | | |1 = System memory error interrupt Enabled.
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* |[19] |ADDRMIEN |Address Match Interrupt Enable
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* | | |0 = Address match interrupt Disabled.
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* | | |1 = Address match interrupt Enabled.
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* @var CCAP_T::POSTERIZE
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* Offset: 0x0C YUV Component Posterizing Factor Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0:7] |VCOMP |V Component Posterizing Factor
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* | | |Final_V_Out = Original_V[7:0] & V_Posterizing_Factor.
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* |[8:15] |UCOMP |U Component Posterizing Factor
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* | | |Final_U_Out = Original_U[7:0] & U_Posterizing_Factor.
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* |[16:23] |YCOMP |Y Component Posterizing Factor
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* | | |Final_Y_Out = Original_Y[7:0] & Y_Posterizing_Factor.
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* @var CCAP_T::MD
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* Offset: 0x10 Motion Detection Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |MDEN |Motion Detection Enable
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* | | |0 = CCAP_MD Disabled.
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* | | |1 = CCAP_MD Enabled.
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* |[8] |MDBS |Motion Detection Block Size
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* | | |0 = 16x16.
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* | | |1 = 8x8.
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* |[9] |MDSM |Motion Detection Save Mode
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* | | |0 = 1 bit DIFF + 7 bit Y Differential.
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* | | |1 = 1 bit DIFF only.
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* |[10:11] |MDDF |Motion Detection Detect Frequency
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* | | |00 = Each frame.
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* | | |01 = Every 2 frame.
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* | | |10 = Every 3 frame.
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* | | |11 = Every 4 frame.
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* |[16:20] |MDTHR |Motion Detection Differential Threshold
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* @var CCAP_T::MDADDR
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* Offset: 0x14 Motion Detection Output Address Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0:31] |MDADDR |Motion Detection Output Address Register (Word Alignment)
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* @var CCAP_T::MDYADDR
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* Offset: 0x18 Motion Detection Temp Y Output Address Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0:31] |MDYADDR |Motion Detection Temp Y Output Address Register (Word Alignment)
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* @var CCAP_T::SEPIA
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* Offset: 0x1C Sepia Effect Control Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0:7] |VCOMP |Define the constant V component while Sepia color effect is turned on.
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* |[8:15] |UCOMP |Define the constant U component while Sepia color effect is turned on.
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* @var CCAP_T::CWSP
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* Offset: 0x20 Cropping Window Starting Address Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0:11] |CWSADDRH |Cropping Window Horizontal Starting Address
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* |[16:26] |CWSADDRV |Cropping Window Vertical Starting Address
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* @var CCAP_T::CWS
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* Offset: 0x24 Cropping Window Size Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0:11] |CIWW |Cropping Image Window Width
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* |[16:26] |CIWH |Cropping Image Window Height
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* @var CCAP_T::PKTSL
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* Offset: 0x28 Packet Scaling Vertical/Horizontal Factor Register (LSB)
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0:7] |PKTSHML |Packet Scaling Horizontal Factor M (Lower 8-Bit)
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* | | |Specifies the lower 8-bit of denominator part (M) of the horizontal scaling factor.
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* | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSHMH) to form a 16-bit denominator (M) of vertical factor.
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* | | |The output image width will be equal to the image width * N/M.
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* | | |Note: The value of N must be equal to or less than M.
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* |[8:15] |PKTSHNL |Packet Scaling Horizontal Factor N (Lower 8-Bit)
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* | | |Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor.
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* | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSHNH) to form a 16-bit numerator of horizontal factor.
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* |[16:23] |PKTSVML |Packet Scaling Vertical Factor M (Lower 8-Bit)
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* | | |Specify the lower 8-bit of denominator part (M) of the vertical scaling factor.
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* | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSVMH) to form a 16-bit denominator (M) of vertical factor.
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* | | |The output image width will be equal to the image height * N/M.
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* | | |Note: The value of N must be equal to or less than M.
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* |[24:31] |PKTSVNL |Packet Scaling Vertical Factor N (Lower 8-Bit)
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* | | |Specify the lower 8-bit of numerator part (N) of the vertical scaling factor.
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* | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSVNH) to form a 16-bit numerator of vertical factor
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* @var CCAP_T::PLNSL
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* Offset: 0x2C Planar Scaling Vertical/Horizontal Factor Register (LSB)
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0:7] |PLNSHML |Planar Scaling Horizontal Factor M (Lower 8-Bit)
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* | | |Specify the lower 8-bit of denominator part (M) of the horizontal scaling factor.
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* | | |The lower 8-bit will be cascaded with higher 8-bit (PNDSHMH) to form a 16-bit denominator (M) of vertical factor.
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* | | |The output image width will be equal to the image width * N/M.
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* | | |Note: The value of N must be equal to or less than M.
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* |[8:15] |PLNSHNL |Planar Scaling Horizontal Factor N (Lower 8-Bit)
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* | | |Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor.
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* | | |The lower 8-bit will be cascaded with higher 8-bit (PNDSHNH) to form a 16-bit numerator of horizontal factor.
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* |[16:23] |PLNSVML |Planar Scaling Vertical Factor M (Lower 8-Bit)
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* | | |Specify the lower 8-bit of denominator part (M) of the vertical scaling factor.
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* | | |The lower 8-bit will be cascaded with higher 8-bit (PNDSVMH) to form a 16-bit denominator (M) of vertical factor.
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* | | |The output image width will be equal to the image height * N/M.
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* | | |Note: The value of N must be equal to or less than M.
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* |[24:31] |PLNSVNL |Planar Scaling Vertical Factor N (Lower 8-Bit)
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* | | |Specify the lower 8-bit of numerator part (N) of the vertical scaling factor.
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* | | |The lower 8-bit will be cascaded with higher 8-bit (PNDSVNH) to form a 16-bit numerator of vertical factor.
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* @var CCAP_T::FRCTL
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* Offset: 0x30 Scaling Frame Rate Factor Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0:5] |FRM |Scaling Frame Rate Factor M
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* | | |Specify the denominator part (M) of the frame rate scaling factor.
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* | | |The output image frame rate will be equal to input image frame rate * (N/M).
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* | | |Note: The value of N must be equal to or less than M.
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* |[8:13] |FRN |Scaling Frame Rate Factor N
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* | | |Specify the denominator part (N) of the frame rate scaling factor.
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* @var CCAP_T::STRIDE
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* Offset: 0x34 Frame Output Pixel Stride Width Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0:13] |PKTSTRIDE |Packet Frame Output Pixel Stride Width
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* | | |The output pixel stride size of packet pipe.
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* |[16:29] |PLNSTRIDE |Planar Frame Output Pixel Stride Width
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* | | |The output pixel stride size of planar pipe.
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* @var CCAP_T::FIFOTH
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* Offset: 0x3C FIFO Threshold Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0:3] |PLNVFTH |Planar V FIFO Threshold
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* |[8:11] |PLNUFTH |Planar U FIFO Threshold
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* |[16:20] |PLNYFTH |Planar Y FIFO Threshold
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* |[24:28] |PKTFTH |Packet FIFO Threshold
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* |[31] |OVF |FIFO Overflow Flag
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* @var CCAP_T::CMPADDR
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* Offset: 0x40 Compare Memory Base Address Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0:31] |CMPADDR |Compare Memory Base Address
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* | | |Word aligns address; ignore the bits [1:0].
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* @var CCAP_T::LUMA_Y1_THD
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* Offset: 0x44 Luminance Y8 to Y1 Threshold Value Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :-----------: | :---- |
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* |[0:8] |LUMA_Y1_THRESH |Luminance Y8 to Y1 Threshold Value
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* | | |Specify the 8-bit threshold value for the luminance Y bit-8 to the luminance Y 1-bit conversion.
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* @var CCAP_T::PKTSM
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* Offset: 0x48 Packet Scaling Vertical/Horizontal Factor Register (MSB)
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0:7] |PKTSHMH |Packet Scaling Horizontal Factor M (Higher 8-Bit)
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* | | |Specify the lower 8-bit of denominator part (M) of the horizontal scaling factor.
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* | | |Please refer to the register CCAP_PKTSL?for the detailed operation.
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* |[8:15] |PKTSHNH |Packet Scaling Horizontal Factor N (Higher 8-Bit)
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* | | |Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor.
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* | | |Please refer to the register CCAP_PKTSL for the detailed operation.
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* |[16:23] |PKTSVMH |Packet Scaling Vertical Factor M (Higher 8-Bit)
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* | | |Specify the lower 8-bit of denominator part (M) of the vertical scaling factor.
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* | | |Please refer to the register CCAP_PKTSL to check the cooperation between these two registers.
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* |[24:31] |PKTSVNH |Packet Scaling Vertical Factor N (Higher 8-Bit)
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* | | |Specify the higher 8-bit of numerator part (N) of the vertical scaling factor.
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* | | |Please refer to the register CCAP_PKTSL?to check the cooperation between these two registers.
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* @var CCAP_T::PKTBA0
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* Offset: 0x60 System Memory Packet Base Address 0 Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0:31] |BASEADDR |System Memory Packet Base Address 0
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* | | |Word aligns address; ignore the bits [1:0].
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*/
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__IO uint32_t CTL;
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__IO uint32_t PAR;
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__IO uint32_t INT;
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__IO uint32_t POSTERIZE;
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__IO uint32_t MD;
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__IO uint32_t MDADDR;
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__IO uint32_t MDYADDR;
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__IO uint32_t SEPIA;
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__IO uint32_t CWSP;
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__IO uint32_t CWS;
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__IO uint32_t PKTSL;
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__IO uint32_t PLNSL;
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__IO uint32_t FRCTL;
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__IO uint32_t STRIDE;
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/// @cond HIDDEN_SYMBOLS
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uint32_t RESERVE0[1];
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/// @endcond //HIDDEN_SYMBOLS
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__IO uint32_t FIFOTH;
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__IO uint32_t CMPADDR;
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__IO uint32_t LUMA_Y1_THD;
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__IO uint32_t PKTSM;
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/// @cond HIDDEN_SYMBOLS
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uint32_t RESERVE2[5];
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/// @endcond //HIDDEN_SYMBOLS
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__IO uint32_t PKTBA0;
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} CCAP_T;
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/**
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@addtogroup CCAP_CONST CCAP Bit Field Definition
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Constant Definitions for CCAP Controller
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@{ */
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#define CCAP_CTL_CCAPEN_Pos (0) /*!< CCAP_T::CTL: CCAPEN Position */
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#define CCAP_CTL_CCAPEN_Msk (0x1ul << CCAP_CTL_CCAPEN_Pos) /*!< CCAP_T::CTL: CCAPEN Mask */
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#define CCAP_CTL_ADDRSW_Pos (3) /*!< CCAP_T::CTL: ADDRSW Position */
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#define CCAP_CTL_ADDRSW_Msk (0x1ul << CCAP_CTL_ADDRSW_Pos) /*!< CCAP_T::CTL: ADDRSW Mask */
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#define CCAP_CTL_PLNEN_Pos (5) /*!< CCAP_T::CTL: PLNEN Position */
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#define CCAP_CTL_PLNEN_Msk (0x1ul << CCAP_CTL_PLNEN_Pos) /*!< CCAP_T::CTL: PLNEN Mask */
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#define CCAP_CTL_PKTEN_Pos (6) /*!< CCAP_T::CTL: PKTEN Position */
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#define CCAP_CTL_PKTEN_Msk (0x1ul << CCAP_CTL_PKTEN_Pos) /*!< CCAP_T::CTL: PKTEN Mask */
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#define CCAP_CTL_MONO_Pos (7) /*!< CCAP_T::CTL: MONO Position */
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#define CCAP_CTL_MONO_Msk (0x1ul << CCAP_CTL_MONO_Pos) /*!< CCAP_T::CTL: MONO Mask */
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#define CCAP_CTL_SHUTTER_Pos (16) /*!< CCAP_T::CTL: SHUTTER Position */
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#define CCAP_CTL_SHUTTER_Msk (0x1ul << CCAP_CTL_SHUTTER_Pos) /*!< CCAP_T::CTL: SHUTTER Mask */
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#define CCAP_CTL_MY4_SWAP_Pos (17) /*!< CCAP_T::CTL: MY4_SWAP Position */
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#define CCAP_CTL_MY4_SWAP_Msk (0x1ul << CCAP_CTL_MY4_SWAP_Pos) /*!< CCAP_T::CTL: MY4_SWAP Mask */
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#define CCAP_CTL_MY8_MY4_Pos (18) /*!< CCAP_T::CTL: MY8_MY4 Position */
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#define CCAP_CTL_MY8_MY4_Msk (0x1ul << CCAP_CTL_MY8_MY4_Pos) /*!< CCAP_T::CTL: MY8_MY4 Mask */
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#define CCAP_CTL_Luma_Y_One_Pos (19) /*!< CCAP_T::CTL: Luma_Y_One Position */
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#define CCAP_CTL_Luma_Y_One_Msk (0x1ul << CCAP_CTL_Luma_Y_One_Pos) /*!< CCAP_T::CTL: Luma_Y_One Mask */
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#define CCAP_CTL_UPDATE_Pos (20) /*!< CCAP_T::CTL: UPDATE Position */
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#define CCAP_CTL_UPDATE_Msk (0x1ul << CCAP_CTL_UPDATE_Pos) /*!< CCAP_T::CTL: UPDATE Mask */
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#define CCAP_CTL_VPRST_Pos (24) /*!< CCAP_T::CTL: VPRST Position */
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#define CCAP_CTL_VPRST_Msk (0x1ul << CCAP_CTL_VPRST_Pos) /*!< CCAP_T::CTL: VPRST Mask */
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#define CCAP_PAR_INFMT_Pos (0) /*!< CCAP_T::PAR: INFMT Position */
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#define CCAP_PAR_INFMT_Msk (0x1ul << CCAP_PAR_INFMT_Pos) /*!< CCAP_T::PAR: INFMT Mask */
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#define CCAP_PAR_SENTYPE_Pos (1) /*!< CCAP_T::PAR: SENTYPE Position */
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#define CCAP_PAR_SENTYPE_Msk (0x1ul << CCAP_PAR_SENTYPE_Pos) /*!< CCAP_T::PAR: SENTYPE Mask */
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#define CCAP_PAR_INDATORD_Pos (2) /*!< CCAP_T::PAR: INDATORD Position */
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#define CCAP_PAR_INDATORD_Msk (0x3ul << CCAP_PAR_INDATORD_Pos) /*!< CCAP_T::PAR: INDATORD Mask */
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#define CCAP_PAR_OUTFMT_Pos (4) /*!< CCAP_T::PAR: OUTFMT Position */
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#define CCAP_PAR_OUTFMT_Msk (0x3ul << CCAP_PAR_OUTFMT_Pos) /*!< CCAP_T::PAR: OUTFMT Mask */
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#define CCAP_PAR_RANGE_Pos (6) /*!< CCAP_T::PAR: RANGE Position */
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#define CCAP_PAR_RANGE_Msk (0x1ul << CCAP_PAR_RANGE_Pos) /*!< CCAP_T::PAR: RANGE Mask */
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#define CCAP_PAR_PLNFMT_Pos (7) /*!< CCAP_T::PAR: PLNFMT Position */
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#define CCAP_PAR_PLNFMT_Msk (0x1ul << CCAP_PAR_PLNFMT_Pos) /*!< CCAP_T::PAR: PLNFMT Mask */
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#define CCAP_PAR_PCLKP_Pos (8) /*!< CCAP_T::PAR: PCLKP Position */
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#define CCAP_PAR_PCLKP_Msk (0x1ul << CCAP_PAR_PCLKP_Pos) /*!< CCAP_T::PAR: PCLKP Mask */
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#define CCAP_PAR_HSP_Pos (9) /*!< CCAP_T::PAR: HSP Position */
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#define CCAP_PAR_HSP_Msk (0x1ul << CCAP_PAR_HSP_Pos) /*!< CCAP_T::PAR: HSP Mask */
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#define CCAP_PAR_VSP_Pos (10) /*!< CCAP_T::PAR: VSP Position */
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#define CCAP_PAR_VSP_Msk (0x1ul << CCAP_PAR_VSP_Pos) /*!< CCAP_T::PAR: VSP Mask */
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#define CCAP_PAR_COLORCTL_Pos (11) /*!< CCAP_T::PAR: COLORCTL Position */
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#define CCAP_PAR_COLORCTL_Msk (0x3ul << CCAP_PAR_COLORCTL_Pos) /*!< CCAP_T::PAR: COLORCTL Mask */
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#define CCAP_PAR_FBB_Pos (18) /*!< CCAP_T::PAR: FBB Position */
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#define CCAP_PAR_FBB_Msk (0x1ul << CCAP_PAR_FBB_Pos) /*!< CCAP_T::PAR: FBB Mask */
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#define CCAP_INT_VINTF_Pos (0) /*!< CCAP_T::INT: VINTF Position */
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#define CCAP_INT_VINTF_Msk (0x1ul << CCAP_INT_VINTF_Pos) /*!< CCAP_T::INT: VINTF Mask */
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#define CCAP_INT_MEINTF_Pos (1) /*!< CCAP_T::INT: MEINTF Position */
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#define CCAP_INT_MEINTF_Msk (0x1ul << CCAP_INT_MEINTF_Pos) /*!< CCAP_T::INT: MEINTF Mask */
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#define CCAP_INT_ADDRMINTF_Pos (3) /*!< CCAP_T::INT: ADDRMINTF Position */
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#define CCAP_INT_ADDRMINTF_Msk (0x1ul << CCAP_INT_ADDRMINTF_Pos) /*!< CCAP_T::INT: ADDRMINTF Mask */
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#define CCAP_INT_MDINTF_Pos (4) /*!< CCAP_T::INT: MDINTF Position */
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#define CCAP_INT_MDINTF_Msk (0x1ul << CCAP_INT_MDINTF_Pos) /*!< CCAP_T::INT: MDINTF Mask */
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#define CCAP_INT_VIEN_Pos (16) /*!< CCAP_T::INT: VIEN Position */
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#define CCAP_INT_VIEN_Msk (0x1ul << CCAP_INT_VIEN_Pos) /*!< CCAP_T::INT: VIEN Mask */
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#define CCAP_INT_MEIEN_Pos (17) /*!< CCAP_T::INT: MEIEN Position */
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#define CCAP_INT_MEIEN_Msk (0x1ul << CCAP_INT_MEIEN_Pos) /*!< CCAP_T::INT: MEIEN Mask */
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#define CCAP_INT_ADDRMIEN_Pos (19) /*!< CCAP_T::INT: ADDRMIEN Position */
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#define CCAP_INT_ADDRMIEN_Msk (0x1ul << CCAP_INT_ADDRMIEN_Pos) /*!< CCAP_T::INT: ADDRMIEN Mask */
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#define CCAP_CWSP_CWSADDRH_Pos (0) /*!< CCAP_T::CWSP: CWSADDRH Position */
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#define CCAP_CWSP_CWSADDRH_Msk (0xffful << CCAP_CWSP_CWSADDRH_Pos) /*!< CCAP_T::CWSP: CWSADDRH Mask */
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#define CCAP_CWSP_CWSADDRV_Pos (16) /*!< CCAP_T::CWSP: CWSADDRV Position */
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#define CCAP_CWSP_CWSADDRV_Msk (0x7fful << CCAP_CWSP_CWSADDRV_Pos) /*!< CCAP_T::CWSP: CWSADDRV Mask */
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#define CCAP_CWS_CWW_Pos (0) /*!< CCAP_T::CWS: CWW Position */
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#define CCAP_CWS_CWW_Msk (0xffful << CCAP_CWS_CWW_Pos) /*!< CCAP_T::CWS: CWW Mask */
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#define CCAP_CWS_CWH_Pos (16) /*!< CCAP_T::CWS: CIWH Position */
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#define CCAP_CWS_CWH_Msk (0x7fful << CCAP_CWS_CWH_Pos) /*!< CCAP_T::CWS: CIWH Mask */
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#define CCAP_PKTSL_PKTSHML_Pos (0) /*!< CCAP_T::PKTSL: PKTSHML Position */
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#define CCAP_PKTSL_PKTSHML_Msk (0xfful << CCAP_PKTSL_PKTSHML_Pos) /*!< CCAP_T::PKTSL: PKTSHML Mask */
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#define CCAP_PKTSL_PKTSHNL_Pos (8) /*!< CCAP_T::PKTSL: PKTSHNL Position */
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#define CCAP_PKTSL_PKTSHNL_Msk (0xfful << CCAP_PKTSL_PKTSHNL_Pos) /*!< CCAP_T::PKTSL: PKTSHNL Mask */
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#define CCAP_PKTSL_PKTSVML_Pos (16) /*!< CCAP_T::PKTSL: PKTSVML Position */
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#define CCAP_PKTSL_PKTSVML_Msk (0xfful << CCAP_PKTSL_PKTSVML_Pos) /*!< CCAP_T::PKTSL: PKTSVML Mask */
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#define CCAP_PKTSL_PKTSVNL_Pos (24) /*!< CCAP_T::PKTSL: PKTSVNL Position */
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#define CCAP_PKTSL_PKTSVNL_Msk (0xfful << CCAP_PKTSL_PKTSVNL_Pos) /*!< CCAP_T::PKTSL: PKTSVNL Mask */
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#define CCAP_FRCTL_FRM_Pos (0) /*!< CCAP_T::FRCTL: FRM Position */
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#define CCAP_FRCTL_FRM_Msk (0x3ful << CCAP_FRCTL_FRM_Pos) /*!< CCAP_T::FRCTL: FRM Mask */
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#define CCAP_FRCTL_FRN_Pos (8) /*!< CCAP_T::FRCTL: FRN Position */
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#define CCAP_FRCTL_FRN_Msk (0x3ful << CCAP_FRCTL_FRN_Pos) /*!< CCAP_T::FRCTL: FRN Mask */
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#define CCAP_STRIDE_PKTSTRIDE_Pos (0) /*!< CCAP_T::STRIDE: PKTSTRIDE Position */
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#define CCAP_STRIDE_PKTSTRIDE_Msk (0x3ffful << CCAP_STRIDE_PKTSTRIDE_Pos) /*!< CCAP_T::STRIDE: PKTSTRIDE Mask */
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#define CCAP_STRIDE_PLNSTRIDE_Pos (16) /*!< CCAP_T::STRIDE: PLNSTRIDE Position */
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#define CCAP_STRIDE_PLNSTRIDE_Msk (0x3ffful << CCAP_STRIDE_PLNSTRIDE_Pos) /*!< CCAP_T::STRIDE: PLNSTRIDE Mask */
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#define CCAP_FIFOTH_PLNVFTH_Pos (0) /*!< CCAP_T::FIFOTH: PLNVFTH Position */
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#define CCAP_FIFOTH_PLNVFTH_Msk (0xful << CCAP_FIFOTH_PLNVFTH_Pos) /*!< CCAP_T::FIFOTH: PLNVFTH Mask */
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#define CCAP_FIFOTH_PLNUFTH_Pos (8) /*!< CCAP_T::FIFOTH: PLNUFTH Position */
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#define CCAP_FIFOTH_PLNUFTH_Msk (0xful << CCAP_FIFOTH_PLNUFTH_Pos) /*!< CCAP_T::FIFOTH: PLNUFTH Mask */
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#define CCAP_FIFOTH_PLNYFTH_Pos (16) /*!< CCAP_T::FIFOTH: PLNYFTH Position */
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#define CCAP_FIFOTH_PLNYFTH_Msk (0x1ful << CCAP_FIFOTH_PLNYFTH_Pos) /*!< CCAP_T::FIFOTH: PLNYFTH Mask */
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#define CCAP_FIFOTH_PKTFTH_Pos (24) /*!< CCAP_T::FIFOTH: PKTFTH Position */
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#define CCAP_FIFOTH_PKTFTH_Msk (0x1ful << CCAP_FIFOTH_PKTFTH_Pos) /*!< CCAP_T::FIFOTH: PKTFTH Mask */
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#define CCAP_FIFOTH_OVF_Pos (31) /*!< CCAP_T::FIFOTH: OVF Position */
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#define CCAP_FIFOTH_OVF_Msk (0x1ul << CCAP_FIFOTH_OVF_Pos) /*!< CCAP_T::FIFOTH: OVF Mask */
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#define CCAP_CMPADDR_CMPADDR_Pos (0) /*!< CCAP_T::CMPADDR: CMPADDR Position */
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#define CCAP_CMPADDR_CMPADDR_Msk (0xfffffffful << CCAP_CMPADDR_CMPADDR_Pos) /*!< CCAP_T::CMPADDR: CMPADDR Mask */
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#define CCAP_PKTSM_PKTSHMH_Pos (0) /*!< CCAP_T::PKTSM: PKTSHMH Position */
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#define CCAP_PKTSM_PKTSHMH_Msk (0xfful << CCAP_PKTSM_PKTSHMH_Pos) /*!< CCAP_T::PKTSM: PKTSHMH Mask */
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#define CCAP_PKTSM_PKTSHNH_Pos (8) /*!< CCAP_T::PKTSM: PKTSHNH Position */
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#define CCAP_PKTSM_PKTSHNH_Msk (0xfful << CCAP_PKTSM_PKTSHNH_Pos) /*!< CCAP_T::PKTSM: PKTSHNH Mask */
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#define CCAP_PKTSM_PKTSVMH_Pos (16) /*!< CCAP_T::PKTSM: PKTSVMH Position */
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#define CCAP_PKTSM_PKTSVMH_Msk (0xfful << CCAP_PKTSM_PKTSVMH_Pos) /*!< CCAP_T::PKTSM: PKTSVMH Mask */
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#define CCAP_PKTSM_PKTSVNH_Pos (24) /*!< CCAP_T::PKTSM: PKTSVNH Position */
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#define CCAP_PKTSM_PKTSVNH_Msk (0xfful << CCAP_PKTSM_PKTSVNH_Pos) /*!< CCAP_T::PKTSM: PKTSVNH Mask */
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#define CCAP_PKTBA0_BASEADDR_Pos (0) /*!< CCAP_T::PKTBA0: BASEADDR Position */
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#define CCAP_PKTBA0_BASEADDR_Msk (0xfffffffful << CCAP_PKTBA0_BASEADDR_Pos) /*!< CCAP_T::PKTBA0: BASEADDR Mask */
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/**@}*/ /* CCAP_CONST */
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/**@}*/ /* end of CCAP register group */
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/**@}*/ /* end of REGISTER group */
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#if defined ( __CC_ARM )
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#pragma no_anon_unions
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#endif
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#endif /* __CCAP_REG_H__ */
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