172 lines
5.3 KiB
C
172 lines
5.3 KiB
C
/*
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* Copyright (c) 2019 - 2022, Nordic Semiconductor ASA
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <nrfx.h>
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#if NRFX_CHECK(NRFX_IPC_ENABLED)
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#include <nrfx_ipc.h>
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// Control block - driver instance local data.
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typedef struct
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{
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nrfx_ipc_handler_t handler;
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nrfx_drv_state_t state;
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void * p_context;
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} ipc_control_block_t;
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static ipc_control_block_t m_ipc_cb;
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nrfx_err_t nrfx_ipc_init(uint8_t irq_priority, nrfx_ipc_handler_t handler, void * p_context)
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{
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if (m_ipc_cb.state != NRFX_DRV_STATE_UNINITIALIZED)
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{
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return NRFX_ERROR_ALREADY_INITIALIZED;
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}
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NRFX_IRQ_PRIORITY_SET(IPC_IRQn, irq_priority);
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NRFX_IRQ_ENABLE(IPC_IRQn);
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m_ipc_cb.state = NRFX_DRV_STATE_INITIALIZED;
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m_ipc_cb.handler = handler;
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m_ipc_cb.p_context = p_context;
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return NRFX_SUCCESS;
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}
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void nrfx_ipc_config_load(const nrfx_ipc_config_t * p_config)
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{
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NRFX_ASSERT(p_config);
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NRFX_ASSERT(m_ipc_cb.state == NRFX_DRV_STATE_INITIALIZED);
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uint32_t i;
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for (i = 0; i < IPC_CONF_NUM; ++i)
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{
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nrf_ipc_send_config_set(NRF_IPC, i, p_config->send_task_config[i]);
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}
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for (i = 0; i < IPC_CONF_NUM; ++i)
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{
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nrf_ipc_receive_config_set(NRF_IPC, i, p_config->receive_event_config[i]);
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}
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nrf_ipc_int_enable(NRF_IPC, p_config->receive_events_enabled);
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}
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void nrfx_ipc_uninit(void)
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{
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NRFX_ASSERT(m_ipc_cb.state == NRFX_DRV_STATE_INITIALIZED);
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uint32_t i;
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for (i = 0; i < IPC_CONF_NUM; ++i)
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{
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nrf_ipc_send_config_set(NRF_IPC, i, 0);
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}
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for (i = 0; i < IPC_CONF_NUM; ++i)
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{
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nrf_ipc_receive_config_set(NRF_IPC, i, 0);
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}
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nrf_ipc_int_disable(NRF_IPC, 0xFFFFFFFF);
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m_ipc_cb.state = NRFX_DRV_STATE_UNINITIALIZED;
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}
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void nrfx_ipc_receive_event_enable(uint8_t event_index)
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{
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NRFX_ASSERT(m_ipc_cb.state == NRFX_DRV_STATE_INITIALIZED);
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nrf_ipc_int_enable(NRF_IPC, (1UL << event_index));
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}
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void nrfx_ipc_receive_event_disable(uint8_t event_index)
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{
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NRFX_ASSERT(m_ipc_cb.state == NRFX_DRV_STATE_INITIALIZED);
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nrf_ipc_int_disable(NRF_IPC, (1UL << event_index));
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}
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void nrfx_ipc_receive_event_group_enable(uint32_t event_bitmask)
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{
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NRFX_ASSERT(m_ipc_cb.state == NRFX_DRV_STATE_INITIALIZED);
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nrf_ipc_int_enable(NRF_IPC, event_bitmask);
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}
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void nrfx_ipc_receive_event_group_disable(uint32_t event_bitmask)
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{
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NRFX_ASSERT(m_ipc_cb.state == NRFX_DRV_STATE_INITIALIZED);
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nrf_ipc_int_disable(NRF_IPC, event_bitmask);
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}
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void nrfx_ipc_receive_event_channel_assign(uint8_t event_index, uint8_t channel_index)
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{
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NRFX_ASSERT(channel_index < IPC_CH_NUM);
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uint32_t channel_bitmask = (1UL << channel_index);
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channel_bitmask |= nrf_ipc_receive_config_get(NRF_IPC, event_index);
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nrf_ipc_receive_config_set(NRF_IPC, event_index, channel_bitmask);
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}
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void nrfx_ipc_send_task_channel_assign(uint8_t send_index, uint8_t channel_index)
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{
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NRFX_ASSERT(channel_index < IPC_CH_NUM);
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uint32_t channel_bitmask = (1UL << channel_index);
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channel_bitmask |= nrf_ipc_send_config_get(NRF_IPC, send_index);
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nrf_ipc_send_config_set(NRF_IPC, send_index, channel_bitmask);
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}
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void nrfx_ipc_irq_handler(void)
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{
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// Get the information about events that fire this interrupt
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uint32_t events_map = nrf_ipc_int_pending_get(NRF_IPC);
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// Clear these events
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uint32_t bitmask = events_map;
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while (bitmask)
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{
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uint8_t event_idx = NRF_CTZ(bitmask);
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bitmask &= ~(1UL << event_idx);
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nrf_ipc_event_clear(NRF_IPC, nrf_ipc_receive_event_get(event_idx));
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#if NRFX_CHECK(NRFX_CONFIG_API_VER_2_10)
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if (m_ipc_cb.handler)
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{
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m_ipc_cb.handler(event_idx, m_ipc_cb.p_context);
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}
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#elif NRFX_CHECK(NRFX_CONFIG_API_VER_2_9)
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}
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if (m_ipc_cb.handler)
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{
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m_ipc_cb.handler(events_map, m_ipc_cb.p_context);
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#endif
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}
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}
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#endif // NRFX_CHECK(NRFX_IPC_ENABLED)
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