1416 lines
26 KiB
C
1416 lines
26 KiB
C
/*
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* Autogenerated file
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <dt-bindings/pinctrl/atmel_sam_pinctrl.h>
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/* pa0_gpio */
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#define PA0_GPIO \
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SAM_PINMUX(a, 0, gpio, gpio)
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/* pa0a_eic_extint0 */
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#define PA0A_EIC_EXTINT0 \
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SAM_PINMUX(a, 0, a, periph)
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/* pa0d_sercom1_pad0 */
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#define PA0D_SERCOM1_PAD0 \
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SAM_PINMUX(a, 0, d, periph)
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/* pa0e_tc2_wo0 */
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#define PA0E_TC2_WO0 \
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SAM_PINMUX(a, 0, e, periph)
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/* pa0h_ac_cmp2 */
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#define PA0H_AC_CMP2 \
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SAM_PINMUX(a, 0, h, periph)
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/* pa1_gpio */
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#define PA1_GPIO \
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SAM_PINMUX(a, 1, gpio, gpio)
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/* pa1a_eic_extint1 */
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#define PA1A_EIC_EXTINT1 \
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SAM_PINMUX(a, 1, a, periph)
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/* pa1d_sercom1_pad1 */
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#define PA1D_SERCOM1_PAD1 \
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SAM_PINMUX(a, 1, d, periph)
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/* pa1e_tc2_wo1 */
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#define PA1E_TC2_WO1 \
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SAM_PINMUX(a, 1, e, periph)
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/* pa1h_ac_cmp3 */
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#define PA1H_AC_CMP3 \
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SAM_PINMUX(a, 1, h, periph)
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/* pa2_gpio */
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#define PA2_GPIO \
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SAM_PINMUX(a, 2, gpio, gpio)
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/* pa2a_eic_extint2 */
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#define PA2A_EIC_EXTINT2 \
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SAM_PINMUX(a, 2, a, periph)
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/* pa2b_adc0_ain0 */
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#define PA2B_ADC0_AIN0 \
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SAM_PINMUX(a, 2, b, periph)
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/* pa2b_ac_ain4 */
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#define PA2B_AC_AIN4 \
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SAM_PINMUX(a, 2, b, periph)
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/* pa2b_ptc_y0 */
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#define PA2B_PTC_Y0 \
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SAM_PINMUX(a, 2, b, periph)
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/* pa2b_dac_vout */
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#define PA2B_DAC_VOUT \
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SAM_PINMUX(a, 2, b, periph)
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/* pa3_gpio */
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#define PA3_GPIO \
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SAM_PINMUX(a, 3, gpio, gpio)
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/* pa3a_eic_extint3 */
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#define PA3A_EIC_EXTINT3 \
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SAM_PINMUX(a, 3, a, periph)
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/* pa3b_anaref_vrefa */
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#define PA3B_ANAREF_VREFA \
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SAM_PINMUX(a, 3, b, periph)
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/* pa3b_adc0_ain5 */
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#define PA3B_ADC0_AIN5 \
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SAM_PINMUX(a, 3, b, periph)
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/* pa3b_ac_ain4 */
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#define PA3B_AC_AIN4 \
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SAM_PINMUX(a, 3, b, periph)
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/* pa3b_ptc_y1 */
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#define PA3B_PTC_Y1 \
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SAM_PINMUX(a, 3, b, periph)
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/* pa4_gpio */
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#define PA4_GPIO \
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SAM_PINMUX(a, 4, gpio, gpio)
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/* pa4a_eic_extint4 */
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#define PA4A_EIC_EXTINT4 \
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SAM_PINMUX(a, 4, a, periph)
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/* pa4b_anaref_vrefb */
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#define PA4B_ANAREF_VREFB \
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SAM_PINMUX(a, 4, b, periph)
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/* pa4b_adc0_ain4 */
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#define PA4B_ADC0_AIN4 \
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SAM_PINMUX(a, 4, b, periph)
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/* pa4b_ac_ain0 */
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#define PA4B_AC_AIN0 \
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SAM_PINMUX(a, 4, b, periph)
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/* pa4b_ptc_y2 */
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#define PA4B_PTC_Y2 \
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SAM_PINMUX(a, 4, b, periph)
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/* pa4d_sercom0_pad0 */
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#define PA4D_SERCOM0_PAD0 \
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SAM_PINMUX(a, 4, d, periph)
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/* pa4e_tcc0_wo0 */
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#define PA4E_TCC0_WO0 \
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SAM_PINMUX(a, 4, e, periph)
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/* pa5_gpio */
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#define PA5_GPIO \
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SAM_PINMUX(a, 5, gpio, gpio)
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/* pa5a_eic_extint5 */
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#define PA5A_EIC_EXTINT5 \
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SAM_PINMUX(a, 5, a, periph)
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/* pa5b_adc0_ain5 */
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#define PA5B_ADC0_AIN5 \
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SAM_PINMUX(a, 5, b, periph)
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/* pa5b_ac_ain1 */
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#define PA5B_AC_AIN1 \
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SAM_PINMUX(a, 5, b, periph)
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/* pa5b_ptc_y3 */
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#define PA5B_PTC_Y3 \
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SAM_PINMUX(a, 5, b, periph)
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/* pa5d_sercom0_pad1 */
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#define PA5D_SERCOM0_PAD1 \
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SAM_PINMUX(a, 5, d, periph)
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/* pa5e_tcc0_wo1 */
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#define PA5E_TCC0_WO1 \
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SAM_PINMUX(a, 5, e, periph)
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/* pa6_gpio */
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#define PA6_GPIO \
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SAM_PINMUX(a, 6, gpio, gpio)
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/* pa6a_eic_extint6 */
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#define PA6A_EIC_EXTINT6 \
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SAM_PINMUX(a, 6, a, periph)
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/* pa6b_adc0_ain6 */
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#define PA6B_ADC0_AIN6 \
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SAM_PINMUX(a, 6, b, periph)
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/* pa6b_ac_ain2 */
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#define PA6B_AC_AIN2 \
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SAM_PINMUX(a, 6, b, periph)
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/* pa6b_ptc_y4 */
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#define PA6B_PTC_Y4 \
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SAM_PINMUX(a, 6, b, periph)
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/* pa6b_sdadc0_ainn0 */
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#define PA6B_SDADC0_AINN0 \
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SAM_PINMUX(a, 6, b, periph)
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/* pa6d_sercom0_pad2 */
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#define PA6D_SERCOM0_PAD2 \
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SAM_PINMUX(a, 6, d, periph)
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/* pa6e_tcc1_wo0 */
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#define PA6E_TCC1_WO0 \
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SAM_PINMUX(a, 6, e, periph)
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/* pa7_gpio */
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#define PA7_GPIO \
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SAM_PINMUX(a, 7, gpio, gpio)
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/* pa7a_eic_extint7 */
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#define PA7A_EIC_EXTINT7 \
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SAM_PINMUX(a, 7, a, periph)
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/* pa7b_adc0_ain7 */
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#define PA7B_ADC0_AIN7 \
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SAM_PINMUX(a, 7, b, periph)
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/* pa7b_ac_ain3 */
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#define PA7B_AC_AIN3 \
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SAM_PINMUX(a, 7, b, periph)
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/* pa7b_ptc_y5 */
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#define PA7B_PTC_Y5 \
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SAM_PINMUX(a, 7, b, periph)
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/* pa7b_sdadc0_ainp0 */
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#define PA7B_SDADC0_AINP0 \
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SAM_PINMUX(a, 7, b, periph)
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/* pa7d_sercom0_pad3 */
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#define PA7D_SERCOM0_PAD3 \
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SAM_PINMUX(a, 7, d, periph)
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/* pa7e_tcc1_wo1 */
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#define PA7E_TCC1_WO1 \
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SAM_PINMUX(a, 7, e, periph)
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/* pa8_gpio */
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#define PA8_GPIO \
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SAM_PINMUX(a, 8, gpio, gpio)
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/* pa8a_eic_nmi */
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#define PA8A_EIC_NMI \
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SAM_PINMUX(a, 8, a, periph)
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/* pa8b_adc0_ain8 */
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#define PA8B_ADC0_AIN8 \
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SAM_PINMUX(a, 8, b, periph)
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/* pa8b_adc1_ain10 */
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#define PA8B_ADC1_AIN10 \
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SAM_PINMUX(a, 8, b, periph)
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/* pa8b_ptc_xy16 */
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#define PA8B_PTC_XY16 \
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SAM_PINMUX(a, 8, b, periph)
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/* pa8c_sercom0_pad0 */
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#define PA8C_SERCOM0_PAD0 \
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SAM_PINMUX(a, 8, c, periph)
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/* pa8d_sercom2_pad0 */
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#define PA8D_SERCOM2_PAD0 \
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SAM_PINMUX(a, 8, d, periph)
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/* pa8e_tcc0_wo0 */
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#define PA8E_TCC0_WO0 \
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SAM_PINMUX(a, 8, e, periph)
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/* pa8f_tcc1_wo2 */
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#define PA8F_TCC1_WO2 \
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SAM_PINMUX(a, 8, f, periph)
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/* pa9_gpio */
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#define PA9_GPIO \
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SAM_PINMUX(a, 9, gpio, gpio)
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/* pa9a_eic_extint9 */
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#define PA9A_EIC_EXTINT9 \
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SAM_PINMUX(a, 9, a, periph)
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/* pa9b_adc0_ain9 */
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#define PA9B_ADC0_AIN9 \
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SAM_PINMUX(a, 9, b, periph)
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/* pa9b_adc1_ain11 */
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#define PA9B_ADC1_AIN11 \
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SAM_PINMUX(a, 9, b, periph)
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/* pa9b_ptc_x1 */
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#define PA9B_PTC_X1 \
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SAM_PINMUX(a, 9, b, periph)
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/* pa9c_sercom0_pad1 */
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#define PA9C_SERCOM0_PAD1 \
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SAM_PINMUX(a, 9, c, periph)
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/* pa9d_sercom2_pad1 */
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#define PA9D_SERCOM2_PAD1 \
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SAM_PINMUX(a, 9, d, periph)
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/* pa9e_tcc0_wo1 */
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#define PA9E_TCC0_WO1 \
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SAM_PINMUX(a, 9, e, periph)
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/* pa9f_tcc1_wo3 */
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#define PA9F_TCC1_WO3 \
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SAM_PINMUX(a, 9, f, periph)
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/* pa10_gpio */
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#define PA10_GPIO \
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SAM_PINMUX(a, 10, gpio, gpio)
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/* pa10a_eic_extint10 */
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#define PA10A_EIC_EXTINT10 \
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SAM_PINMUX(a, 10, a, periph)
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/* pa10b_adc0_ain10 */
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#define PA10B_ADC0_AIN10 \
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SAM_PINMUX(a, 10, b, periph)
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/* pa10b_ptc_x2 */
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#define PA10B_PTC_X2 \
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SAM_PINMUX(a, 10, b, periph)
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/* pa10c_sercom0_pad2 */
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#define PA10C_SERCOM0_PAD2 \
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SAM_PINMUX(a, 10, c, periph)
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/* pa10d_sercom2_pad2 */
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#define PA10D_SERCOM2_PAD2 \
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SAM_PINMUX(a, 10, d, periph)
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/* pa10e_tcc1_wo0 */
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#define PA10E_TCC1_WO0 \
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SAM_PINMUX(a, 10, e, periph)
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/* pa10f_tcc0_wo2 */
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#define PA10F_TCC0_WO2 \
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SAM_PINMUX(a, 10, f, periph)
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/* pa10h_gclk_io4 */
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#define PA10H_GCLK_IO4 \
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SAM_PINMUX(a, 10, h, periph)
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/* pa11_gpio */
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#define PA11_GPIO \
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SAM_PINMUX(a, 11, gpio, gpio)
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/* pa11a_eic_extint11 */
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#define PA11A_EIC_EXTINT11 \
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SAM_PINMUX(a, 11, a, periph)
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/* pa11b_adc0_ain11 */
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#define PA11B_ADC0_AIN11 \
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SAM_PINMUX(a, 11, b, periph)
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/* pa11b_ptc_x3 */
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#define PA11B_PTC_X3 \
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SAM_PINMUX(a, 11, b, periph)
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/* pa11c_sercom0_pad3 */
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#define PA11C_SERCOM0_PAD3 \
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SAM_PINMUX(a, 11, c, periph)
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/* pa11d_sercom2_pad3 */
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#define PA11D_SERCOM2_PAD3 \
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SAM_PINMUX(a, 11, d, periph)
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/* pa11e_tcc1_wo1 */
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#define PA11E_TCC1_WO1 \
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SAM_PINMUX(a, 11, e, periph)
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/* pa11f_tcc0_wo3 */
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#define PA11F_TCC0_WO3 \
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SAM_PINMUX(a, 11, f, periph)
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/* pa11h_gclk_io5 */
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#define PA11H_GCLK_IO5 \
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SAM_PINMUX(a, 11, h, periph)
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/* pa12_gpio */
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#define PA12_GPIO \
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SAM_PINMUX(a, 12, gpio, gpio)
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/* pa12a_eic_extint12 */
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#define PA12A_EIC_EXTINT12 \
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SAM_PINMUX(a, 12, a, periph)
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/* pa12c_sercom2_pad0 */
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#define PA12C_SERCOM2_PAD0 \
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SAM_PINMUX(a, 12, c, periph)
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/* pa12d_sercom4_pad0 */
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#define PA12D_SERCOM4_PAD0 \
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SAM_PINMUX(a, 12, d, periph)
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/* pa12e_tcc2_wo0 */
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#define PA12E_TCC2_WO0 \
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SAM_PINMUX(a, 12, e, periph)
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/* pa12f_tcc0_wo6 */
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#define PA12F_TCC0_WO6 \
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SAM_PINMUX(a, 12, f, periph)
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/* pa12h_ac_cmp0 */
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#define PA12H_AC_CMP0 \
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SAM_PINMUX(a, 12, h, periph)
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/* pa13_gpio */
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#define PA13_GPIO \
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SAM_PINMUX(a, 13, gpio, gpio)
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/* pa13a_eic_extint13 */
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#define PA13A_EIC_EXTINT13 \
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SAM_PINMUX(a, 13, a, periph)
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/* pa13c_sercom2_pad1 */
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#define PA13C_SERCOM2_PAD1 \
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SAM_PINMUX(a, 13, c, periph)
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/* pa13d_sercom4_pad1 */
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#define PA13D_SERCOM4_PAD1 \
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SAM_PINMUX(a, 13, d, periph)
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/* pa13e_tcc2_wo1 */
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#define PA13E_TCC2_WO1 \
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SAM_PINMUX(a, 13, e, periph)
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/* pa13f_tcc0_wo7 */
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#define PA13F_TCC0_WO7 \
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SAM_PINMUX(a, 13, f, periph)
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/* pa13h_ac_cmp1 */
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#define PA13H_AC_CMP1 \
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SAM_PINMUX(a, 13, h, periph)
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/* pa14_gpio */
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#define PA14_GPIO \
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SAM_PINMUX(a, 14, gpio, gpio)
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/* pa14a_eic_extint14 */
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#define PA14A_EIC_EXTINT14 \
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SAM_PINMUX(a, 14, a, periph)
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/* pa14c_sercom2_pad2 */
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#define PA14C_SERCOM2_PAD2 \
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SAM_PINMUX(a, 14, c, periph)
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/* pa14d_sercom4_pad2 */
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#define PA14D_SERCOM4_PAD2 \
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SAM_PINMUX(a, 14, d, periph)
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/* pa14e_tc4_wo0 */
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#define PA14E_TC4_WO0 \
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SAM_PINMUX(a, 14, e, periph)
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/* pa14f_tcc0_wo4 */
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#define PA14F_TCC0_WO4 \
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SAM_PINMUX(a, 14, f, periph)
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/* pa14h_gclk_io0 */
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#define PA14H_GCLK_IO0 \
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SAM_PINMUX(a, 14, h, periph)
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/* pa15_gpio */
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#define PA15_GPIO \
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SAM_PINMUX(a, 15, gpio, gpio)
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/* pa15a_eic_extint15 */
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#define PA15A_EIC_EXTINT15 \
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SAM_PINMUX(a, 15, a, periph)
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/* pa15c_sercom2_pad3 */
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#define PA15C_SERCOM2_PAD3 \
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SAM_PINMUX(a, 15, c, periph)
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/* pa15d_sercom4_pad3 */
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#define PA15D_SERCOM4_PAD3 \
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SAM_PINMUX(a, 15, d, periph)
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/* pa15e_tc4_wo1 */
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#define PA15E_TC4_WO1 \
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SAM_PINMUX(a, 15, e, periph)
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/* pa15f_tcc0_wo5 */
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#define PA15F_TCC0_WO5 \
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SAM_PINMUX(a, 15, f, periph)
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/* pa15h_gclk_io1 */
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#define PA15H_GCLK_IO1 \
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SAM_PINMUX(a, 15, h, periph)
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/* pa16_gpio */
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#define PA16_GPIO \
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SAM_PINMUX(a, 16, gpio, gpio)
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/* pa16a_eic_extint0 */
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#define PA16A_EIC_EXTINT0 \
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SAM_PINMUX(a, 16, a, periph)
|
|
|
|
/* pa16b_ptc_x4 */
|
|
#define PA16B_PTC_X4 \
|
|
SAM_PINMUX(a, 16, b, periph)
|
|
|
|
/* pa16c_sercom1_pad0 */
|
|
#define PA16C_SERCOM1_PAD0 \
|
|
SAM_PINMUX(a, 16, c, periph)
|
|
|
|
/* pa16d_sercom3_pad0 */
|
|
#define PA16D_SERCOM3_PAD0 \
|
|
SAM_PINMUX(a, 16, d, periph)
|
|
|
|
/* pa16e_tcc2_wo0 */
|
|
#define PA16E_TCC2_WO0 \
|
|
SAM_PINMUX(a, 16, e, periph)
|
|
|
|
/* pa16f_tcc0_wo6 */
|
|
#define PA16F_TCC0_WO6 \
|
|
SAM_PINMUX(a, 16, f, periph)
|
|
|
|
/* pa16h_gclk_io2 */
|
|
#define PA16H_GCLK_IO2 \
|
|
SAM_PINMUX(a, 16, h, periph)
|
|
|
|
/* pa17_gpio */
|
|
#define PA17_GPIO \
|
|
SAM_PINMUX(a, 17, gpio, gpio)
|
|
|
|
/* pa17a_eic_extint1 */
|
|
#define PA17A_EIC_EXTINT1 \
|
|
SAM_PINMUX(a, 17, a, periph)
|
|
|
|
/* pa17b_ptc_x5 */
|
|
#define PA17B_PTC_X5 \
|
|
SAM_PINMUX(a, 17, b, periph)
|
|
|
|
/* pa17c_sercom1_pad1 */
|
|
#define PA17C_SERCOM1_PAD1 \
|
|
SAM_PINMUX(a, 17, c, periph)
|
|
|
|
/* pa17d_sercom3_pad1 */
|
|
#define PA17D_SERCOM3_PAD1 \
|
|
SAM_PINMUX(a, 17, d, periph)
|
|
|
|
/* pa17e_tcc2_wo1 */
|
|
#define PA17E_TCC2_WO1 \
|
|
SAM_PINMUX(a, 17, e, periph)
|
|
|
|
/* pa17f_tcc0_wo7 */
|
|
#define PA17F_TCC0_WO7 \
|
|
SAM_PINMUX(a, 17, f, periph)
|
|
|
|
/* pa17h_gclk_io3 */
|
|
#define PA17H_GCLK_IO3 \
|
|
SAM_PINMUX(a, 17, h, periph)
|
|
|
|
/* pa18_gpio */
|
|
#define PA18_GPIO \
|
|
SAM_PINMUX(a, 18, gpio, gpio)
|
|
|
|
/* pa18a_eic_extint2 */
|
|
#define PA18A_EIC_EXTINT2 \
|
|
SAM_PINMUX(a, 18, a, periph)
|
|
|
|
/* pa18b_ptc_x6 */
|
|
#define PA18B_PTC_X6 \
|
|
SAM_PINMUX(a, 18, b, periph)
|
|
|
|
/* pa18c_sercom1_pad2 */
|
|
#define PA18C_SERCOM1_PAD2 \
|
|
SAM_PINMUX(a, 18, c, periph)
|
|
|
|
/* pa18d_sercom3_pad2 */
|
|
#define PA18D_SERCOM3_PAD2 \
|
|
SAM_PINMUX(a, 18, d, periph)
|
|
|
|
/* pa18e_tc4_wo0 */
|
|
#define PA18E_TC4_WO0 \
|
|
SAM_PINMUX(a, 18, e, periph)
|
|
|
|
/* pa18f_tcc0_wo2 */
|
|
#define PA18F_TCC0_WO2 \
|
|
SAM_PINMUX(a, 18, f, periph)
|
|
|
|
/* pa18h_ac_cmp0 */
|
|
#define PA18H_AC_CMP0 \
|
|
SAM_PINMUX(a, 18, h, periph)
|
|
|
|
/* pa19_gpio */
|
|
#define PA19_GPIO \
|
|
SAM_PINMUX(a, 19, gpio, gpio)
|
|
|
|
/* pa19a_eic_extint3 */
|
|
#define PA19A_EIC_EXTINT3 \
|
|
SAM_PINMUX(a, 19, a, periph)
|
|
|
|
/* pa19b_ptc_x7 */
|
|
#define PA19B_PTC_X7 \
|
|
SAM_PINMUX(a, 19, b, periph)
|
|
|
|
/* pa19c_sercom1_pad3 */
|
|
#define PA19C_SERCOM1_PAD3 \
|
|
SAM_PINMUX(a, 19, c, periph)
|
|
|
|
/* pa19d_sercom3_pad3 */
|
|
#define PA19D_SERCOM3_PAD3 \
|
|
SAM_PINMUX(a, 19, d, periph)
|
|
|
|
/* pa19e_tc4_wo1 */
|
|
#define PA19E_TC4_WO1 \
|
|
SAM_PINMUX(a, 19, e, periph)
|
|
|
|
/* pa19f_tcc0_wo3 */
|
|
#define PA19F_TCC0_WO3 \
|
|
SAM_PINMUX(a, 19, f, periph)
|
|
|
|
/* pa19h_ac_cmp1 */
|
|
#define PA19H_AC_CMP1 \
|
|
SAM_PINMUX(a, 19, h, periph)
|
|
|
|
/* pa20_gpio */
|
|
#define PA20_GPIO \
|
|
SAM_PINMUX(a, 20, gpio, gpio)
|
|
|
|
/* pa20a_eic_extint4 */
|
|
#define PA20A_EIC_EXTINT4 \
|
|
SAM_PINMUX(a, 20, a, periph)
|
|
|
|
/* pa20b_ptc_x8 */
|
|
#define PA20B_PTC_X8 \
|
|
SAM_PINMUX(a, 20, b, periph)
|
|
|
|
/* pa20c_sercom5_pad2 */
|
|
#define PA20C_SERCOM5_PAD2 \
|
|
SAM_PINMUX(a, 20, c, periph)
|
|
|
|
/* pa20d_sercom3_pad2 */
|
|
#define PA20D_SERCOM3_PAD2 \
|
|
SAM_PINMUX(a, 20, d, periph)
|
|
|
|
/* pa20e_tc3_wo0 */
|
|
#define PA20E_TC3_WO0 \
|
|
SAM_PINMUX(a, 20, e, periph)
|
|
|
|
/* pa20f_tcc0_wo6 */
|
|
#define PA20F_TCC0_WO6 \
|
|
SAM_PINMUX(a, 20, f, periph)
|
|
|
|
/* pa20h_gclk_io4 */
|
|
#define PA20H_GCLK_IO4 \
|
|
SAM_PINMUX(a, 20, h, periph)
|
|
|
|
/* pa21_gpio */
|
|
#define PA21_GPIO \
|
|
SAM_PINMUX(a, 21, gpio, gpio)
|
|
|
|
/* pa21a_eic_extint5 */
|
|
#define PA21A_EIC_EXTINT5 \
|
|
SAM_PINMUX(a, 21, a, periph)
|
|
|
|
/* pa21b_ptc_x9 */
|
|
#define PA21B_PTC_X9 \
|
|
SAM_PINMUX(a, 21, b, periph)
|
|
|
|
/* pa21c_sercom5_pad3 */
|
|
#define PA21C_SERCOM5_PAD3 \
|
|
SAM_PINMUX(a, 21, c, periph)
|
|
|
|
/* pa21d_sercom3_pad3 */
|
|
#define PA21D_SERCOM3_PAD3 \
|
|
SAM_PINMUX(a, 21, d, periph)
|
|
|
|
/* pa21e_tc3_wo1 */
|
|
#define PA21E_TC3_WO1 \
|
|
SAM_PINMUX(a, 21, e, periph)
|
|
|
|
/* pa21f_tcc0_wo7 */
|
|
#define PA21F_TCC0_WO7 \
|
|
SAM_PINMUX(a, 21, f, periph)
|
|
|
|
/* pa21h_gclk_io5 */
|
|
#define PA21H_GCLK_IO5 \
|
|
SAM_PINMUX(a, 21, h, periph)
|
|
|
|
/* pa22_gpio */
|
|
#define PA22_GPIO \
|
|
SAM_PINMUX(a, 22, gpio, gpio)
|
|
|
|
/* pa22a_eic_extint6 */
|
|
#define PA22A_EIC_EXTINT6 \
|
|
SAM_PINMUX(a, 22, a, periph)
|
|
|
|
/* pa22b_ptc_x10 */
|
|
#define PA22B_PTC_X10 \
|
|
SAM_PINMUX(a, 22, b, periph)
|
|
|
|
/* pa22c_sercom3_pad0 */
|
|
#define PA22C_SERCOM3_PAD0 \
|
|
SAM_PINMUX(a, 22, c, periph)
|
|
|
|
/* pa22d_sercom5_pad0 */
|
|
#define PA22D_SERCOM5_PAD0 \
|
|
SAM_PINMUX(a, 22, d, periph)
|
|
|
|
/* pa22e_tc0_wo0 */
|
|
#define PA22E_TC0_WO0 \
|
|
SAM_PINMUX(a, 22, e, periph)
|
|
|
|
/* pa22f_tcc0_wo4 */
|
|
#define PA22F_TCC0_WO4 \
|
|
SAM_PINMUX(a, 22, f, periph)
|
|
|
|
/* pa22h_gclk_io6 */
|
|
#define PA22H_GCLK_IO6 \
|
|
SAM_PINMUX(a, 22, h, periph)
|
|
|
|
/* pa23_gpio */
|
|
#define PA23_GPIO \
|
|
SAM_PINMUX(a, 23, gpio, gpio)
|
|
|
|
/* pa23a_eic_extint7 */
|
|
#define PA23A_EIC_EXTINT7 \
|
|
SAM_PINMUX(a, 23, a, periph)
|
|
|
|
/* pa23b_ptc_x11 */
|
|
#define PA23B_PTC_X11 \
|
|
SAM_PINMUX(a, 23, b, periph)
|
|
|
|
/* pa23c_sercom3_pad1 */
|
|
#define PA23C_SERCOM3_PAD1 \
|
|
SAM_PINMUX(a, 23, c, periph)
|
|
|
|
/* pa23d_sercom5_pad1 */
|
|
#define PA23D_SERCOM5_PAD1 \
|
|
SAM_PINMUX(a, 23, d, periph)
|
|
|
|
/* pa23e_tc0_wo1 */
|
|
#define PA23E_TC0_WO1 \
|
|
SAM_PINMUX(a, 23, e, periph)
|
|
|
|
/* pa23f_tcc0_wo5 */
|
|
#define PA23F_TCC0_WO5 \
|
|
SAM_PINMUX(a, 23, f, periph)
|
|
|
|
/* pa23h_gclk_io7 */
|
|
#define PA23H_GCLK_IO7 \
|
|
SAM_PINMUX(a, 23, h, periph)
|
|
|
|
/* pa24_gpio */
|
|
#define PA24_GPIO \
|
|
SAM_PINMUX(a, 24, gpio, gpio)
|
|
|
|
/* pa24a_eic_extint12 */
|
|
#define PA24A_EIC_EXTINT12 \
|
|
SAM_PINMUX(a, 24, a, periph)
|
|
|
|
/* pa24c_sercom3_pad2 */
|
|
#define PA24C_SERCOM3_PAD2 \
|
|
SAM_PINMUX(a, 24, c, periph)
|
|
|
|
/* pa24d_sercom5_pad2 */
|
|
#define PA24D_SERCOM5_PAD2 \
|
|
SAM_PINMUX(a, 24, d, periph)
|
|
|
|
/* pa24e_tc1_wo0 */
|
|
#define PA24E_TC1_WO0 \
|
|
SAM_PINMUX(a, 24, e, periph)
|
|
|
|
/* pa24f_tcc1_wo2 */
|
|
#define PA24F_TCC1_WO2 \
|
|
SAM_PINMUX(a, 24, f, periph)
|
|
|
|
/* pa24g_can0_tx */
|
|
#define PA24G_CAN0_TX \
|
|
SAM_PINMUX(a, 24, g, periph)
|
|
|
|
/* pa24h_ac_cmp2 */
|
|
#define PA24H_AC_CMP2 \
|
|
SAM_PINMUX(a, 24, h, periph)
|
|
|
|
/* pa25_gpio */
|
|
#define PA25_GPIO \
|
|
SAM_PINMUX(a, 25, gpio, gpio)
|
|
|
|
/* pa25a_eic_extint13 */
|
|
#define PA25A_EIC_EXTINT13 \
|
|
SAM_PINMUX(a, 25, a, periph)
|
|
|
|
/* pa25c_sercom3_pad3 */
|
|
#define PA25C_SERCOM3_PAD3 \
|
|
SAM_PINMUX(a, 25, c, periph)
|
|
|
|
/* pa25d_sercom5_pad3 */
|
|
#define PA25D_SERCOM5_PAD3 \
|
|
SAM_PINMUX(a, 25, d, periph)
|
|
|
|
/* pa25e_tc1_wo1 */
|
|
#define PA25E_TC1_WO1 \
|
|
SAM_PINMUX(a, 25, e, periph)
|
|
|
|
/* pa25f_tcc1_wo3 */
|
|
#define PA25F_TCC1_WO3 \
|
|
SAM_PINMUX(a, 25, f, periph)
|
|
|
|
/* pa25g_can0_rx */
|
|
#define PA25G_CAN0_RX \
|
|
SAM_PINMUX(a, 25, g, periph)
|
|
|
|
/* pa25h_ac_cmp3 */
|
|
#define PA25H_AC_CMP3 \
|
|
SAM_PINMUX(a, 25, h, periph)
|
|
|
|
/* pa27_gpio */
|
|
#define PA27_GPIO \
|
|
SAM_PINMUX(a, 27, gpio, gpio)
|
|
|
|
/* pa27a_eic_extint15 */
|
|
#define PA27A_EIC_EXTINT15 \
|
|
SAM_PINMUX(a, 27, a, periph)
|
|
|
|
/* pa27h_gclk_io0 */
|
|
#define PA27H_GCLK_IO0 \
|
|
SAM_PINMUX(a, 27, h, periph)
|
|
|
|
/* pa28_gpio */
|
|
#define PA28_GPIO \
|
|
SAM_PINMUX(a, 28, gpio, gpio)
|
|
|
|
/* pa28a_eic_extint8 */
|
|
#define PA28A_EIC_EXTINT8 \
|
|
SAM_PINMUX(a, 28, a, periph)
|
|
|
|
/* pa28h_gclk_io0 */
|
|
#define PA28H_GCLK_IO0 \
|
|
SAM_PINMUX(a, 28, h, periph)
|
|
|
|
/* pa30_gpio */
|
|
#define PA30_GPIO \
|
|
SAM_PINMUX(a, 30, gpio, gpio)
|
|
|
|
/* pa30a_eic_extint10 */
|
|
#define PA30A_EIC_EXTINT10 \
|
|
SAM_PINMUX(a, 30, a, periph)
|
|
|
|
/* pa30d_sercom1_pad2 */
|
|
#define PA30D_SERCOM1_PAD2 \
|
|
SAM_PINMUX(a, 30, d, periph)
|
|
|
|
/* pa30e_tcc1_wo0 */
|
|
#define PA30E_TCC1_WO0 \
|
|
SAM_PINMUX(a, 30, e, periph)
|
|
|
|
/* pa30g_swd_clk */
|
|
#define PA30G_SWD_CLK \
|
|
SAM_PINMUX(a, 30, g, periph)
|
|
|
|
/* pa30h_gclk_io0 */
|
|
#define PA30H_GCLK_IO0 \
|
|
SAM_PINMUX(a, 30, h, periph)
|
|
|
|
/* pa31_gpio */
|
|
#define PA31_GPIO \
|
|
SAM_PINMUX(a, 31, gpio, gpio)
|
|
|
|
/* pa31a_eic_extint11 */
|
|
#define PA31A_EIC_EXTINT11 \
|
|
SAM_PINMUX(a, 31, a, periph)
|
|
|
|
/* pa31d_sercom1_pad3 */
|
|
#define PA31D_SERCOM1_PAD3 \
|
|
SAM_PINMUX(a, 31, d, periph)
|
|
|
|
/* pa31e_tcc1_wo1 */
|
|
#define PA31E_TCC1_WO1 \
|
|
SAM_PINMUX(a, 31, e, periph)
|
|
|
|
/* pa31g_swd_io */
|
|
#define PA31G_SWD_IO \
|
|
SAM_PINMUX(a, 31, g, periph)
|
|
|
|
/* pb0_gpio */
|
|
#define PB0_GPIO \
|
|
SAM_PINMUX(b, 0, gpio, gpio)
|
|
|
|
/* pb0a_eic_extint0 */
|
|
#define PB0A_EIC_EXTINT0 \
|
|
SAM_PINMUX(b, 0, a, periph)
|
|
|
|
/* pb0b_adc1_ain0 */
|
|
#define PB0B_ADC1_AIN0 \
|
|
SAM_PINMUX(b, 0, b, periph)
|
|
|
|
/* pb0b_ptc_y6 */
|
|
#define PB0B_PTC_Y6 \
|
|
SAM_PINMUX(b, 0, b, periph)
|
|
|
|
/* pb0d_sercom5_pad2 */
|
|
#define PB0D_SERCOM5_PAD2 \
|
|
SAM_PINMUX(b, 0, d, periph)
|
|
|
|
/* pb0e_tc3_wo0 */
|
|
#define PB0E_TC3_WO0 \
|
|
SAM_PINMUX(b, 0, e, periph)
|
|
|
|
/* pb1_gpio */
|
|
#define PB1_GPIO \
|
|
SAM_PINMUX(b, 1, gpio, gpio)
|
|
|
|
/* pb1a_eic_extint1 */
|
|
#define PB1A_EIC_EXTINT1 \
|
|
SAM_PINMUX(b, 1, a, periph)
|
|
|
|
/* pb1b_adc1_ain1 */
|
|
#define PB1B_ADC1_AIN1 \
|
|
SAM_PINMUX(b, 1, b, periph)
|
|
|
|
/* pb1b_ptc_y7 */
|
|
#define PB1B_PTC_Y7 \
|
|
SAM_PINMUX(b, 1, b, periph)
|
|
|
|
/* pb1d_sercom5_pad3 */
|
|
#define PB1D_SERCOM5_PAD3 \
|
|
SAM_PINMUX(b, 1, d, periph)
|
|
|
|
/* pb1e_tc3_wo1 */
|
|
#define PB1E_TC3_WO1 \
|
|
SAM_PINMUX(b, 1, e, periph)
|
|
|
|
/* pb2_gpio */
|
|
#define PB2_GPIO \
|
|
SAM_PINMUX(b, 2, gpio, gpio)
|
|
|
|
/* pb2a_eic_extint2 */
|
|
#define PB2A_EIC_EXTINT2 \
|
|
SAM_PINMUX(b, 2, a, periph)
|
|
|
|
/* pb2b_adc1_ain2 */
|
|
#define PB2B_ADC1_AIN2 \
|
|
SAM_PINMUX(b, 2, b, periph)
|
|
|
|
/* pb2b_ptc_y8 */
|
|
#define PB2B_PTC_Y8 \
|
|
SAM_PINMUX(b, 2, b, periph)
|
|
|
|
/* pb2d_sercom5_pad0 */
|
|
#define PB2D_SERCOM5_PAD0 \
|
|
SAM_PINMUX(b, 2, d, periph)
|
|
|
|
/* pb2e_tc2_wo0 */
|
|
#define PB2E_TC2_WO0 \
|
|
SAM_PINMUX(b, 2, e, periph)
|
|
|
|
/* pb3_gpio */
|
|
#define PB3_GPIO \
|
|
SAM_PINMUX(b, 3, gpio, gpio)
|
|
|
|
/* pb3a_eic_extint3 */
|
|
#define PB3A_EIC_EXTINT3 \
|
|
SAM_PINMUX(b, 3, a, periph)
|
|
|
|
/* pb3b_adc1_ain3 */
|
|
#define PB3B_ADC1_AIN3 \
|
|
SAM_PINMUX(b, 3, b, periph)
|
|
|
|
/* pb3b_ptc_y9 */
|
|
#define PB3B_PTC_Y9 \
|
|
SAM_PINMUX(b, 3, b, periph)
|
|
|
|
/* pb3d_sercom5_pad1 */
|
|
#define PB3D_SERCOM5_PAD1 \
|
|
SAM_PINMUX(b, 3, d, periph)
|
|
|
|
/* pb3e_tc2_wo1 */
|
|
#define PB3E_TC2_WO1 \
|
|
SAM_PINMUX(b, 3, e, periph)
|
|
|
|
/* pb4_gpio */
|
|
#define PB4_GPIO \
|
|
SAM_PINMUX(b, 4, gpio, gpio)
|
|
|
|
/* pb4a_eic_extint4 */
|
|
#define PB4A_EIC_EXTINT4 \
|
|
SAM_PINMUX(b, 4, a, periph)
|
|
|
|
/* pb4b_adc0_ain6 */
|
|
#define PB4B_ADC0_AIN6 \
|
|
SAM_PINMUX(b, 4, b, periph)
|
|
|
|
/* pb4b_ptc_y10 */
|
|
#define PB4B_PTC_Y10 \
|
|
SAM_PINMUX(b, 4, b, periph)
|
|
|
|
/* pb5_gpio */
|
|
#define PB5_GPIO \
|
|
SAM_PINMUX(b, 5, gpio, gpio)
|
|
|
|
/* pb5a_eic_extint5 */
|
|
#define PB5A_EIC_EXTINT5 \
|
|
SAM_PINMUX(b, 5, a, periph)
|
|
|
|
/* pb5b_adc0_ain7 */
|
|
#define PB5B_ADC0_AIN7 \
|
|
SAM_PINMUX(b, 5, b, periph)
|
|
|
|
/* pb5b_ac_ain6 */
|
|
#define PB5B_AC_AIN6 \
|
|
SAM_PINMUX(b, 5, b, periph)
|
|
|
|
/* pb5b_ptc_y11 */
|
|
#define PB5B_PTC_Y11 \
|
|
SAM_PINMUX(b, 5, b, periph)
|
|
|
|
/* pb6_gpio */
|
|
#define PB6_GPIO \
|
|
SAM_PINMUX(b, 6, gpio, gpio)
|
|
|
|
/* pb6a_eic_extint6 */
|
|
#define PB6A_EIC_EXTINT6 \
|
|
SAM_PINMUX(b, 6, a, periph)
|
|
|
|
/* pb6b_adc0_ain8 */
|
|
#define PB6B_ADC0_AIN8 \
|
|
SAM_PINMUX(b, 6, b, periph)
|
|
|
|
/* pb6b_ac_ain7 */
|
|
#define PB6B_AC_AIN7 \
|
|
SAM_PINMUX(b, 6, b, periph)
|
|
|
|
/* pb6b_ptc_y12 */
|
|
#define PB6B_PTC_Y12 \
|
|
SAM_PINMUX(b, 6, b, periph)
|
|
|
|
/* pb6b_sdadc0_ainn2 */
|
|
#define PB6B_SDADC0_AINN2 \
|
|
SAM_PINMUX(b, 6, b, periph)
|
|
|
|
/* pb7_gpio */
|
|
#define PB7_GPIO \
|
|
SAM_PINMUX(b, 7, gpio, gpio)
|
|
|
|
/* pb7a_eic_extint7 */
|
|
#define PB7A_EIC_EXTINT7 \
|
|
SAM_PINMUX(b, 7, a, periph)
|
|
|
|
/* pb7b_adc0_ain9 */
|
|
#define PB7B_ADC0_AIN9 \
|
|
SAM_PINMUX(b, 7, b, periph)
|
|
|
|
/* pb7b_ptc_y13 */
|
|
#define PB7B_PTC_Y13 \
|
|
SAM_PINMUX(b, 7, b, periph)
|
|
|
|
/* pb7b_sdadc0_ainp2 */
|
|
#define PB7B_SDADC0_AINP2 \
|
|
SAM_PINMUX(b, 7, b, periph)
|
|
|
|
/* pb8_gpio */
|
|
#define PB8_GPIO \
|
|
SAM_PINMUX(b, 8, gpio, gpio)
|
|
|
|
/* pb8a_eic_extint8 */
|
|
#define PB8A_EIC_EXTINT8 \
|
|
SAM_PINMUX(b, 8, a, periph)
|
|
|
|
/* pb8b_adc0_ain2 */
|
|
#define PB8B_ADC0_AIN2 \
|
|
SAM_PINMUX(b, 8, b, periph)
|
|
|
|
/* pb8b_adc1_ain4 */
|
|
#define PB8B_ADC1_AIN4 \
|
|
SAM_PINMUX(b, 8, b, periph)
|
|
|
|
/* pb8b_ptc_y14 */
|
|
#define PB8B_PTC_Y14 \
|
|
SAM_PINMUX(b, 8, b, periph)
|
|
|
|
/* pb8b_sdadc0_ainn1 */
|
|
#define PB8B_SDADC0_AINN1 \
|
|
SAM_PINMUX(b, 8, b, periph)
|
|
|
|
/* pb8d_sercom4_pad0 */
|
|
#define PB8D_SERCOM4_PAD0 \
|
|
SAM_PINMUX(b, 8, d, periph)
|
|
|
|
/* pb8e_tc0_wo0 */
|
|
#define PB8E_TC0_WO0 \
|
|
SAM_PINMUX(b, 8, e, periph)
|
|
|
|
/* pb9_gpio */
|
|
#define PB9_GPIO \
|
|
SAM_PINMUX(b, 9, gpio, gpio)
|
|
|
|
/* pb9a_eic_extint9 */
|
|
#define PB9A_EIC_EXTINT9 \
|
|
SAM_PINMUX(b, 9, a, periph)
|
|
|
|
/* pb9b_adc0_ain3 */
|
|
#define PB9B_ADC0_AIN3 \
|
|
SAM_PINMUX(b, 9, b, periph)
|
|
|
|
/* pb9b_adc1_ain5 */
|
|
#define PB9B_ADC1_AIN5 \
|
|
SAM_PINMUX(b, 9, b, periph)
|
|
|
|
/* pb9b_ptc_y15 */
|
|
#define PB9B_PTC_Y15 \
|
|
SAM_PINMUX(b, 9, b, periph)
|
|
|
|
/* pb9b_sdadc0_ainp1 */
|
|
#define PB9B_SDADC0_AINP1 \
|
|
SAM_PINMUX(b, 9, b, periph)
|
|
|
|
/* pb9d_sercom4_pad1 */
|
|
#define PB9D_SERCOM4_PAD1 \
|
|
SAM_PINMUX(b, 9, d, periph)
|
|
|
|
/* pb9e_tc0_wo1 */
|
|
#define PB9E_TC0_WO1 \
|
|
SAM_PINMUX(b, 9, e, periph)
|
|
|
|
/* pb10_gpio */
|
|
#define PB10_GPIO \
|
|
SAM_PINMUX(b, 10, gpio, gpio)
|
|
|
|
/* pb10a_eic_extint10 */
|
|
#define PB10A_EIC_EXTINT10 \
|
|
SAM_PINMUX(b, 10, a, periph)
|
|
|
|
/* pb10d_sercom4_pad2 */
|
|
#define PB10D_SERCOM4_PAD2 \
|
|
SAM_PINMUX(b, 10, d, periph)
|
|
|
|
/* pb10e_tc1_wo0 */
|
|
#define PB10E_TC1_WO0 \
|
|
SAM_PINMUX(b, 10, e, periph)
|
|
|
|
/* pb10f_tcc0_wo4 */
|
|
#define PB10F_TCC0_WO4 \
|
|
SAM_PINMUX(b, 10, f, periph)
|
|
|
|
/* pb10g_can1_tx */
|
|
#define PB10G_CAN1_TX \
|
|
SAM_PINMUX(b, 10, g, periph)
|
|
|
|
/* pb10h_gclk_io4 */
|
|
#define PB10H_GCLK_IO4 \
|
|
SAM_PINMUX(b, 10, h, periph)
|
|
|
|
/* pb11_gpio */
|
|
#define PB11_GPIO \
|
|
SAM_PINMUX(b, 11, gpio, gpio)
|
|
|
|
/* pb11a_eic_extint11 */
|
|
#define PB11A_EIC_EXTINT11 \
|
|
SAM_PINMUX(b, 11, a, periph)
|
|
|
|
/* pb11d_sercom4_pad3 */
|
|
#define PB11D_SERCOM4_PAD3 \
|
|
SAM_PINMUX(b, 11, d, periph)
|
|
|
|
/* pb11e_tc1_wo1 */
|
|
#define PB11E_TC1_WO1 \
|
|
SAM_PINMUX(b, 11, e, periph)
|
|
|
|
/* pb11f_tcc0_wo5 */
|
|
#define PB11F_TCC0_WO5 \
|
|
SAM_PINMUX(b, 11, f, periph)
|
|
|
|
/* pb11g_can1_rx */
|
|
#define PB11G_CAN1_RX \
|
|
SAM_PINMUX(b, 11, g, periph)
|
|
|
|
/* pb11h_gclk_io5 */
|
|
#define PB11H_GCLK_IO5 \
|
|
SAM_PINMUX(b, 11, h, periph)
|
|
|
|
/* pb12_gpio */
|
|
#define PB12_GPIO \
|
|
SAM_PINMUX(b, 12, gpio, gpio)
|
|
|
|
/* pb12a_eic_extint12 */
|
|
#define PB12A_EIC_EXTINT12 \
|
|
SAM_PINMUX(b, 12, a, periph)
|
|
|
|
/* pb12b_ptc_x12 */
|
|
#define PB12B_PTC_X12 \
|
|
SAM_PINMUX(b, 12, b, periph)
|
|
|
|
/* pb12c_sercom4_pad0 */
|
|
#define PB12C_SERCOM4_PAD0 \
|
|
SAM_PINMUX(b, 12, c, periph)
|
|
|
|
/* pb12e_tc0_wo0 */
|
|
#define PB12E_TC0_WO0 \
|
|
SAM_PINMUX(b, 12, e, periph)
|
|
|
|
/* pb12f_tcc0_wo6 */
|
|
#define PB12F_TCC0_WO6 \
|
|
SAM_PINMUX(b, 12, f, periph)
|
|
|
|
/* pb12h_gclk_io6 */
|
|
#define PB12H_GCLK_IO6 \
|
|
SAM_PINMUX(b, 12, h, periph)
|
|
|
|
/* pb13_gpio */
|
|
#define PB13_GPIO \
|
|
SAM_PINMUX(b, 13, gpio, gpio)
|
|
|
|
/* pb13a_eic_extint13 */
|
|
#define PB13A_EIC_EXTINT13 \
|
|
SAM_PINMUX(b, 13, a, periph)
|
|
|
|
/* pb13b_ptc_x13 */
|
|
#define PB13B_PTC_X13 \
|
|
SAM_PINMUX(b, 13, b, periph)
|
|
|
|
/* pb13c_sercom4_pad1 */
|
|
#define PB13C_SERCOM4_PAD1 \
|
|
SAM_PINMUX(b, 13, c, periph)
|
|
|
|
/* pb13e_tc0_wo1 */
|
|
#define PB13E_TC0_WO1 \
|
|
SAM_PINMUX(b, 13, e, periph)
|
|
|
|
/* pb13f_tcc0_wo7 */
|
|
#define PB13F_TCC0_WO7 \
|
|
SAM_PINMUX(b, 13, f, periph)
|
|
|
|
/* pb13h_gclk_io7 */
|
|
#define PB13H_GCLK_IO7 \
|
|
SAM_PINMUX(b, 13, h, periph)
|
|
|
|
/* pb14_gpio */
|
|
#define PB14_GPIO \
|
|
SAM_PINMUX(b, 14, gpio, gpio)
|
|
|
|
/* pb14a_eic_extint14 */
|
|
#define PB14A_EIC_EXTINT14 \
|
|
SAM_PINMUX(b, 14, a, periph)
|
|
|
|
/* pb14b_ptc_x14 */
|
|
#define PB14B_PTC_X14 \
|
|
SAM_PINMUX(b, 14, b, periph)
|
|
|
|
/* pb14c_sercom4_pad2 */
|
|
#define PB14C_SERCOM4_PAD2 \
|
|
SAM_PINMUX(b, 14, c, periph)
|
|
|
|
/* pb14e_tc1_wo0 */
|
|
#define PB14E_TC1_WO0 \
|
|
SAM_PINMUX(b, 14, e, periph)
|
|
|
|
/* pb14g_can1_tx */
|
|
#define PB14G_CAN1_TX \
|
|
SAM_PINMUX(b, 14, g, periph)
|
|
|
|
/* pb14h_gclk_io0 */
|
|
#define PB14H_GCLK_IO0 \
|
|
SAM_PINMUX(b, 14, h, periph)
|
|
|
|
/* pb15_gpio */
|
|
#define PB15_GPIO \
|
|
SAM_PINMUX(b, 15, gpio, gpio)
|
|
|
|
/* pb15a_eic_extint15 */
|
|
#define PB15A_EIC_EXTINT15 \
|
|
SAM_PINMUX(b, 15, a, periph)
|
|
|
|
/* pb15b_ptc_x15 */
|
|
#define PB15B_PTC_X15 \
|
|
SAM_PINMUX(b, 15, b, periph)
|
|
|
|
/* pb15c_sercom4_pad3 */
|
|
#define PB15C_SERCOM4_PAD3 \
|
|
SAM_PINMUX(b, 15, c, periph)
|
|
|
|
/* pb15e_tc1_wo1 */
|
|
#define PB15E_TC1_WO1 \
|
|
SAM_PINMUX(b, 15, e, periph)
|
|
|
|
/* pb15g_can1_rx */
|
|
#define PB15G_CAN1_RX \
|
|
SAM_PINMUX(b, 15, g, periph)
|
|
|
|
/* pb15h_gclk_io1 */
|
|
#define PB15H_GCLK_IO1 \
|
|
SAM_PINMUX(b, 15, h, periph)
|
|
|
|
/* pb16_gpio */
|
|
#define PB16_GPIO \
|
|
SAM_PINMUX(b, 16, gpio, gpio)
|
|
|
|
/* pb16a_eic_extint0 */
|
|
#define PB16A_EIC_EXTINT0 \
|
|
SAM_PINMUX(b, 16, a, periph)
|
|
|
|
/* pb16c_sercom5_pad0 */
|
|
#define PB16C_SERCOM5_PAD0 \
|
|
SAM_PINMUX(b, 16, c, periph)
|
|
|
|
/* pb16e_tc2_wo0 */
|
|
#define PB16E_TC2_WO0 \
|
|
SAM_PINMUX(b, 16, e, periph)
|
|
|
|
/* pb16f_tcc0_wo4 */
|
|
#define PB16F_TCC0_WO4 \
|
|
SAM_PINMUX(b, 16, f, periph)
|
|
|
|
/* pb16h_gclk_io2 */
|
|
#define PB16H_GCLK_IO2 \
|
|
SAM_PINMUX(b, 16, h, periph)
|
|
|
|
/* pb17_gpio */
|
|
#define PB17_GPIO \
|
|
SAM_PINMUX(b, 17, gpio, gpio)
|
|
|
|
/* pb17a_eic_extint1 */
|
|
#define PB17A_EIC_EXTINT1 \
|
|
SAM_PINMUX(b, 17, a, periph)
|
|
|
|
/* pb17c_sercom5_pad1 */
|
|
#define PB17C_SERCOM5_PAD1 \
|
|
SAM_PINMUX(b, 17, c, periph)
|
|
|
|
/* pb17e_tc2_wo1 */
|
|
#define PB17E_TC2_WO1 \
|
|
SAM_PINMUX(b, 17, e, periph)
|
|
|
|
/* pb17f_tcc0_wo5 */
|
|
#define PB17F_TCC0_WO5 \
|
|
SAM_PINMUX(b, 17, f, periph)
|
|
|
|
/* pb17h_gclk_io3 */
|
|
#define PB17H_GCLK_IO3 \
|
|
SAM_PINMUX(b, 17, h, periph)
|
|
|
|
/* pb22_gpio */
|
|
#define PB22_GPIO \
|
|
SAM_PINMUX(b, 22, gpio, gpio)
|
|
|
|
/* pb22a_eic_extint6 */
|
|
#define PB22A_EIC_EXTINT6 \
|
|
SAM_PINMUX(b, 22, a, periph)
|
|
|
|
/* pb22d_sercom5_pad2 */
|
|
#define PB22D_SERCOM5_PAD2 \
|
|
SAM_PINMUX(b, 22, d, periph)
|
|
|
|
/* pb22e_tc3_wo0 */
|
|
#define PB22E_TC3_WO0 \
|
|
SAM_PINMUX(b, 22, e, periph)
|
|
|
|
/* pb22g_can0_tx */
|
|
#define PB22G_CAN0_TX \
|
|
SAM_PINMUX(b, 22, g, periph)
|
|
|
|
/* pb22h_gclk_io0 */
|
|
#define PB22H_GCLK_IO0 \
|
|
SAM_PINMUX(b, 22, h, periph)
|
|
|
|
/* pb23_gpio */
|
|
#define PB23_GPIO \
|
|
SAM_PINMUX(b, 23, gpio, gpio)
|
|
|
|
/* pb23a_eic_extint7 */
|
|
#define PB23A_EIC_EXTINT7 \
|
|
SAM_PINMUX(b, 23, a, periph)
|
|
|
|
/* pb23d_sercom5_pad3 */
|
|
#define PB23D_SERCOM5_PAD3 \
|
|
SAM_PINMUX(b, 23, d, periph)
|
|
|
|
/* pb23e_tc3_wo1 */
|
|
#define PB23E_TC3_WO1 \
|
|
SAM_PINMUX(b, 23, e, periph)
|
|
|
|
/* pb23g_can0_rx */
|
|
#define PB23G_CAN0_RX \
|
|
SAM_PINMUX(b, 23, g, periph)
|
|
|
|
/* pb23h_gclk_io1 */
|
|
#define PB23H_GCLK_IO1 \
|
|
SAM_PINMUX(b, 23, h, periph)
|
|
|
|
/* pb30_gpio */
|
|
#define PB30_GPIO \
|
|
SAM_PINMUX(b, 30, gpio, gpio)
|
|
|
|
/* pb30a_eic_extint14 */
|
|
#define PB30A_EIC_EXTINT14 \
|
|
SAM_PINMUX(b, 30, a, periph)
|
|
|
|
/* pb30d_sercom5_pad0 */
|
|
#define PB30D_SERCOM5_PAD0 \
|
|
SAM_PINMUX(b, 30, d, periph)
|
|
|
|
/* pb30e_tcc0_wo0 */
|
|
#define PB30E_TCC0_WO0 \
|
|
SAM_PINMUX(b, 30, e, periph)
|
|
|
|
/* pb30f_tcc1_wo2 */
|
|
#define PB30F_TCC1_WO2 \
|
|
SAM_PINMUX(b, 30, f, periph)
|
|
|
|
/* pb30h_ac_cmp2 */
|
|
#define PB30H_AC_CMP2 \
|
|
SAM_PINMUX(b, 30, h, periph)
|
|
|
|
/* pb31_gpio */
|
|
#define PB31_GPIO \
|
|
SAM_PINMUX(b, 31, gpio, gpio)
|
|
|
|
/* pb31a_eic_extint15 */
|
|
#define PB31A_EIC_EXTINT15 \
|
|
SAM_PINMUX(b, 31, a, periph)
|
|
|
|
/* pb31d_sercom5_pad1 */
|
|
#define PB31D_SERCOM5_PAD1 \
|
|
SAM_PINMUX(b, 31, d, periph)
|
|
|
|
/* pb31e_tcc0_wo1 */
|
|
#define PB31E_TCC0_WO1 \
|
|
SAM_PINMUX(b, 31, e, periph)
|
|
|
|
/* pb31f_tcc1_wo3 */
|
|
#define PB31F_TCC1_WO3 \
|
|
SAM_PINMUX(b, 31, f, periph)
|
|
|
|
/* pb31h_ac_cmp3 */
|
|
#define PB31H_AC_CMP3 \
|
|
SAM_PINMUX(b, 31, h, periph)
|