100 lines
1.9 KiB
C
100 lines
1.9 KiB
C
/* Copyright (c) 2011-2012 Tensilica Inc. ALL RIGHTS RESERVED.
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// These coded instructions, statements, and computer programs are the
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// copyrighted works and confidential proprietary information of Tensilica Inc.
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// They may not be modified, copied, reproduced, distributed, or disclosed to
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// third parties in any manner, medium, or form, in whole or in part, without
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// the prior written consent of Tensilica Inc.
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*/
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#ifndef _JTAG_XTENSA_H_
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#define _JTAG_XTENSA_H_
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/* ---------------- JTAG registers ------------------ */
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/* -- ER and later JTAG registers */
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typedef enum {
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regIR,
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regBypass,
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regNAR,
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regNDR,
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regIdcode,
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regPWRCTL,
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regPWRSTAT,
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regJtagMAX,
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} xtensaJtagReg;
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/* -- pre-ER JTAG registers */
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typedef enum {
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regOldIR,
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regOldBypass,
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regOldDIRW,
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regOldDIR,
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regOldDDR,
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regOldDOSR,
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regOldESR,
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regOldDCR,
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regOldTraxNDR,
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regOldTraxNAR,
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regOldMAX
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} xtensaOldJtagReg;
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/* ---------------- JTAG Instructions ------------------ */
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/* -- pre-ER JTAG instructions */
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typedef enum {
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ji_EnableOCD = 0x11,
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ji_DebugInt,
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ji_RetDebugInt, // TBD: remove
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ji_DisRetOCD, // TBD: remove
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ji_ExecuteDI,
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ji_LoadDI,
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ji_ScanDDR,
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ji_ReadDOSR,
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ji_ScanDCR,
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ji_LoadWDI,
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ji_TRAX = 0x1c,
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ji_BYPASS = 0x1f,
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} xtensaJtagInstruction;
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typedef enum {
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OCDNormalMode,
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OCDRunMode,
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OCDHaltMode,
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OCDStepMode
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} xtensaMode;
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typedef struct {
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xtensaMode mode;
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int DRsel;
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XTMP_core core;
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XTMP_tap tap;
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int core_num;
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jtagReg_t *jtagRegs;
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void *dap; // used for ARM DAP only
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bool isBig;
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int dir_array_option; // used by pre-ER devices only
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// for testing, below - FIXME - delete later
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int ocdReg;
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unsigned int wr_data;
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XTMP_event start_OCD_trans;
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bool data_cycle;
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bool data_pending;
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} coreSlaveData_t;
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enum OCD_ACCESS_TYPE{
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NEXUS_ACCESS,
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CS_ACCESS,
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};
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// pre-ER Xtensa initializiation
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EXTERN XTMP_deviceStatus
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XTMP_jtagCoreSlaveEX(XTMP_component component, XTMP_jtagSlave slave, void* mydata);
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extern char *OCDrd;
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extern char *OCDwr;
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#endif
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