143 lines
3.6 KiB
C
143 lines
3.6 KiB
C
/*-------------------------------------------------------------------------
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*
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* generic-xlc.h
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* Atomic operations for IBM's CC
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*
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* Portions Copyright (c) 2013-2019, PostgreSQL Global Development Group
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*
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* NOTES:
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*
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* Documentation:
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* * Synchronization and atomic built-in functions
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* http://www-01.ibm.com/support/knowledgecenter/SSGH3R_13.1.2/com.ibm.xlcpp131.aix.doc/compiler_ref/bifs_sync_atomic.html
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*
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* src/include/port/atomics/generic-xlc.h
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*
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* -------------------------------------------------------------------------
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*/
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#if defined(HAVE_ATOMICS)
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#define PG_HAVE_ATOMIC_U32_SUPPORT
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typedef struct pg_atomic_uint32
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{
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volatile uint32 value;
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} pg_atomic_uint32;
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/* 64bit atomics are only supported in 64bit mode */
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#ifdef __64BIT__
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#define PG_HAVE_ATOMIC_U64_SUPPORT
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typedef struct pg_atomic_uint64
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{
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volatile uint64 value pg_attribute_aligned(8);
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} pg_atomic_uint64;
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#endif /* __64BIT__ */
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#define PG_HAVE_ATOMIC_COMPARE_EXCHANGE_U32
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static inline bool
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pg_atomic_compare_exchange_u32_impl(volatile pg_atomic_uint32 *ptr,
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uint32 *expected, uint32 newval)
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{
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bool ret;
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/*
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* atomics.h specifies sequential consistency ("full barrier semantics")
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* for this interface. Since "lwsync" provides acquire/release
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* consistency only, do not use it here. GCC atomics observe the same
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* restriction; see its rs6000_pre_atomic_barrier().
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*/
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__asm__ __volatile__ (" sync \n" ::: "memory");
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/*
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* XXX: __compare_and_swap is defined to take signed parameters, but that
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* shouldn't matter since we don't perform any arithmetic operations.
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*/
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ret = __compare_and_swap((volatile int*)&ptr->value,
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(int *)expected, (int)newval);
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/*
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* xlc's documentation tells us:
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* "If __compare_and_swap is used as a locking primitive, insert a call to
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* the __isync built-in function at the start of any critical sections."
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*
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* The critical section begins immediately after __compare_and_swap().
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*/
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__isync();
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return ret;
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}
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#define PG_HAVE_ATOMIC_FETCH_ADD_U32
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static inline uint32
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pg_atomic_fetch_add_u32_impl(volatile pg_atomic_uint32 *ptr, int32 add_)
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{
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uint32 _t;
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uint32 res;
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/*
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* xlc has a no-longer-documented __fetch_and_add() intrinsic. In xlc
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* 12.01.0000.0000, it emits a leading "sync" and trailing "isync". In
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* xlc 13.01.0003.0004, it emits neither. Hence, using the intrinsic
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* would add redundant syncs on xlc 12.
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*/
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__asm__ __volatile__(
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" sync \n"
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" lwarx %1,0,%4 \n"
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" add %0,%1,%3 \n"
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" stwcx. %0,0,%4 \n"
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" bne $-12 \n" /* branch to lwarx */
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" isync \n"
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: "=&r"(_t), "=&r"(res), "+m"(ptr->value)
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: "r"(add_), "r"(&ptr->value)
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: "memory", "cc");
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return res;
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}
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#ifdef PG_HAVE_ATOMIC_U64_SUPPORT
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#define PG_HAVE_ATOMIC_COMPARE_EXCHANGE_U64
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static inline bool
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pg_atomic_compare_exchange_u64_impl(volatile pg_atomic_uint64 *ptr,
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uint64 *expected, uint64 newval)
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{
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bool ret;
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__asm__ __volatile__ (" sync \n" ::: "memory");
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ret = __compare_and_swaplp((volatile long*)&ptr->value,
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(long *)expected, (long)newval);
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__isync();
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return ret;
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}
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#define PG_HAVE_ATOMIC_FETCH_ADD_U64
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static inline uint64
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pg_atomic_fetch_add_u64_impl(volatile pg_atomic_uint64 *ptr, int64 add_)
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{
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uint64 _t;
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uint64 res;
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/* Like u32, but s/lwarx/ldarx/; s/stwcx/stdcx/ */
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__asm__ __volatile__(
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" sync \n"
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" ldarx %1,0,%4 \n"
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" add %0,%1,%3 \n"
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" stdcx. %0,0,%4 \n"
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" bne $-12 \n" /* branch to ldarx */
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" isync \n"
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: "=&r"(_t), "=&r"(res), "+m"(ptr->value)
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: "r"(add_), "r"(&ptr->value)
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: "memory", "cc");
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return res;
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}
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#endif /* PG_HAVE_ATOMIC_U64_SUPPORT */
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#endif /* defined(HAVE_ATOMICS) */
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