22 lines
420 B
Makefile
22 lines
420 B
Makefile
# Created by: Ying-Chieh Liao <ijliao@FreeBSD.org>
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# $FreeBSD$
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PORTNAME= iverilog
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PORTVERSION= 10.2
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PORTREVISION= 1
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CATEGORIES= cad
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MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v10/
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DISTNAME= verilog-${PORTVERSION}
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MAINTAINER= zeising@FreeBSD.org
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COMMENT= Verilog simulation and synthesis tool
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LICENSE= GPLv2
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GNU_CONFIGURE= yes
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CONFIGURE_ARGS= --disable-suffix
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USES= bison gmake readline
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.include <bsd.port.mk>
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