36 lines
1.0 KiB
Makefile
36 lines
1.0 KiB
Makefile
PORTNAME= qflow
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DISTVERSION= 1.4.96
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CATEGORIES= cad
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MAINTAINER= yuri@FreeBSD.org
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COMMENT= End-to-end digital synthesis flow for ASIC designs
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LICENSE= GPLv2
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APP_DEPENDS= abc:cad/abc \
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graywolf:cad/graywolf \
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magic>0:cad/magic \
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netgen-lvs>0:cad/netgen-lvs \
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qrouter>0:cad/qrouter \
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sta:cad/openroad \
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yosys>0:cad/yosys
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BUILD_DEPENDS= ${APP_DEPENDS}
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RUN_DEPENDS= ${APP_DEPENDS}
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USES= gmake python tar:tgz tcl tk
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USE_GITHUB= yes
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GH_ACCOUNT= RTimothyEdwards
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GNU_CONFIGURE= yes
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post-patch:
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@${REINPLACE_CMD} -e 's|^#!ENV_PATH python3$$|#!${PYTHON_CMD}|' ${WRKSRC}/scripts/*.py.in
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@${REINPLACE_CMD} -e 's|^#!TCLSH_PATH$$|#!${TCLSH}|' ${WRKSRC}/scripts/*.tcl.in
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post-install:
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@cd ${STAGEDIR}${PREFIX}/share/qflow/bin && \
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${STRIP_CMD} vlog2Spice vlog2Verilog vlog2Def vlog2Cel vlogFanout DEF2Verilog addspacers vesta spice2delay rc2dly blif2BSpice blif2Verilog blifFanout && \
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${RM} yosys-abc && ${LN} -s ${LOCALBASE}/bin/abc yosys-abc # https://github.com/RTimothyEdwards/qflow/issues/6
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.include <bsd.port.mk>
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