700 lines
22 KiB
C
700 lines
22 KiB
C
// Low level AHCI disk access
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//
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// Copyright (C) 2010 Gerd Hoffmann <kraxel@redhat.com>
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//
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// This file may be distributed under the terms of the GNU LGPLv3 license.
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#include "ahci.h" // CDB_CMD_READ_10
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#include "ata.h" // ATA_CB_STAT
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#include "biosvar.h" // GET_GLOBAL
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#include "blockcmd.h" // CDB_CMD_READ_10
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#include "malloc.h" // free
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#include "output.h" // dprintf
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#include "pci.h" // pci_config_readb
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#include "pcidevice.h" // foreachpci
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#include "pci_ids.h" // PCI_CLASS_STORAGE_OTHER
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#include "pci_regs.h" // PCI_INTERRUPT_LINE
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#include "stacks.h" // yield
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#include "std/disk.h" // DISK_RET_SUCCESS
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#include "string.h" // memset
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#include "util.h" // timer_calc
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#include "x86.h" // inb
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#define AHCI_REQUEST_TIMEOUT 32000 // 32 seconds max for IDE ops
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#define AHCI_RESET_TIMEOUT 500 // 500 miliseconds
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#define AHCI_LINK_TIMEOUT 10 // 10 miliseconds
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// prepare sata command fis
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static void sata_prep_simple(struct sata_cmd_fis *fis, u8 command)
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{
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memset_fl(fis, 0, sizeof(*fis));
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fis->command = command;
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}
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static void sata_prep_readwrite(struct sata_cmd_fis *fis,
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struct disk_op_s *op, int iswrite)
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{
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u64 lba = op->lba;
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u8 command;
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memset_fl(fis, 0, sizeof(*fis));
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if (op->count >= (1<<8) || lba + op->count >= (1<<28)) {
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fis->sector_count2 = op->count >> 8;
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fis->lba_low2 = lba >> 24;
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fis->lba_mid2 = lba >> 32;
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fis->lba_high2 = lba >> 40;
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lba &= 0xffffff;
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command = (iswrite ? ATA_CMD_WRITE_DMA_EXT
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: ATA_CMD_READ_DMA_EXT);
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} else {
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command = (iswrite ? ATA_CMD_WRITE_DMA
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: ATA_CMD_READ_DMA);
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}
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fis->feature = 1; /* dma */
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fis->command = command;
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fis->sector_count = op->count;
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fis->lba_low = lba;
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fis->lba_mid = lba >> 8;
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fis->lba_high = lba >> 16;
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fis->device = ((lba >> 24) & 0xf) | ATA_CB_DH_LBA;
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}
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static void sata_prep_atapi(struct sata_cmd_fis *fis, u16 blocksize)
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{
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memset_fl(fis, 0, sizeof(*fis));
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fis->command = ATA_CMD_PACKET;
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fis->feature = 1; /* dma */
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fis->lba_mid = blocksize;
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fis->lba_high = blocksize >> 8;
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}
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// ahci register access helpers
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static u32 ahci_ctrl_readl(struct ahci_ctrl_s *ctrl, u32 reg)
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{
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return readl(ctrl->iobase + reg);
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}
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static void ahci_ctrl_writel(struct ahci_ctrl_s *ctrl, u32 reg, u32 val)
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{
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writel(ctrl->iobase + reg, val);
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}
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static u32 ahci_port_to_ctrl(u32 pnr, u32 port_reg)
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{
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u32 ctrl_reg = 0x100;
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ctrl_reg += pnr * 0x80;
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ctrl_reg += port_reg;
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return ctrl_reg;
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}
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static u32 ahci_port_readl(struct ahci_ctrl_s *ctrl, u32 pnr, u32 reg)
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{
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u32 ctrl_reg = ahci_port_to_ctrl(pnr, reg);
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return ahci_ctrl_readl(ctrl, ctrl_reg);
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}
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static void ahci_port_writel(struct ahci_ctrl_s *ctrl, u32 pnr, u32 reg, u32 val)
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{
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u32 ctrl_reg = ahci_port_to_ctrl(pnr, reg);
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ahci_ctrl_writel(ctrl, ctrl_reg, val);
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}
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// submit ahci command + wait for result
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static int ahci_command(struct ahci_port_s *port_gf, int iswrite, int isatapi,
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void *buffer, u32 bsize)
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{
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u32 val, status, success, flags, intbits, error;
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struct ahci_ctrl_s *ctrl = port_gf->ctrl;
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struct ahci_cmd_s *cmd = port_gf->cmd;
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struct ahci_fis_s *fis = port_gf->fis;
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struct ahci_list_s *list = port_gf->list;
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u32 pnr = port_gf->pnr;
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cmd->fis.reg = 0x27;
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cmd->fis.pmp_type = 1 << 7; /* cmd fis */
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cmd->prdt[0].base = (u32)buffer;
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cmd->prdt[0].baseu = 0;
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cmd->prdt[0].flags = bsize-1;
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flags = ((1 << 16) | /* one prd entry */
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(iswrite ? (1 << 6) : 0) |
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(isatapi ? (1 << 5) : 0) |
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(5 << 0)); /* fis length (dwords) */
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list[0].flags = flags;
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list[0].bytes = 0;
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list[0].base = (u32)(cmd);
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list[0].baseu = 0;
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dprintf(8, "AHCI/%d: send cmd ...\n", pnr);
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intbits = ahci_port_readl(ctrl, pnr, PORT_IRQ_STAT);
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if (intbits)
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ahci_port_writel(ctrl, pnr, PORT_IRQ_STAT, intbits);
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ahci_port_writel(ctrl, pnr, PORT_CMD_ISSUE, 1);
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u32 end = timer_calc(AHCI_REQUEST_TIMEOUT);
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do {
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for (;;) {
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intbits = ahci_port_readl(ctrl, pnr, PORT_IRQ_STAT);
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if (intbits) {
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ahci_port_writel(ctrl, pnr, PORT_IRQ_STAT, intbits);
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if (intbits & 0x02) {
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status = GET_LOWFLAT(fis->psfis[2]);
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error = GET_LOWFLAT(fis->psfis[3]);
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break;
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}
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if (intbits & 0x01) {
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status = GET_LOWFLAT(fis->rfis[2]);
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error = GET_LOWFLAT(fis->rfis[3]);
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break;
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}
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}
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if (timer_check(end)) {
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warn_timeout();
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return -1;
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}
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yield();
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}
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dprintf(8, "AHCI/%d: ... intbits 0x%x, status 0x%x ...\n",
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pnr, intbits, status);
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} while (status & ATA_CB_STAT_BSY);
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success = (0x00 == (status & (ATA_CB_STAT_BSY | ATA_CB_STAT_DF |
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ATA_CB_STAT_ERR)) &&
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ATA_CB_STAT_RDY == (status & (ATA_CB_STAT_RDY)));
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if (success) {
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dprintf(8, "AHCI/%d: ... finished, status 0x%x, OK\n", pnr,
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status);
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} else {
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dprintf(2, "AHCI/%d: ... finished, status 0x%x, ERROR 0x%x\n", pnr,
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status, error);
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// non-queued error recovery (AHCI 1.3 section 6.2.2.1)
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// Clears PxCMD.ST to 0 to reset the PxCI register
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val = ahci_port_readl(ctrl, pnr, PORT_CMD);
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ahci_port_writel(ctrl, pnr, PORT_CMD, val & ~PORT_CMD_START);
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// waits for PxCMD.CR to clear to 0
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while (1) {
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val = ahci_port_readl(ctrl, pnr, PORT_CMD);
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if ((val & PORT_CMD_LIST_ON) == 0)
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break;
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yield();
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}
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// Clears any error bits in PxSERR to enable capturing new errors
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val = ahci_port_readl(ctrl, pnr, PORT_SCR_ERR);
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ahci_port_writel(ctrl, pnr, PORT_SCR_ERR, val);
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// Clears status bits in PxIS as appropriate
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val = ahci_port_readl(ctrl, pnr, PORT_IRQ_STAT);
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ahci_port_writel(ctrl, pnr, PORT_IRQ_STAT, val);
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// If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to 1, issue
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// a COMRESET to the device to put it in an idle state
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val = ahci_port_readl(ctrl, pnr, PORT_TFDATA);
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if (val & (ATA_CB_STAT_BSY | ATA_CB_STAT_DRQ)) {
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dprintf(2, "AHCI/%d: issue comreset\n", pnr);
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val = ahci_port_readl(ctrl, pnr, PORT_SCR_CTL);
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// set Device Detection Initialization (DET) to 1 for 1 ms for comreset
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ahci_port_writel(ctrl, pnr, PORT_SCR_CTL, val | 1);
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mdelay (1);
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ahci_port_writel(ctrl, pnr, PORT_SCR_CTL, val);
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}
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// Sets PxCMD.ST to 1 to enable issuing new commands
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val = ahci_port_readl(ctrl, pnr, PORT_CMD);
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ahci_port_writel(ctrl, pnr, PORT_CMD, val | PORT_CMD_START);
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}
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return success ? 0 : -1;
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}
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#define CDROM_CDB_SIZE 12
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int ahci_atapi_process_op(struct disk_op_s *op)
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{
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if (! CONFIG_AHCI)
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return 0;
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struct ahci_port_s *port_gf = container_of(
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op->drive_fl, struct ahci_port_s, drive);
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struct ahci_cmd_s *cmd = port_gf->cmd;
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if (op->command == CMD_WRITE || op->command == CMD_FORMAT)
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return DISK_RET_EWRITEPROTECT;
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int blocksize = scsi_fill_cmd(op, cmd->atapi, CDROM_CDB_SIZE);
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if (blocksize < 0)
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return default_process_op(op);
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sata_prep_atapi(&cmd->fis, blocksize);
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int rc = ahci_command(port_gf, 0, 1, op->buf_fl, op->count * blocksize);
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if (rc < 0)
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return DISK_RET_EBADTRACK;
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return DISK_RET_SUCCESS;
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}
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// read/write count blocks from a harddrive, op->buf_fl must be word aligned
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static int
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ahci_disk_readwrite_aligned(struct disk_op_s *op, int iswrite)
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{
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struct ahci_port_s *port_gf = container_of(
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op->drive_fl, struct ahci_port_s, drive);
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struct ahci_cmd_s *cmd = port_gf->cmd;
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int rc;
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sata_prep_readwrite(&cmd->fis, op, iswrite);
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rc = ahci_command(port_gf, iswrite, 0, op->buf_fl,
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op->count * DISK_SECTOR_SIZE);
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dprintf(8, "ahci disk %s, lba %6x, count %3x, buf %p, rc %d\n",
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iswrite ? "write" : "read", (u32)op->lba, op->count, op->buf_fl, rc);
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if (rc < 0)
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return DISK_RET_EBADTRACK;
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return DISK_RET_SUCCESS;
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}
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// read/write count blocks from a harddrive.
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static int
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ahci_disk_readwrite(struct disk_op_s *op, int iswrite)
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{
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// if caller's buffer is word aligned, use it directly
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if (((u32) op->buf_fl & 1) == 0)
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return ahci_disk_readwrite_aligned(op, iswrite);
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// Use a word aligned buffer for AHCI I/O
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int rc;
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struct disk_op_s localop = *op;
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u8 *alignedbuf_fl = bounce_buf_fl;
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u8 *position = op->buf_fl;
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localop.buf_fl = alignedbuf_fl;
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localop.count = 1;
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if (iswrite) {
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u16 block;
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for (block = 0; block < op->count; block++) {
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memcpy_fl (alignedbuf_fl, position, DISK_SECTOR_SIZE);
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rc = ahci_disk_readwrite_aligned (&localop, 1);
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if (rc)
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return rc;
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position += DISK_SECTOR_SIZE;
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localop.lba++;
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}
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} else { // read
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u16 block;
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for (block = 0; block < op->count; block++) {
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rc = ahci_disk_readwrite_aligned (&localop, 0);
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if (rc)
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return rc;
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memcpy_fl (position, alignedbuf_fl, DISK_SECTOR_SIZE);
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position += DISK_SECTOR_SIZE;
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localop.lba++;
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}
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}
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return DISK_RET_SUCCESS;
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}
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// command demuxer
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int
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ahci_process_op(struct disk_op_s *op)
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{
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if (!CONFIG_AHCI)
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return 0;
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switch (op->command) {
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case CMD_READ:
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return ahci_disk_readwrite(op, 0);
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case CMD_WRITE:
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return ahci_disk_readwrite(op, 1);
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default:
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return default_process_op(op);
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}
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}
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static void
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ahci_port_reset(struct ahci_ctrl_s *ctrl, u32 pnr)
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{
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u32 val;
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/* disable FIS + CMD */
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u32 end = timer_calc(AHCI_RESET_TIMEOUT);
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for (;;) {
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val = ahci_port_readl(ctrl, pnr, PORT_CMD);
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if (!(val & (PORT_CMD_FIS_RX | PORT_CMD_START |
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PORT_CMD_FIS_ON | PORT_CMD_LIST_ON)))
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break;
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val &= ~(PORT_CMD_FIS_RX | PORT_CMD_START);
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ahci_port_writel(ctrl, pnr, PORT_CMD, val);
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if (timer_check(end)) {
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warn_timeout();
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break;
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}
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yield();
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}
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/* disable + clear IRQs */
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ahci_port_writel(ctrl, pnr, PORT_IRQ_MASK, 0);
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val = ahci_port_readl(ctrl, pnr, PORT_IRQ_STAT);
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if (val)
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ahci_port_writel(ctrl, pnr, PORT_IRQ_STAT, val);
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}
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static struct ahci_port_s*
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ahci_port_alloc(struct ahci_ctrl_s *ctrl, u32 pnr)
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{
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struct ahci_port_s *port = malloc_tmp(sizeof(*port));
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if (!port) {
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warn_noalloc();
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return NULL;
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}
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memset(port, 0, sizeof(*port));
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port->pnr = pnr;
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port->ctrl = ctrl;
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port->list = memalign_tmp(1024, 1024);
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port->fis = memalign_tmp(256, 256);
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port->cmd = memalign_tmp(256, 256);
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if (port->list == NULL || port->fis == NULL || port->cmd == NULL) {
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warn_noalloc();
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return NULL;
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}
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memset(port->list, 0, 1024);
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memset(port->fis, 0, 256);
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memset(port->cmd, 0, 256);
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ahci_port_writel(ctrl, pnr, PORT_LST_ADDR, (u32)port->list);
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ahci_port_writel(ctrl, pnr, PORT_FIS_ADDR, (u32)port->fis);
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if (ctrl->caps & HOST_CAP_64) {
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ahci_port_writel(ctrl, pnr, PORT_LST_ADDR_HI, 0);
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ahci_port_writel(ctrl, pnr, PORT_FIS_ADDR_HI, 0);
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}
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return port;
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}
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static void ahci_port_release(struct ahci_port_s *port)
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{
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ahci_port_reset(port->ctrl, port->pnr);
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free(port->list);
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free(port->fis);
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free(port->cmd);
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free(port);
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}
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static struct ahci_port_s* ahci_port_realloc(struct ahci_port_s *port)
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{
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struct ahci_port_s *tmp;
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u32 cmd;
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tmp = malloc_fseg(sizeof(*port));
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if (!tmp) {
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warn_noalloc();
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ahci_port_release(port);
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return NULL;
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}
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*tmp = *port;
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free(port);
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port = tmp;
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ahci_port_reset(port->ctrl, port->pnr);
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free(port->list);
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free(port->fis);
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free(port->cmd);
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port->list = memalign_high(1024, 1024);
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port->fis = memalign_high(256, 256);
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port->cmd = memalign_high(256, 256);
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if (!port->list || !port->fis || !port->cmd) {
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warn_noalloc();
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free(port->list);
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free(port->fis);
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free(port->cmd);
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free(port);
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return NULL;
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}
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ahci_port_writel(port->ctrl, port->pnr, PORT_LST_ADDR, (u32)port->list);
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ahci_port_writel(port->ctrl, port->pnr, PORT_FIS_ADDR, (u32)port->fis);
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cmd = ahci_port_readl(port->ctrl, port->pnr, PORT_CMD);
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cmd |= (PORT_CMD_FIS_RX|PORT_CMD_START);
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ahci_port_writel(port->ctrl, port->pnr, PORT_CMD, cmd);
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return port;
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}
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#define MAXMODEL 40
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/* See ahci spec chapter 10.1 "Software Initialization of HBA" */
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static int ahci_port_setup(struct ahci_port_s *port)
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{
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struct ahci_ctrl_s *ctrl = port->ctrl;
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u32 pnr = port->pnr;
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char model[MAXMODEL+1];
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u16 buffer[256];
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u32 cmd, stat, err, tf;
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int rc;
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/* enable FIS recv */
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cmd = ahci_port_readl(ctrl, pnr, PORT_CMD);
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cmd |= PORT_CMD_FIS_RX;
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ahci_port_writel(ctrl, pnr, PORT_CMD, cmd);
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/* spin up */
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cmd |= PORT_CMD_SPIN_UP;
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ahci_port_writel(ctrl, pnr, PORT_CMD, cmd);
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u32 end = timer_calc(AHCI_LINK_TIMEOUT);
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for (;;) {
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stat = ahci_port_readl(ctrl, pnr, PORT_SCR_STAT);
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if ((stat & 0x07) == 0x03) {
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dprintf(2, "AHCI/%d: link up\n", port->pnr);
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break;
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}
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if (timer_check(end)) {
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dprintf(2, "AHCI/%d: link down\n", port->pnr);
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return -1;
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}
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yield();
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}
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/* clear error status */
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err = ahci_port_readl(ctrl, pnr, PORT_SCR_ERR);
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if (err)
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ahci_port_writel(ctrl, pnr, PORT_SCR_ERR, err);
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/* wait for device becoming ready */
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end = timer_calc(AHCI_REQUEST_TIMEOUT);
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for (;;) {
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tf = ahci_port_readl(ctrl, pnr, PORT_TFDATA);
|
|
if (!(tf & (ATA_CB_STAT_BSY |
|
|
ATA_CB_STAT_DRQ)))
|
|
break;
|
|
if (timer_check(end)) {
|
|
warn_timeout();
|
|
dprintf(1, "AHCI/%d: device not ready (tf 0x%x)\n", port->pnr, tf);
|
|
return -1;
|
|
}
|
|
yield();
|
|
}
|
|
|
|
/* start device */
|
|
cmd |= PORT_CMD_START;
|
|
ahci_port_writel(ctrl, pnr, PORT_CMD, cmd);
|
|
|
|
sata_prep_simple(&port->cmd->fis, ATA_CMD_IDENTIFY_PACKET_DEVICE);
|
|
rc = ahci_command(port, 0, 0, buffer, sizeof(buffer));
|
|
if (rc == 0) {
|
|
port->atapi = 1;
|
|
} else {
|
|
port->atapi = 0;
|
|
sata_prep_simple(&port->cmd->fis, ATA_CMD_IDENTIFY_DEVICE);
|
|
rc = ahci_command(port, 0, 0, buffer, sizeof(buffer));
|
|
if (rc < 0)
|
|
return -1;
|
|
}
|
|
|
|
port->drive.cntl_id = pnr;
|
|
port->drive.removable = (buffer[0] & 0x80) ? 1 : 0;
|
|
|
|
if (!port->atapi) {
|
|
// found disk (ata)
|
|
port->drive.type = DTYPE_AHCI;
|
|
port->drive.blksize = DISK_SECTOR_SIZE;
|
|
port->drive.pchs.cylinder = buffer[1];
|
|
port->drive.pchs.head = buffer[3];
|
|
port->drive.pchs.sector = buffer[6];
|
|
|
|
u64 sectors;
|
|
if (buffer[83] & (1 << 10)) // word 83 - lba48 support
|
|
sectors = *(u64*)&buffer[100]; // word 100-103
|
|
else
|
|
sectors = *(u32*)&buffer[60]; // word 60 and word 61
|
|
port->drive.sectors = sectors;
|
|
u64 adjsize = sectors >> 11;
|
|
char adjprefix = 'M';
|
|
if (adjsize >= (1 << 16)) {
|
|
adjsize >>= 10;
|
|
adjprefix = 'G';
|
|
}
|
|
port->desc = znprintf(MAXDESCSIZE
|
|
, "AHCI/%d: %s ATA-%d Hard-Disk (%u %ciBytes)"
|
|
, port->pnr
|
|
, ata_extract_model(model, MAXMODEL, buffer)
|
|
, ata_extract_version(buffer)
|
|
, (u32)adjsize, adjprefix);
|
|
port->prio = bootprio_find_ata_device(ctrl->pci_tmp, pnr, 0);
|
|
|
|
s8 multi_dma = -1;
|
|
s8 pio_mode = -1;
|
|
s8 udma_mode = -1;
|
|
// If bit 2 in word 53 is set, udma information is valid in word 88.
|
|
if (buffer[53] & 0x04) {
|
|
udma_mode = 6;
|
|
while ((udma_mode >= 0) &&
|
|
!((buffer[88] & 0x7f) & ( 1 << udma_mode ))) {
|
|
udma_mode--;
|
|
}
|
|
}
|
|
// If bit 1 in word 53 is set, multiword-dma and advanced pio modes
|
|
// are available in words 63 and 64.
|
|
if (buffer[53] & 0x02) {
|
|
pio_mode = 4;
|
|
multi_dma = 3;
|
|
while ((multi_dma >= 0) &&
|
|
!((buffer[63] & 0x7) & ( 1 << multi_dma ))) {
|
|
multi_dma--;
|
|
}
|
|
while ((pio_mode >= 3) &&
|
|
!((buffer[64] & 0x3) & ( 1 << ( pio_mode - 3 ) ))) {
|
|
pio_mode--;
|
|
}
|
|
}
|
|
dprintf(2, "AHCI/%d: supported modes: udma %d, multi-dma %d, pio %d\n",
|
|
port->pnr, udma_mode, multi_dma, pio_mode);
|
|
|
|
sata_prep_simple(&port->cmd->fis, ATA_CMD_SET_FEATURES);
|
|
port->cmd->fis.feature = ATA_SET_FEATRUE_TRANSFER_MODE;
|
|
// Select used mode. UDMA first, then Multi-DMA followed by
|
|
// advanced PIO modes 3 or 4. If non, set default PIO.
|
|
if (udma_mode >= 0) {
|
|
dprintf(1, "AHCI/%d: Set transfer mode to UDMA-%d\n",
|
|
port->pnr, udma_mode);
|
|
port->cmd->fis.sector_count = ATA_TRANSFER_MODE_ULTRA_DMA
|
|
| udma_mode;
|
|
} else if (multi_dma >= 0) {
|
|
dprintf(1, "AHCI/%d: Set transfer mode to Multi-DMA-%d\n",
|
|
port->pnr, multi_dma);
|
|
port->cmd->fis.sector_count = ATA_TRANSFER_MODE_MULTIWORD_DMA
|
|
| multi_dma;
|
|
} else if (pio_mode >= 3) {
|
|
dprintf(1, "AHCI/%d: Set transfer mode to PIO-%d\n",
|
|
port->pnr, pio_mode);
|
|
port->cmd->fis.sector_count = ATA_TRANSFER_MODE_PIO_FLOW_CTRL
|
|
| pio_mode;
|
|
} else {
|
|
dprintf(1, "AHCI/%d: Set transfer mode to default PIO\n",
|
|
port->pnr);
|
|
port->cmd->fis.sector_count = ATA_TRANSFER_MODE_DEFAULT_PIO;
|
|
}
|
|
rc = ahci_command(port, 1, 0, 0, 0);
|
|
if (rc < 0) {
|
|
dprintf(1, "AHCI/%d: Set transfer mode failed.\n", port->pnr);
|
|
}
|
|
} else {
|
|
// found cdrom (atapi)
|
|
port->drive.type = DTYPE_AHCI_ATAPI;
|
|
port->drive.blksize = CDROM_SECTOR_SIZE;
|
|
port->drive.sectors = (u64)-1;
|
|
u8 iscd = ((buffer[0] >> 8) & 0x1f) == 0x05;
|
|
if (!iscd) {
|
|
dprintf(1, "AHCI/%d: atapi device isn't a cdrom\n", port->pnr);
|
|
return -1;
|
|
}
|
|
port->desc = znprintf(MAXDESCSIZE
|
|
, "DVD/CD [AHCI/%d: %s ATAPI-%d DVD/CD]"
|
|
, port->pnr
|
|
, ata_extract_model(model, MAXMODEL, buffer)
|
|
, ata_extract_version(buffer));
|
|
port->prio = bootprio_find_ata_device(ctrl->pci_tmp, pnr, 0);
|
|
}
|
|
boot_lchs_find_ata_device(ctrl->pci_tmp, pnr, 0, &(port->drive.lchs));
|
|
return 0;
|
|
}
|
|
|
|
// Detect any drives attached to a given controller.
|
|
static void
|
|
ahci_port_detect(void *data)
|
|
{
|
|
struct ahci_port_s *port = data;
|
|
int rc;
|
|
|
|
dprintf(2, "AHCI/%d: probing\n", port->pnr);
|
|
ahci_port_reset(port->ctrl, port->pnr);
|
|
rc = ahci_port_setup(port);
|
|
if (rc < 0)
|
|
ahci_port_release(port);
|
|
else {
|
|
port = ahci_port_realloc(port);
|
|
if (port == NULL)
|
|
return;
|
|
dprintf(1, "AHCI/%d: registering: \"%s\"\n", port->pnr, port->desc);
|
|
if (!port->atapi) {
|
|
// Register with bcv system.
|
|
boot_add_hd(&port->drive, port->desc, port->prio);
|
|
} else {
|
|
// fill cdidmap
|
|
boot_add_cd(&port->drive, port->desc, port->prio);
|
|
}
|
|
}
|
|
}
|
|
|
|
// Initialize an ata controller and detect its drives.
|
|
static void
|
|
ahci_controller_setup(struct pci_device *pci)
|
|
{
|
|
struct ahci_port_s *port;
|
|
u32 val, pnr, max;
|
|
|
|
if (create_bounce_buf() < 0)
|
|
return;
|
|
|
|
void *iobase = pci_enable_membar(pci, PCI_BASE_ADDRESS_5);
|
|
if (!iobase)
|
|
return;
|
|
|
|
struct ahci_ctrl_s *ctrl = malloc_fseg(sizeof(*ctrl));
|
|
if (!ctrl) {
|
|
warn_noalloc();
|
|
return;
|
|
}
|
|
|
|
ctrl->pci_tmp = pci;
|
|
ctrl->iobase = iobase;
|
|
ctrl->irq = pci_config_readb(pci->bdf, PCI_INTERRUPT_LINE);
|
|
dprintf(1, "AHCI controller at %pP, iobase %p, irq %d\n"
|
|
, pci, ctrl->iobase, ctrl->irq);
|
|
|
|
pci_enable_busmaster(pci);
|
|
|
|
val = ahci_ctrl_readl(ctrl, HOST_CTL);
|
|
ahci_ctrl_writel(ctrl, HOST_CTL, val | HOST_CTL_AHCI_EN);
|
|
|
|
ctrl->caps = ahci_ctrl_readl(ctrl, HOST_CAP);
|
|
ctrl->ports = ahci_ctrl_readl(ctrl, HOST_PORTS_IMPL);
|
|
dprintf(2, "AHCI: cap 0x%x, ports_impl 0x%x\n",
|
|
ctrl->caps, ctrl->ports);
|
|
|
|
max = 0x1f;
|
|
for (pnr = 0; pnr <= max; pnr++) {
|
|
if (!(ctrl->ports & (1 << pnr)))
|
|
continue;
|
|
port = ahci_port_alloc(ctrl, pnr);
|
|
if (port == NULL)
|
|
continue;
|
|
run_thread(ahci_port_detect, port);
|
|
}
|
|
}
|
|
|
|
// Locate and init ahci controllers.
|
|
static void
|
|
ahci_scan(void)
|
|
{
|
|
// Scan PCI bus for ATA adapters
|
|
struct pci_device *pci;
|
|
foreachpci(pci) {
|
|
if (pci->class != PCI_CLASS_STORAGE_SATA)
|
|
continue;
|
|
if (pci->prog_if != 1 /* AHCI rev 1 */)
|
|
continue;
|
|
ahci_controller_setup(pci);
|
|
}
|
|
}
|
|
|
|
void
|
|
ahci_setup(void)
|
|
{
|
|
ASSERT32FLAT();
|
|
if (!CONFIG_AHCI)
|
|
return;
|
|
|
|
dprintf(3, "init ahci\n");
|
|
ahci_scan();
|
|
}
|