218 lines
6.5 KiB
C
218 lines
6.5 KiB
C
// Initialize PCI devices (on emulators)
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//
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// Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
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// Copyright (C) 2006 Fabrice Bellard
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//
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// This file may be distributed under the terms of the GNU LGPLv3 license.
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#include "util.h" // dprintf
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#include "pci.h" // pci_config_readl
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#include "biosvar.h" // GET_EBDA
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#include "pci_ids.h" // PCI_VENDOR_ID_INTEL
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#include "pci_regs.h" // PCI_COMMAND
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#define PCI_ROM_SLOT 6
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#define PCI_NUM_REGIONS 7
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static u32 pci_bios_io_addr;
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static u32 pci_bios_mem_addr;
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static u32 pci_bios_bigmem_addr;
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/* host irqs corresponding to PCI irqs A-D */
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static u8 pci_irqs[4] = {
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#if CONFIG_KVM
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10, 10, 11, 11
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#else
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11, 9, 11, 9
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#endif
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};
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static void pci_set_io_region_addr(u16 bdf, int region_num, u32 addr)
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{
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u16 cmd;
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u32 ofs, old_addr;
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if (region_num == PCI_ROM_SLOT) {
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ofs = PCI_ROM_ADDRESS;
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} else {
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ofs = PCI_BASE_ADDRESS_0 + region_num * 4;
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}
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old_addr = pci_config_readl(bdf, ofs);
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pci_config_writel(bdf, ofs, addr);
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dprintf(1, "region %d: 0x%08x\n", region_num, addr);
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/* enable memory mappings */
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cmd = pci_config_readw(bdf, PCI_COMMAND);
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if (region_num == PCI_ROM_SLOT)
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cmd |= PCI_COMMAND_MEMORY;
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else if (old_addr & PCI_BASE_ADDRESS_SPACE_IO)
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cmd |= PCI_COMMAND_IO;
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else
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cmd |= PCI_COMMAND_MEMORY;
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pci_config_writew(bdf, PCI_COMMAND, cmd);
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}
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/* return the global irq number corresponding to a given device irq
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pin. We could also use the bus number to have a more precise
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mapping. */
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static int pci_slot_get_pirq(u16 bdf, int irq_num)
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{
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int slot_addend = pci_bdf_to_dev(bdf) - 1;
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return (irq_num + slot_addend) & 3;
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}
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static void pci_bios_init_bridges(u16 bdf)
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{
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u16 vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID);
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u16 device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
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if (vendor_id == PCI_VENDOR_ID_INTEL
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&& (device_id == PCI_DEVICE_ID_INTEL_82371SB_0
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|| device_id == PCI_DEVICE_ID_INTEL_82371AB_0)) {
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int i, irq;
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u8 elcr[2];
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/* PIIX3/PIIX4 PCI to ISA bridge */
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elcr[0] = 0x00;
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elcr[1] = 0x00;
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for(i = 0; i < 4; i++) {
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irq = pci_irqs[i];
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/* set to trigger level */
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elcr[irq >> 3] |= (1 << (irq & 7));
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/* activate irq remapping in PIIX */
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pci_config_writeb(bdf, 0x60 + i, irq);
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}
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outb(elcr[0], 0x4d0);
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outb(elcr[1], 0x4d1);
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dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n",
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elcr[0], elcr[1]);
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}
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}
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static void pci_bios_init_device(u16 bdf)
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{
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int class;
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u32 *paddr;
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int i, pin, pic_irq, vendor_id, device_id;
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class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
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vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID);
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device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
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dprintf(1, "PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n"
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, pci_bdf_to_bus(bdf), pci_bdf_to_devfn(bdf), vendor_id, device_id);
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switch(class) {
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case PCI_CLASS_STORAGE_IDE:
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if (vendor_id == PCI_VENDOR_ID_INTEL
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&& (device_id == PCI_DEVICE_ID_INTEL_82371SB_1
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|| device_id == PCI_DEVICE_ID_INTEL_82371AB)) {
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/* PIIX3/PIIX4 IDE */
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pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
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pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
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goto default_map;
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} else {
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/* IDE: we map it as in ISA mode */
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pci_set_io_region_addr(bdf, 0, 0x1f0);
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pci_set_io_region_addr(bdf, 1, 0x3f4);
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pci_set_io_region_addr(bdf, 2, 0x170);
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pci_set_io_region_addr(bdf, 3, 0x374);
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}
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break;
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case PCI_CLASS_DISPLAY_VGA:
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if (vendor_id != 0x1234)
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goto default_map;
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/* VGA: map frame buffer to default Bochs VBE address */
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pci_set_io_region_addr(bdf, 0, 0xE0000000);
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break;
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case PCI_CLASS_SYSTEM_PIC:
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/* PIC */
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if (vendor_id == PCI_VENDOR_ID_IBM) {
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/* IBM */
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if (device_id == 0x0046 || device_id == 0xFFFF) {
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/* MPIC & MPIC2 */
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pci_set_io_region_addr(bdf, 0, 0x80800000 + 0x00040000);
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}
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}
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break;
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case 0xff00:
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if (vendor_id == PCI_VENDOR_ID_APPLE &&
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(device_id == 0x0017 || device_id == 0x0022)) {
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/* macio bridge */
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pci_set_io_region_addr(bdf, 0, 0x80800000);
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}
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break;
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default:
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default_map:
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/* default memory mappings */
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for (i = 0; i < PCI_NUM_REGIONS; i++) {
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int ofs;
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u32 val, size;
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if (i == PCI_ROM_SLOT)
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ofs = PCI_ROM_ADDRESS;
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else
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ofs = PCI_BASE_ADDRESS_0 + i * 4;
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pci_config_writel(bdf, ofs, 0xffffffff);
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val = pci_config_readl(bdf, ofs);
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if (val != 0) {
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size = (~(val & ~0xf)) + 1;
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if (val & PCI_BASE_ADDRESS_SPACE_IO)
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paddr = &pci_bios_io_addr;
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else if (size >= 0x04000000)
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paddr = &pci_bios_bigmem_addr;
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else
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paddr = &pci_bios_mem_addr;
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*paddr = ALIGN(*paddr, size);
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pci_set_io_region_addr(bdf, i, *paddr);
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*paddr += size;
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}
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}
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break;
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}
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/* map the interrupt */
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pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
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if (pin != 0) {
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pin = pci_slot_get_pirq(bdf, pin - 1);
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pic_irq = pci_irqs[pin];
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pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pic_irq);
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}
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if (vendor_id == PCI_VENDOR_ID_INTEL
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&& device_id == PCI_DEVICE_ID_INTEL_82371AB_3) {
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/* PIIX4 Power Management device (for ACPI) */
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if (CONFIG_KVM)
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// acpi sci is hardwired to 9
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pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
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pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1);
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pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
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pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1);
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pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
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}
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}
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void
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pci_bios_setup(void)
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{
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if (CONFIG_COREBOOT)
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// Already done by coreboot.
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return;
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pci_bios_io_addr = 0xc000;
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pci_bios_mem_addr = 0xf0000000;
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pci_bios_bigmem_addr = RamSize;
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if (pci_bios_bigmem_addr < 0x90000000)
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pci_bios_bigmem_addr = 0x90000000;
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int bdf, max;
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foreachpci(bdf, max) {
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pci_bios_init_bridges(bdf);
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}
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foreachpci(bdf, max) {
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pci_bios_init_device(bdf);
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}
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}
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