190 lines
4.6 KiB
C
190 lines
4.6 KiB
C
// PCI BIOS (int 1a/b1) calls
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//
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// Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
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// Copyright (C) 2002 MandrakeSoft S.A.
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//
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// This file may be distributed under the terms of the GNU LGPLv3 license.
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#include "types.h" // u32
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#include "util.h" // handle_1ab1
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#include "pci.h" // pci_config_readl
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#include "bregs.h" // struct bregs
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#include "biosvar.h" // GET_EBDA
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#include "pci_regs.h" // PCI_VENDOR_ID
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#define RET_FUNC_NOT_SUPPORTED 0x81
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#define RET_BAD_VENDOR_ID 0x83
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#define RET_DEVICE_NOT_FOUND 0x86
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#define RET_BUFFER_TOO_SMALL 0x89
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// installation check
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static void
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handle_1ab101(struct bregs *regs)
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{
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// Find max bus.
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int bdf, max;
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foreachpci(bdf, max) {
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}
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regs->al = 0x01; // Flags - "Config Mechanism #1" supported.
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regs->bx = 0x0210; // PCI version 2.10
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regs->cl = pci_bdf_to_bus(max - 1);
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regs->edx = 0x20494350; // "PCI "
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// XXX - bochs bios code sets edi to point to 32bit code - but no
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// reference to this in spec.
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set_code_success(regs);
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}
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// find pci device
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static void
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handle_1ab102(struct bregs *regs)
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{
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u32 id = (regs->cx << 16) | regs->dx;
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int count = regs->si;
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int bdf, max;
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foreachpci(bdf, max) {
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u32 v = pci_config_readl(bdf, PCI_VENDOR_ID);
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if (v != id)
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continue;
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if (count--)
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continue;
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regs->bx = bdf;
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set_code_success(regs);
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return;
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}
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set_code_fail(regs, RET_DEVICE_NOT_FOUND);
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}
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// find class code
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static void
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handle_1ab103(struct bregs *regs)
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{
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int count = regs->si;
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u32 classprog = regs->ecx;
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int bdf, max;
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foreachpci(bdf, max) {
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u32 v = pci_config_readl(bdf, PCI_CLASS_REVISION);
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if ((v>>8) != classprog)
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continue;
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if (count--)
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continue;
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regs->bx = bdf;
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set_code_success(regs);
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return;
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}
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set_code_fail(regs, RET_DEVICE_NOT_FOUND);
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}
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// read configuration byte
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static void
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handle_1ab108(struct bregs *regs)
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{
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regs->cl = pci_config_readb(regs->bx, regs->di);
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set_code_success(regs);
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}
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// read configuration word
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static void
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handle_1ab109(struct bregs *regs)
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{
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regs->cx = pci_config_readw(regs->bx, regs->di);
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set_code_success(regs);
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}
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// read configuration dword
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static void
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handle_1ab10a(struct bregs *regs)
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{
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regs->ecx = pci_config_readl(regs->bx, regs->di);
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set_code_success(regs);
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}
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// write configuration byte
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static void
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handle_1ab10b(struct bregs *regs)
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{
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pci_config_writeb(regs->bx, regs->di, regs->cl);
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set_code_success(regs);
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}
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// write configuration word
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static void
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handle_1ab10c(struct bregs *regs)
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{
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pci_config_writew(regs->bx, regs->di, regs->cx);
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set_code_success(regs);
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}
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// write configuration dword
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static void
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handle_1ab10d(struct bregs *regs)
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{
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pci_config_writel(regs->bx, regs->di, regs->ecx);
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set_code_success(regs);
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}
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// get irq routing options
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static void
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handle_1ab10e(struct bregs *regs)
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{
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struct pir_header *pirtable_g = (void*)(GET_GLOBAL(PirOffset) + 0);
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if (! pirtable_g) {
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set_code_fail(regs, RET_FUNC_NOT_SUPPORTED);
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return;
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}
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// Validate and update size.
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u16 size = GET_FARVAR(regs->es, *(u16*)(regs->di+0));
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u16 pirsize = (GET_GLOBAL(pirtable_g->size)
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- sizeof(struct pir_header));
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SET_FARVAR(regs->es, *(u16*)(regs->di+0), pirsize);
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if (size < pirsize) {
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set_code_fail(regs, RET_BUFFER_TOO_SMALL);
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return;
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}
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// Get dest buffer.
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u16 d = (GET_FARVAR(regs->es, *(u16*)(regs->di+2)) + 0);
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u16 destseg = GET_FARVAR(regs->es, *(u16*)(regs->di+4));
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// Memcpy pir table slots to dest buffer.
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memcpy_far(MAKE_FARPTR(destseg, d)
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, MAKE_FARPTR(SEG_BIOS, pirtable_g)
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, pirsize);
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// XXX - bochs bios sets bx to (1 << 9) | (1 << 11)
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regs->bx = GET_GLOBAL(pirtable_g->exclusive_irqs);
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set_code_success(regs);
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}
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static void
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handle_1ab1XX(struct bregs *regs)
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{
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set_code_fail(regs, RET_FUNC_NOT_SUPPORTED);
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}
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void
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handle_1ab1(struct bregs *regs)
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{
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//debug_stub(regs);
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if (! CONFIG_PCIBIOS) {
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set_fail(regs);
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return;
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}
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switch (regs->al) {
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case 0x01: handle_1ab101(regs); break;
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case 0x02: handle_1ab102(regs); break;
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case 0x03: handle_1ab103(regs); break;
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case 0x08: handle_1ab108(regs); break;
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case 0x09: handle_1ab109(regs); break;
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case 0x0a: handle_1ab10a(regs); break;
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case 0x0b: handle_1ab10b(regs); break;
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case 0x0c: handle_1ab10c(regs); break;
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case 0x0d: handle_1ab10d(regs); break;
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case 0x0e: handle_1ab10e(regs); break;
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default: handle_1ab1XX(regs); break;
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}
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}
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