483 lines
18 KiB
C
483 lines
18 KiB
C
// Support for generating ACPI tables (on emulators)
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//
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// Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
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// Copyright (C) 2006 Fabrice Bellard
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//
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// This file may be distributed under the terms of the GNU LGPLv3 license.
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#include "acpi.h" // struct rsdp_descriptor
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#include "util.h" // memcpy
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#include "memmap.h" // bios_table_cur_addr
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#include "pci.h" // pci_find_device
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#include "biosvar.h" // GET_EBDA
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#include "pci_ids.h" // PCI_VENDOR_ID_INTEL
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#include "pci_regs.h" // PCI_INTERRUPT_LINE
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/****************************************************/
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/* ACPI tables init */
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/* Table structure from Linux kernel (the ACPI tables are under the
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BSD license) */
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#define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
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u32 signature; /* ACPI signature (4 ASCII characters) */\
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u32 length; /* Length of table, in bytes, including header */\
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u8 revision; /* ACPI Specification minor version # */\
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u8 checksum; /* To make sum of entire table == 0 */\
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u8 oem_id [6]; /* OEM identification */\
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u8 oem_table_id [8]; /* OEM table identification */\
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u32 oem_revision; /* OEM revision number */\
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u8 asl_compiler_id [4]; /* ASL compiler vendor ID */\
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u32 asl_compiler_revision; /* ASL compiler revision number */
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struct acpi_table_header /* ACPI common table header */
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{
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ACPI_TABLE_HEADER_DEF
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};
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/*
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* ACPI 1.0 Root System Description Table (RSDT)
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*/
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#define RSDT_SIGNATURE 0x54445352 // RSDT
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struct rsdt_descriptor_rev1
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{
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ACPI_TABLE_HEADER_DEF /* ACPI common table header */
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u32 table_offset_entry [3]; /* Array of pointers to other */
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/* ACPI tables */
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};
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/*
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* ACPI 1.0 Firmware ACPI Control Structure (FACS)
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*/
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#define FACS_SIGNATURE 0x53434146 // FACS
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struct facs_descriptor_rev1
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{
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u32 signature; /* ACPI Signature */
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u32 length; /* Length of structure, in bytes */
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u32 hardware_signature; /* Hardware configuration signature */
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u32 firmware_waking_vector; /* ACPI OS waking vector */
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u32 global_lock; /* Global Lock */
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u32 S4bios_f : 1; /* Indicates if S4BIOS support is present */
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u32 reserved1 : 31; /* Must be 0 */
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u8 resverved3 [40]; /* Reserved - must be zero */
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};
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/*
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* ACPI 1.0 Fixed ACPI Description Table (FADT)
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*/
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#define FACP_SIGNATURE 0x50434146 // FACP
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struct fadt_descriptor_rev1
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{
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ACPI_TABLE_HEADER_DEF /* ACPI common table header */
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u32 firmware_ctrl; /* Physical address of FACS */
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u32 dsdt; /* Physical address of DSDT */
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u8 model; /* System Interrupt Model */
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u8 reserved1; /* Reserved */
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u16 sci_int; /* System vector of SCI interrupt */
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u32 smi_cmd; /* Port address of SMI command port */
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u8 acpi_enable; /* Value to write to smi_cmd to enable ACPI */
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u8 acpi_disable; /* Value to write to smi_cmd to disable ACPI */
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u8 S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
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u8 reserved2; /* Reserved - must be zero */
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u32 pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
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u32 pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
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u32 pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
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u32 pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
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u32 pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
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u32 pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
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u32 gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
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u32 gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
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u8 pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
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u8 pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
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u8 pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
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u8 pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
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u8 gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
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u8 gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
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u8 gpe1_base; /* Offset in gpe model where gpe1 events start */
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u8 reserved3; /* Reserved */
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u16 plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
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u16 plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
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u16 flush_size; /* Size of area read to flush caches */
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u16 flush_stride; /* Stride used in flushing caches */
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u8 duty_offset; /* Bit location of duty cycle field in p_cnt reg */
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u8 duty_width; /* Bit width of duty cycle field in p_cnt reg */
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u8 day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
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u8 mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
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u8 century; /* Index to century in RTC CMOS RAM */
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u8 reserved4; /* Reserved */
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u8 reserved4a; /* Reserved */
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u8 reserved4b; /* Reserved */
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#if 0
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u32 wb_invd : 1; /* The wbinvd instruction works properly */
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u32 wb_invd_flush : 1; /* The wbinvd flushes but does not invalidate */
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u32 proc_c1 : 1; /* All processors support C1 state */
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u32 plvl2_up : 1; /* C2 state works on MP system */
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u32 pwr_button : 1; /* Power button is handled as a generic feature */
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u32 sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */
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u32 fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */
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u32 rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
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u32 tmr_val_ext : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */
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u32 reserved5 : 23; /* Reserved - must be zero */
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#else
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u32 flags;
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#endif
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};
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/*
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* MADT values and structures
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*/
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/* Values for MADT PCATCompat */
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#define DUAL_PIC 0
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#define MULTIPLE_APIC 1
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/* Master MADT */
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#define APIC_SIGNATURE 0x43495041 // APIC
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struct multiple_apic_table
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{
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ACPI_TABLE_HEADER_DEF /* ACPI common table header */
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u32 local_apic_address; /* Physical address of local APIC */
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#if 0
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u32 PCATcompat : 1; /* A one indicates system also has dual 8259s */
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u32 reserved1 : 31;
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#else
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u32 flags;
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#endif
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};
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/* Values for Type in APIC_HEADER_DEF */
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#define APIC_PROCESSOR 0
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#define APIC_IO 1
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#define APIC_XRUPT_OVERRIDE 2
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#define APIC_NMI 3
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#define APIC_LOCAL_NMI 4
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#define APIC_ADDRESS_OVERRIDE 5
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#define APIC_IO_SAPIC 6
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#define APIC_LOCAL_SAPIC 7
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#define APIC_XRUPT_SOURCE 8
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#define APIC_RESERVED 9 /* 9 and greater are reserved */
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/*
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* MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
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*/
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#define APIC_HEADER_DEF /* Common APIC sub-structure header */\
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u8 type; \
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u8 length;
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/* Sub-structures for MADT */
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struct madt_processor_apic
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{
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APIC_HEADER_DEF
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u8 processor_id; /* ACPI processor id */
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u8 local_apic_id; /* Processor's local APIC id */
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#if 0
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u32 processor_enabled: 1; /* Processor is usable if set */
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u32 reserved2 : 31; /* Reserved, must be zero */
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#else
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u32 flags;
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#endif
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};
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struct madt_io_apic
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{
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APIC_HEADER_DEF
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u8 io_apic_id; /* I/O APIC ID */
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u8 reserved; /* Reserved - must be zero */
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u32 address; /* APIC physical address */
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u32 interrupt; /* Global system interrupt where INTI
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* lines start */
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};
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#if CONFIG_KVM
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/* IRQs 5,9,10,11 */
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#define PCI_ISA_IRQ_MASK 0x0e20
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#else
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#define PCI_ISA_IRQ_MASK 0x0000
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#endif
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struct madt_intsrcovr {
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APIC_HEADER_DEF
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u8 bus;
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u8 source;
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u32 gsi;
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u16 flags;
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} PACKED;
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#include "acpi-dsdt.hex"
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static inline u16 cpu_to_le16(u16 x)
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{
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return x;
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}
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static inline u32 cpu_to_le32(u32 x)
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{
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return x;
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}
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static void acpi_build_table_header(struct acpi_table_header *h,
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u32 sig, int len, u8 rev)
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{
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h->signature = sig;
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h->length = cpu_to_le32(len);
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h->revision = rev;
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memcpy(h->oem_id, CONFIG_APPNAME6, 6);
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memcpy(h->oem_table_id, CONFIG_APPNAME4, 4);
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memcpy(h->asl_compiler_id, CONFIG_APPNAME4, 4);
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memcpy(h->oem_table_id + 4, (void*)&sig, 4);
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h->oem_revision = cpu_to_le32(1);
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h->asl_compiler_revision = cpu_to_le32(1);
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h->checksum = -checksum((void *)h, len);
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}
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#define SSDT_SIGNATURE 0x54445353// SSDT
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static int
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acpi_build_processor_ssdt(u8 *ssdt)
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{
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u8 *ssdt_ptr = ssdt;
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int i, length;
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int smp_cpus = smp_probe();
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int acpi_cpus = smp_cpus > 0xff ? 0xff : smp_cpus;
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ssdt_ptr[9] = 0; // checksum;
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ssdt_ptr += sizeof(struct acpi_table_header);
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// caluculate the length of processor block and scope block excluding PkgLength
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length = 0x0d * acpi_cpus + 4;
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// build processor scope header
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*(ssdt_ptr++) = 0x10; // ScopeOp
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if (length <= 0x3e) {
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*(ssdt_ptr++) = length + 1;
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} else {
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*(ssdt_ptr++) = 0x7F;
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*(ssdt_ptr++) = (length + 2) >> 6;
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}
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*(ssdt_ptr++) = '_'; // Name
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*(ssdt_ptr++) = 'P';
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*(ssdt_ptr++) = 'R';
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*(ssdt_ptr++) = '_';
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// build object for each processor
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for(i=0;i<acpi_cpus;i++) {
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*(ssdt_ptr++) = 0x5B; // ProcessorOp
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*(ssdt_ptr++) = 0x83;
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*(ssdt_ptr++) = 0x0B; // Length
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*(ssdt_ptr++) = 'C'; // Name (CPUxx)
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*(ssdt_ptr++) = 'P';
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if ((i & 0xf0) != 0)
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*(ssdt_ptr++) = (i >> 4) < 0xa ? (i >> 4) + '0' : (i >> 4) + 'A' - 0xa;
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else
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*(ssdt_ptr++) = 'U';
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*(ssdt_ptr++) = (i & 0xf) < 0xa ? (i & 0xf) + '0' : (i & 0xf) + 'A' - 0xa;
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*(ssdt_ptr++) = i;
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*(ssdt_ptr++) = 0x10; // Processor block address
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*(ssdt_ptr++) = 0xb0;
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*(ssdt_ptr++) = 0;
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*(ssdt_ptr++) = 0;
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*(ssdt_ptr++) = 6; // Processor block length
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}
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acpi_build_table_header((struct acpi_table_header *)ssdt,
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SSDT_SIGNATURE, ssdt_ptr - ssdt, 1);
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return ssdt_ptr - ssdt;
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}
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struct rsdp_descriptor *RsdpAddr;
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/* base_addr must be a multiple of 4KB */
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void acpi_bios_init(void)
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{
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if (! CONFIG_ACPI)
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return;
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dprintf(3, "init ACPI tables\n");
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// This code is hardcoded for PIIX4 Power Management device.
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int bdf = pci_find_device(PCI_VENDOR_ID_INTEL
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, PCI_DEVICE_ID_INTEL_82371AB_3);
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if (bdf < 0)
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// Device not found
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return;
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struct rsdp_descriptor *rsdp;
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struct rsdt_descriptor_rev1 *rsdt;
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struct fadt_descriptor_rev1 *fadt;
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struct facs_descriptor_rev1 *facs;
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struct multiple_apic_table *madt;
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u8 *dsdt, *ssdt;
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u32 base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr, ssdt_addr;
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u32 acpi_tables_size, madt_addr, madt_size;
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int i;
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/* reserve memory space for tables */
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bios_table_cur_addr = ALIGN(bios_table_cur_addr, 16);
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rsdp = (void *)(bios_table_cur_addr);
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bios_table_cur_addr += sizeof(*rsdp);
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addr = base_addr = RamSize - CONFIG_ACPI_DATA_SIZE;
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add_e820(addr, CONFIG_ACPI_DATA_SIZE, E820_ACPI);
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rsdt_addr = addr;
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rsdt = (void *)(addr);
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addr += sizeof(*rsdt);
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fadt_addr = addr;
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fadt = (void *)(addr);
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addr += sizeof(*fadt);
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addr = ALIGN(addr, 64);
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facs_addr = addr;
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facs = (void *)(addr);
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addr += sizeof(*facs);
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dsdt_addr = addr;
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dsdt = (void *)(addr);
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addr += sizeof(AmlCode);
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ssdt_addr = addr;
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ssdt = (void *)(addr);
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addr += acpi_build_processor_ssdt(ssdt);
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int smp_cpus = smp_probe();
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addr = ALIGN(addr, 8);
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madt_addr = addr;
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madt_size = sizeof(*madt) +
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sizeof(struct madt_processor_apic) * smp_cpus +
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sizeof(struct madt_io_apic);
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madt = (void *)(addr);
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addr += madt_size;
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acpi_tables_size = addr - base_addr;
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dprintf(1, "ACPI tables: RSDP addr=0x%08lx"
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" ACPI DATA addr=0x%08lx size=0x%x\n",
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(unsigned long)rsdp,
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(unsigned long)rsdt, acpi_tables_size);
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/* RSDP */
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memset(rsdp, 0, sizeof(*rsdp));
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rsdp->signature = RSDP_SIGNATURE;
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memcpy(rsdp->oem_id, CONFIG_APPNAME6, 6);
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rsdp->rsdt_physical_address = cpu_to_le32(rsdt_addr);
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rsdp->checksum = -checksum((void *)rsdp, 20);
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RsdpAddr = rsdp;
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/* RSDT */
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memset(rsdt, 0, sizeof(*rsdt));
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rsdt->table_offset_entry[0] = cpu_to_le32(fadt_addr);
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rsdt->table_offset_entry[1] = cpu_to_le32(madt_addr);
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rsdt->table_offset_entry[2] = cpu_to_le32(ssdt_addr);
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acpi_build_table_header((struct acpi_table_header *)rsdt,
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RSDT_SIGNATURE, sizeof(*rsdt), 1);
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/* FADT */
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memset(fadt, 0, sizeof(*fadt));
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fadt->firmware_ctrl = cpu_to_le32(facs_addr);
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fadt->dsdt = cpu_to_le32(dsdt_addr);
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fadt->model = 1;
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fadt->reserved1 = 0;
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int pm_sci_int = pci_config_readb(bdf, PCI_INTERRUPT_LINE);
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fadt->sci_int = cpu_to_le16(pm_sci_int);
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fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD);
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fadt->acpi_enable = 0xf1;
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fadt->acpi_disable = 0xf0;
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fadt->pm1a_evt_blk = cpu_to_le32(PORT_ACPI_PM_BASE);
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fadt->pm1a_cnt_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x04);
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fadt->pm_tmr_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x08);
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fadt->pm1_evt_len = 4;
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fadt->pm1_cnt_len = 2;
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fadt->pm_tmr_len = 4;
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fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
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fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
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/* WBINVD + PROC_C1 + PWR_BUTTON + SLP_BUTTON + FIX_RTC */
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fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 4) | (1 << 5) | (1 << 6));
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acpi_build_table_header((struct acpi_table_header *)fadt, FACP_SIGNATURE,
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sizeof(*fadt), 1);
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/* FACS */
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memset(facs, 0, sizeof(*facs));
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facs->signature = FACS_SIGNATURE;
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facs->length = cpu_to_le32(sizeof(*facs));
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/* DSDT */
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memcpy(dsdt, AmlCode, sizeof(AmlCode));
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/* MADT */
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memset(madt, 0, madt_size);
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madt->local_apic_address = cpu_to_le32(BUILD_APIC_ADDR);
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madt->flags = cpu_to_le32(1);
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struct madt_processor_apic *apic = (void *)(madt + 1);
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for(i=0;i<smp_cpus;i++) {
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apic->type = APIC_PROCESSOR;
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apic->length = sizeof(*apic);
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apic->processor_id = i;
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apic->local_apic_id = i;
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apic->flags = cpu_to_le32(1);
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apic++;
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}
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struct madt_io_apic *io_apic = (void *)apic;
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io_apic->type = APIC_IO;
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io_apic->length = sizeof(*io_apic);
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io_apic->io_apic_id = smp_cpus;
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io_apic->address = cpu_to_le32(BUILD_IOAPIC_ADDR);
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io_apic->interrupt = cpu_to_le32(0);
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struct madt_intsrcovr *intsrcovr = (struct madt_intsrcovr*)(io_apic + 1);
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for (i = 0; i < 16; i++) {
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if (PCI_ISA_IRQ_MASK & (1 << i)) {
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memset(intsrcovr, 0, sizeof(*intsrcovr));
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intsrcovr->type = APIC_XRUPT_OVERRIDE;
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intsrcovr->length = sizeof(*intsrcovr);
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intsrcovr->source = i;
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intsrcovr->gsi = i;
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intsrcovr->flags = 0xd; /* active high, level triggered */
|
|
} else {
|
|
/* No need for a INT source override structure. */
|
|
continue;
|
|
}
|
|
intsrcovr++;
|
|
madt_size += sizeof(struct madt_intsrcovr);
|
|
}
|
|
|
|
acpi_build_table_header((struct acpi_table_header *)madt,
|
|
APIC_SIGNATURE, madt_size, 1);
|
|
}
|
|
|
|
u32
|
|
find_resume_vector()
|
|
{
|
|
dprintf(4, "rsdp=%p\n", RsdpAddr);
|
|
if (!RsdpAddr || RsdpAddr->signature != RSDP_SIGNATURE)
|
|
return 0;
|
|
struct rsdt_descriptor_rev1 *rsdt = (void*)RsdpAddr->rsdt_physical_address;
|
|
dprintf(4, "rsdt=%p\n", rsdt);
|
|
if (!rsdt || rsdt->signature != RSDT_SIGNATURE)
|
|
return 0;
|
|
void *end = (void*)rsdt + rsdt->length;
|
|
int i;
|
|
for (i=0; (void*)&rsdt->table_offset_entry[i] < end; i++) {
|
|
struct fadt_descriptor_rev1 *fadt = (void*)rsdt->table_offset_entry[i];
|
|
if (!fadt || fadt->signature != FACP_SIGNATURE)
|
|
continue;
|
|
dprintf(4, "fadt=%p\n", fadt);
|
|
struct facs_descriptor_rev1 *facs = (void*)fadt->firmware_ctrl;
|
|
dprintf(4, "facs=%p\n", facs);
|
|
if (! facs || facs->signature != FACS_SIGNATURE)
|
|
return 0;
|
|
// Found it.
|
|
dprintf(4, "resume addr=%d\n", facs->firmware_waking_vector);
|
|
return facs->firmware_waking_vector;
|
|
}
|
|
return 0;
|
|
}
|