246 lines
7.2 KiB
C
246 lines
7.2 KiB
C
// QEMU ATI VGABIOS Extension.
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//
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// This file may be distributed under the terms of the GNU LGPLv3 license.
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#include "biosvar.h" // GET_GLOBAL
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#include "bregs.h" // struct bregs
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#include "hw/pci.h" // pci_config_readl
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#include "hw/pci_regs.h" // PCI_BASE_ADDRESS_0
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#include "output.h" // dprintf
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#include "stdvga.h" // VGAREG_SEQU_ADDRESS
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#include "string.h" // memset16_far
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#include "vgabios.h" // SET_VGA
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#include "vgautil.h" // VBE_total_memory
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#include "vgafb.h" // memset_high
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#include "svgamodes.h"
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#define MM_INDEX 0x0000
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#define MM_DATA 0x0004
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#define CRTC_GEN_CNTL 0x0050
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#define CRTC_EXT_CNTL 0x0054
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#define CRTC_H_TOTAL_DISP 0x0200
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#define CRTC_V_TOTAL_DISP 0x0208
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#define CRTC_OFFSET 0x0224
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#define CRTC_PITCH 0x022c
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/* CRTC control values (CRTC_GEN_CNTL) */
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#define CRTC2_EXT_DISP_EN 0x01000000
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#define CRTC2_EN 0x02000000
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#define CRTC_PIX_WIDTH_MASK 0x00000700
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#define CRTC_PIX_WIDTH_4BPP 0x00000100
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#define CRTC_PIX_WIDTH_8BPP 0x00000200
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#define CRTC_PIX_WIDTH_15BPP 0x00000300
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#define CRTC_PIX_WIDTH_16BPP 0x00000400
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#define CRTC_PIX_WIDTH_24BPP 0x00000500
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#define CRTC_PIX_WIDTH_32BPP 0x00000600
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/* CRTC_EXT_CNTL */
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#define CRT_CRTC_DISPLAY_DIS 0x00000400
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#define CRT_CRTC_ON 0x00008000
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static u32 ati_io_addr VAR16 = 0;
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int
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is_ati_mode(struct vgamode_s *vmode_g)
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{
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unsigned int mcount = GET_GLOBAL(svga_mcount);
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return (vmode_g >= &svga_modes[0].info &&
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vmode_g <= &svga_modes[mcount-1].info);
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}
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struct vgamode_s *
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ati_find_mode(int mode)
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{
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u32 io_addr = GET_GLOBAL(ati_io_addr);
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struct generic_svga_mode *table_g = svga_modes;
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unsigned int mcount = GET_GLOBAL(svga_mcount);
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if (io_addr) {
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while (table_g < &svga_modes[mcount]) {
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if (GET_GLOBAL(table_g->mode) == mode)
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return &table_g->info;
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table_g++;
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}
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}
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return stdvga_find_mode(mode);
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}
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void
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ati_list_modes(u16 seg, u16 *dest, u16 *last)
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{
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u32 io_addr = GET_GLOBAL(ati_io_addr);
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unsigned int mcount = GET_GLOBAL(svga_mcount);
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dprintf(1, "%s: ati ext %s\n", __func__, io_addr ? "yes" : "no");
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if (io_addr) {
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int i;
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for (i=0; i<mcount && dest<last; i++) {
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u16 mode = GET_GLOBAL(svga_modes[i].mode);
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if (mode == 0xffff)
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continue;
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SET_FARVAR(seg, *dest, mode);
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dest++;
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}
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}
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stdvga_list_modes(seg, dest, last);
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}
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/****************************************************************
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* Mode setting
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****************************************************************/
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static inline void ati_write(u32 reg, u32 val)
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{
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u32 io_addr = GET_GLOBAL(ati_io_addr);
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if (reg < 0x100) {
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outl(val, io_addr + reg);
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} else {
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outl(reg, io_addr + MM_INDEX);
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outl(val, io_addr + MM_DATA);
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}
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}
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static void ati_clear(u32 offset, u32 size)
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{
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u8 data[64];
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void *datap = MAKE_FLATPTR(GET_SEG(SS), data);
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void *fb = (void*)(GET_GLOBAL(VBE_framebuffer) + offset);
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u32 i, pos;
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for (i = 0; i < sizeof(data); i++)
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data[i] = 0;
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for (pos = 0; pos < size; pos += sizeof(data)) {
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memcpy_high(fb, datap, sizeof(data));
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fb += sizeof(data);
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}
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}
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static int
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ati_ext_mode(struct generic_svga_mode *table, int flags)
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{
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u32 width = GET_GLOBAL(table->info.width);
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u32 height = GET_GLOBAL(table->info.height);
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u32 depth = GET_GLOBAL(table->info.depth);
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u32 stride = width;
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u32 offset = 0;
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u32 pxmask = 0;
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u32 bytes = 0;
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dprintf(1, "%s: 0x%x, %dx%d-%d\n", __func__,
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GET_GLOBAL(table->mode),
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width, height, depth);
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switch (depth) {
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case 8: pxmask = CRTC_PIX_WIDTH_8BPP; bytes = 1; break;
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case 15: pxmask = CRTC_PIX_WIDTH_15BPP; bytes = 2; break;
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case 16: pxmask = CRTC_PIX_WIDTH_16BPP; bytes = 2; break;
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case 24: pxmask = CRTC_PIX_WIDTH_24BPP; bytes = 3; break;
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case 32: pxmask = CRTC_PIX_WIDTH_32BPP; bytes = 4; break;
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}
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/* disable display */
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ati_write(CRTC_EXT_CNTL, CRT_CRTC_DISPLAY_DIS);
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/* modeset */
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ati_write(CRTC_GEN_CNTL, CRTC2_EXT_DISP_EN | CRTC2_EN | pxmask);
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ati_write(CRTC_H_TOTAL_DISP, ((width / 8) - 1) << 16);
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ati_write(CRTC_V_TOTAL_DISP, (height - 1) << 16);
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ati_write(CRTC_OFFSET, offset);
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ati_write(CRTC_PITCH, stride / 8);
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/* clear screen */
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if (!(flags & MF_NOCLEARMEM)) {
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u32 size = width * height * bytes;
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ati_clear(offset, size);
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}
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/* enable display */
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ati_write(CRTC_EXT_CNTL, 0);
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return 0;
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}
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int
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ati_set_mode(struct vgamode_s *vmode_g, int flags)
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{
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struct generic_svga_mode *table_g =
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container_of(vmode_g, struct generic_svga_mode, info);
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if (is_ati_mode(vmode_g)) {
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return ati_ext_mode(table_g, flags);
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}
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ati_write(CRTC_GEN_CNTL, 0);
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return stdvga_set_mode(vmode_g, flags);
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}
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/****************************************************************
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* init
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****************************************************************/
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int
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ati_setup(void)
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{
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int ret = stdvga_setup();
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if (ret)
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return ret;
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dprintf(1, "%s:%d\n", __func__, __LINE__);
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if (GET_GLOBAL(HaveRunInit))
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return 0;
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int bdf = GET_GLOBAL(VgaBDF);
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if (!CONFIG_VGA_PCI || bdf == 0)
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return 0;
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u32 bar = pci_config_readl(bdf, PCI_BASE_ADDRESS_0);
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u32 lfb_addr = bar & PCI_BASE_ADDRESS_MEM_MASK;
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pci_config_writel(bdf, PCI_BASE_ADDRESS_0, ~0);
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u32 barmask = pci_config_readl(bdf, PCI_BASE_ADDRESS_0);
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u32 totalmem = ~(barmask & PCI_BASE_ADDRESS_MEM_MASK) + 1;
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pci_config_writel(bdf, PCI_BASE_ADDRESS_0, bar);
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bar = pci_config_readl(bdf, PCI_BASE_ADDRESS_1);
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u32 io_addr = bar & PCI_BASE_ADDRESS_IO_MASK;
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bar = pci_config_readl(bdf, PCI_BASE_ADDRESS_2);
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u32 mmio_addr = bar & PCI_BASE_ADDRESS_MEM_MASK;
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dprintf(1, "ati: bdf %02x:%02x.%x, lfb 0x%x, %d MB, io 0x%x, mmio 0x%x\n",
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pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf),
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lfb_addr, totalmem / (1024 * 1024), io_addr, mmio_addr);
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SET_VGA(VBE_framebuffer, lfb_addr);
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SET_VGA(VBE_total_memory, totalmem);
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SET_VGA(ati_io_addr, io_addr);
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// Validate modes
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struct generic_svga_mode *m = svga_modes;
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unsigned int mcount = GET_GLOBAL(svga_mcount);
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for (; m < &svga_modes[mcount]; m++) {
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u8 memmodel = GET_GLOBAL(m->info.memmodel);
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u16 width = GET_GLOBAL(m->info.width);
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u16 height = GET_GLOBAL(m->info.height);
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u32 mem = (height * DIV_ROUND_UP(width * vga_bpp(&m->info), 8)
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* stdvga_vram_ratio(&m->info));
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if (width % 8 != 0 ||
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width > 0x7ff * 8 ||
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height > 0xfff ||
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mem > totalmem ||
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memmodel != MM_DIRECT) {
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dprintf(1, "ati: removing mode 0x%x\n", GET_GLOBAL(m->mode));
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SET_VGA(m->mode, 0xffff);
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}
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}
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return 0;
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}
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