90 lines
3.1 KiB
C
90 lines
3.1 KiB
C
// Geode GX2/LX VGA functions
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//
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// Copyright (C) 2009 Chris Kindt
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//
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// Written for Google Summer of Code 2009 for the coreboot project
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//
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// This file may be distributed under the terms of the GNU LGPLv3 license.
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#ifndef GEODEVGA_H
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#define GEODEVGA_H
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#define VRC_INDEX 0xAC1C // Index register
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#define VRC_DATA 0xAC1E // Data register
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#define VR_UNLOCK 0xFC53 // Virtual register unlock code
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// Graphics-specific registers:
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#define OEM_BAR0 0x50
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#define OEM_BAR1 0x54
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#define OEM_BAR2 0x58
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#define OEM_BAR3 0x5C
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#define DC_LOCK_LOCK 0x00000000
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#define DC_LOCK_UNLOCK 0x00004758
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/* LX MSRs */
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#define MSR_GLIU0 (1 << 28)
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#define MSR_GLIU0_BASE4 (MSR_GLIU0 + 0x23) /* LX */
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#define GLIU0_P2D_BM_4 (MSR_GLIU0 + 0x24) /* GX2 */
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#define GLIU0_P2D_RO (MSR_GLIU0 + 0x29)
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#define GLIU0_IOD_BM_0 (MSR_GLIU0 + 0xE0)
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#define GLIU0_IOD_BM_1 (MSR_GLIU0 + 0xE1)
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#define DC_SPARE 0x80000011
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#define VP_MSR_CONFIG_GX2 0xc0002001 /* GX2 */
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#define VP_MSR_CONFIG_LX 0x48002001 /* LX */
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#define VP_MSR_PADSEL 0x48002011
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#define VP_MSR_PADSEL_TFT_SEL_LOW 0xDFFFFFFF
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#define VP_MSR_PADSEL_TFT_SEL_HIGH 0x0000003F
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/* VP_MSR_CONFIG bits */
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#define VP_MSR_CONFIG_FMT_CRT (0)
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#define VP_MSR_CONFIG_FMT_FP (1 << 3)
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#define VP_MSR_CONFIG_FPC (1 << 15)
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#define VP_MSR_CONFIG_FMT ((1 << 3) | (1 << 4) | (1 << 5))
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/* DC REG OFFSET */
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#define DC_UNLOCK 0x0
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#define DC_GENERAL_CFG 0x4
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#define DC_DISPLAY_CFG 0x8
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#define DC_FB_ST_OFFSET 0x10
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#define DC_CB_ST_OFFSET 0x14
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#define DC_CURS_ST_OFFSET 0x18
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#define DC_GLIU0_MEM_OFFSET 0x84
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/* VP REG OFFSET */
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#define VP_VCFG 0x0
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#define VP_DCFG 0x8
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#define VP_MISC 0x50
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/* FP REG OFFSET */
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#define FP_PT1 0x00
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#define FP_PT2 0x08
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#define FP_PM 0x10
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/* DC bits */
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#define DC_GENERAL_CFG_VGAE (1 << 7)
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#define DC_DISPLAY_CFG_GDEN (1 << 3)
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#define DC_DISPLAY_CFG_TRUP (1 << 6)
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/* VP bits */
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#define VP_DCFG_CRT_EN (1 << 0)
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#define VP_DCFG_HSYNC_EN (1 << 1)
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#define VP_DCFG_VSYNC_EN (1 << 2)
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#define VP_DCFG_DAC_BL_EN (1 << 3)
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#define VP_DCFG_CRT_SKEW (1 << 16)
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#define VP_DCFG_BYP_BOTH (1 << 0)
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/* FP bits */
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#define FP_PM_P (1 << 24) /* panel power ctl */
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#define FP_PT2_SCRC (1 << 27) /* panel shift clock retrace activity ctl */
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/* Mask */
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#define DC_CFG_MSK 0xf000a6
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int geodevga_setup();
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#endif
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