196 lines
5.3 KiB
C
196 lines
5.3 KiB
C
// Code for misc 16bit handlers and variables.
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//
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// Copyright (C) 2008,2009 Kevin O'Connor <kevin@koconnor.net>
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// Copyright (C) 2002 MandrakeSoft S.A.
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//
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// This file may be distributed under the terms of the GNU LGPLv3 license.
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#include "biosvar.h" // GET_BDA
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#include "bregs.h" // struct bregs
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#include "hw/pic.h" // enable_hwirq
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#include "output.h" // debug_enter
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#include "stacks.h" // call16_int
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#include "string.h" // memset
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#define PORT_MATH_CLEAR 0x00f0
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// Indicator if POST phase has been started (and if it has completed).
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int HaveRunPost VARFSEG;
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int
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in_post(void)
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{
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return GET_GLOBAL(HaveRunPost) == 1;
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}
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/****************************************************************
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* Misc 16bit ISRs
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****************************************************************/
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// INT 12h Memory Size Service Entry Point
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void VISIBLE16
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handle_12(struct bregs *regs)
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{
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debug_enter(regs, DEBUG_HDL_12);
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regs->ax = GET_BDA(mem_size_kb);
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}
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// INT 11h Equipment List Service Entry Point
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void VISIBLE16
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handle_11(struct bregs *regs)
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{
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debug_enter(regs, DEBUG_HDL_11);
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regs->ax = GET_BDA(equipment_list_flags);
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}
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// INT 05h Print Screen Service Entry Point
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void VISIBLE16
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handle_05(struct bregs *regs)
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{
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debug_enter(regs, DEBUG_HDL_05);
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}
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// NMI handler
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void VISIBLE16
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handle_02(void)
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{
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debug_isr(DEBUG_ISR_02);
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}
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void
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mathcp_setup(void)
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{
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dprintf(3, "math cp init\n");
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// 80x87 coprocessor installed
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set_equipment_flags(0x02, 0x02);
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enable_hwirq(13, FUNC16(entry_75));
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}
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// INT 75 - IRQ13 - MATH COPROCESSOR EXCEPTION
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void VISIBLE16
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handle_75(void)
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{
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debug_isr(DEBUG_ISR_75);
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// clear irq13
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outb(0, PORT_MATH_CLEAR);
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// clear interrupt
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pic_eoi2();
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// legacy nmi call
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struct bregs br;
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memset(&br, 0, sizeof(br));
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br.flags = F_IF;
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call16_int(0x02, &br);
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}
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/****************************************************************
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* BIOS_CONFIG_TABLE
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****************************************************************/
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// DMA channel 3 used by hard disk BIOS
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#define CBT_F1_DMA3USED (1<<7)
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// 2nd interrupt controller (8259) installed
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#define CBT_F1_2NDPIC (1<<6)
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// Real-Time Clock installed
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#define CBT_F1_RTC (1<<5)
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// INT 15/AH=4Fh called upon INT 09h
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#define CBT_F1_INT154F (1<<4)
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// wait for external event (INT 15/AH=41h) supported
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#define CBT_F1_WAITEXT (1<<3)
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// extended BIOS area allocated (usually at top of RAM)
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#define CBT_F1_EBDA (1<<2)
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// bus is Micro Channel instead of ISA
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#define CBT_F1_MCA (1<<1)
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// system has dual bus (Micro Channel + ISA)
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#define CBT_F1_MCAISA (1<<0)
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// INT 16/AH=09h (keyboard functionality) supported
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#define CBT_F2_INT1609 (1<<6)
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struct bios_config_table_s BIOS_CONFIG_TABLE VARFSEGFIXED(0xe6f5) = {
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.size = sizeof(BIOS_CONFIG_TABLE) - 2,
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.model = BUILD_MODEL_ID,
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.submodel = BUILD_SUBMODEL_ID,
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.biosrev = BUILD_BIOS_REVISION,
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.feature1 = (
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CBT_F1_2NDPIC | CBT_F1_RTC | CBT_F1_EBDA
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| (CONFIG_KBD_CALL_INT15_4F ? CBT_F1_INT154F : 0)),
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.feature2 = CBT_F2_INT1609,
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.feature3 = 0,
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.feature4 = 0,
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.feature5 = 0,
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};
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/****************************************************************
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* GDT and IDT tables
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****************************************************************/
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// Real mode IDT descriptor
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struct descloc_s rmode_IDT_info VARFSEG = {
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.length = sizeof(struct rmode_IVT) - 1,
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.addr = (u32)MAKE_FLATPTR(SEG_IVT, 0),
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};
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// Dummy IDT that forces a machine shutdown if an irq happens in
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// protected mode.
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u8 dummy_IDT VARFSEG;
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// Protected mode IDT descriptor
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struct descloc_s pmode_IDT_info VARFSEG = {
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.length = sizeof(dummy_IDT) - 1,
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.addr = (u32)&dummy_IDT,
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};
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// GDT
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u64 rombios32_gdt[] VARFSEG __aligned(8) = {
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// First entry can't be used.
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0x0000000000000000LL,
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// 32 bit flat code segment (SEG32_MODE32_CS)
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GDT_GRANLIMIT(0xffffffff) | GDT_CODE | GDT_B,
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// 32 bit flat data segment (SEG32_MODE32_DS)
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GDT_GRANLIMIT(0xffffffff) | GDT_DATA | GDT_B,
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// 16 bit code segment base=0xf0000 limit=0xffff (SEG32_MODE16_CS)
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GDT_LIMIT(BUILD_BIOS_SIZE-1) | GDT_CODE | GDT_BASE(BUILD_BIOS_ADDR),
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// 16 bit data segment base=0x0 limit=0xffff (SEG32_MODE16_DS)
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GDT_LIMIT(0x0ffff) | GDT_DATA,
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// 16 bit code segment base=0xf0000 limit=0xffffffff (SEG32_MODE16BIG_CS)
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GDT_GRANLIMIT(0xffffffff) | GDT_CODE | GDT_BASE(BUILD_BIOS_ADDR),
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// 16 bit data segment base=0 limit=0xffffffff (SEG32_MODE16BIG_DS)
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GDT_GRANLIMIT(0xffffffff) | GDT_DATA,
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};
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// GDT descriptor
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struct descloc_s rombios32_gdt_48 VARFSEG = {
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.length = sizeof(rombios32_gdt) - 1,
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.addr = (u32)rombios32_gdt,
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};
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/****************************************************************
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* Misc fixed vars
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****************************************************************/
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// BIOS build date
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char BiosDate[] VARFSEGFIXED(0xfff5) = "06/23/99";
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u8 BiosModelId VARFSEGFIXED(0xfffe) = BUILD_MODEL_ID;
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u8 BiosChecksum VARFSEGFIXED(0xffff);
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struct floppy_dbt_s diskette_param_table VARFSEGFIXED(0xefc7);
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// Old Fixed Disk Parameter Table (newer tables are in the ebda).
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struct fdpt_s OldFDPT VARFSEGFIXED(0xe401);
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// XXX - Baud Rate Generator Table
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u8 BaudTable[16] VARFSEGFIXED(0xe729);
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// XXX - Initial Interrupt Vector Offsets Loaded by POST
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u8 InitVectors[13] VARFSEGFIXED(0xfef3);
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// XXX - INT 1D - SYSTEM DATA - VIDEO PARAMETER TABLES
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u8 VideoParams[88] VARFSEGFIXED(0xf0a4);
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