lib: sbi_misaligned_ldst: Determine transformed instruction length correctly
If MTINST[0:0] bit is 1 then we have transformed instruction encoding in MTINST CSR. For transformed instructions, if the MTINST[1:1] bit is Zero then original trapped instruction was a 16bit instruction which was converted to 32bit instruction at time of taking trap. We should use MTINST[1:1] bit to determine correct instruction length of transformed instruction. This patch updates misaligned load/store emulation as-per above. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
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@ -24,7 +24,7 @@ union reg_data {
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int sbi_misaligned_load_handler(ulong addr, ulong tval2, ulong tinst,
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struct sbi_trap_regs *regs)
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{
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ulong insn;
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ulong insn, insn_len;
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union reg_data val;
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struct sbi_trap_info uptrap;
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int i, fp = 0, shift = 0, len = 0;
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@ -35,6 +35,7 @@ int sbi_misaligned_load_handler(ulong addr, ulong tval2, ulong tinst,
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* transformed instruction or custom instruction.
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*/
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insn = tinst | INSN_16BIT_MASK;
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insn_len = (tinst & 0x2) ? INSN_LEN(insn) : 2;
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} else {
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/*
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* Bit[0] == 0 implies trapped instruction value is
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@ -45,6 +46,7 @@ int sbi_misaligned_load_handler(ulong addr, ulong tval2, ulong tinst,
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uptrap.epc = regs->mepc;
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return sbi_trap_redirect(regs, &uptrap);
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}
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insn_len = INSN_LEN(insn);
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}
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if ((insn & INSN_MASK_LW) == INSN_MATCH_LW) {
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@ -134,7 +136,7 @@ int sbi_misaligned_load_handler(ulong addr, ulong tval2, ulong tinst,
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SET_F32_RD(insn, regs, val.data_ulong);
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#endif
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regs->mepc += INSN_LEN(insn);
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regs->mepc += insn_len;
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return 0;
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}
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@ -142,7 +144,7 @@ int sbi_misaligned_load_handler(ulong addr, ulong tval2, ulong tinst,
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int sbi_misaligned_store_handler(ulong addr, ulong tval2, ulong tinst,
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struct sbi_trap_regs *regs)
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{
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ulong insn;
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ulong insn, insn_len;
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union reg_data val;
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struct sbi_trap_info uptrap;
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int i, len = 0;
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@ -153,6 +155,7 @@ int sbi_misaligned_store_handler(ulong addr, ulong tval2, ulong tinst,
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* transformed instruction or custom instruction.
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*/
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insn = tinst | INSN_16BIT_MASK;
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insn_len = (tinst & 0x2) ? INSN_LEN(insn) : 2;
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} else {
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/*
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* Bit[0] == 0 implies trapped instruction value is
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@ -163,6 +166,7 @@ int sbi_misaligned_store_handler(ulong addr, ulong tval2, ulong tinst,
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uptrap.epc = regs->mepc;
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return sbi_trap_redirect(regs, &uptrap);
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}
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insn_len = INSN_LEN(insn);
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}
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val.data_ulong = GET_RS2(insn, regs);
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@ -233,7 +237,7 @@ int sbi_misaligned_store_handler(ulong addr, ulong tval2, ulong tinst,
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}
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}
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regs->mepc += INSN_LEN(insn);
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regs->mepc += insn_len;
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return 0;
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}
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