361 lines
16 KiB
C
361 lines
16 KiB
C
/*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*/
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/*
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* parse_t30.h - Definitions for the dev/sdram parameters
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*/
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#include "../parse.h"
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#include "nvboot_bct_t30.h"
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enum_item s_devtype_table_t30[] = {
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{ "NvBootDevType_Sdmmc", nvboot_dev_type_sdmmc },
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{ "NvBootDevType_Spi", nvboot_dev_type_spi },
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{ "NvBootDevType_Nand", nvboot_dev_type_nand },
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{ "Sdmmc", nvboot_dev_type_sdmmc },
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{ "Spi", nvboot_dev_type_spi },
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{ "Nand", nvboot_dev_type_nand },
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{ NULL, 0 }
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};
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enum_item s_sdmmc_data_width_table_t30[] = {
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{
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"NvBootSdmmcDataWidth_4Bit",
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nvboot_sdmmc_data_width_4bit
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},
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{
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"NvBootSdmmcDataWidth_8Bit",
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nvboot_sdmmc_data_width_8bit
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},
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{ "4Bit", nvboot_sdmmc_data_width_4bit },
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{ "8Bit", nvboot_sdmmc_data_width_8bit },
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{ NULL, 0 }
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};
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enum_item s_spi_clock_source_table_t30[] = {
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{
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"NvBootSpiClockSource_PllPOut0",
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nvboot_spi_clock_source_pllp_out0
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},
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{
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"NvBootSpiClockSource_PllCOut0",
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nvboot_spi_clock_source_pllc_out0
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},
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{
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"NvBootSpiClockSource_PllMOut0",
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nvboot_spi_clock_source_pllm_out0
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},
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{
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"NvBootSpiClockSource_ClockM",
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nvboot_spi_clock_source_clockm
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},
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{ "ClockSource_PllPOut0", nvboot_spi_clock_source_pllp_out0 },
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{ "ClockSource_PllCOut0", nvboot_spi_clock_source_pllc_out0 },
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{ "ClockSource_PllMOut0", nvboot_spi_clock_source_pllm_out0 },
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{ "ClockSource_ClockM", nvboot_spi_clock_source_clockm },
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{ "PllPOut0", nvboot_spi_clock_source_pllp_out0 },
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{ "PllCOut0", nvboot_spi_clock_source_pllc_out0 },
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{ "PllMOut0", nvboot_spi_clock_source_pllm_out0 },
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{ "ClockM", nvboot_spi_clock_source_clockm },
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{ NULL, 0 }
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};
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enum_item s_nvboot_memory_type_table_t30[] = {
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{ "NvBootMemoryType_None", nvboot_memory_type_none },
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{ "NvBootMemoryType_Ddr3", nvboot_memory_type_ddr3 },
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{ "NvBootMemoryType_Ddr2", nvboot_memory_type_ddr2 },
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{ "NvBootMemoryType_Ddr", nvboot_memory_type_ddr },
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{ "NvBootMemoryType_LpDdr2", nvboot_memory_type_lpddr2 },
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{ "NvBootMemoryType_LpDdr", nvboot_memory_type_lpddr },
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{ "None", nvboot_memory_type_none },
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{ "Ddr3", nvboot_memory_type_ddr3 },
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{ "Ddr2", nvboot_memory_type_ddr2 },
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{ "Ddr", nvboot_memory_type_ddr },
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{ "LpDdr2", nvboot_memory_type_lpddr2 },
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{ "LpDdr", nvboot_memory_type_lpddr },
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{ NULL, 0 }
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};
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#define TOKEN(name) \
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token_##name, field_type_u32, NULL
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field_item s_sdram_field_table_t30[] = {
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{ "MemoryType", token_memory_type,
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field_type_enum, s_nvboot_memory_type_table_t30 },
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{ "PllMChargePumpSetupControl", TOKEN(pllm_charge_pump_setup_ctrl) },
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{ "PllMLoopFilterSetupControl", TOKEN(pllm_loop_filter_setup_ctrl) },
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{ "PllMInputDivider", TOKEN(pllm_input_divider) },
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{ "PllMFeedbackDivider", TOKEN(pllm_feedback_divider) },
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{ "PllMPostDivider", TOKEN(pllm_post_divider) },
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{ "PllMStableTime", TOKEN(pllm_stable_time) },
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{ "EmcClockDivider", TOKEN(emc_clock_divider) },
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{ "EmcAutoCalInterval", TOKEN(emc_auto_cal_interval) },
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{ "EmcAutoCalConfig", TOKEN(emc_auto_cal_config) },
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{ "EmcAutoCalWait", TOKEN(emc_auto_cal_wait) },
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{ "EmcPinProgramWait", TOKEN(emc_pin_program_wait) },
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{ "EmcRc", TOKEN(emc_rc) },
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{ "EmcRfc", TOKEN(emc_rfc) },
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{ "EmcRas", TOKEN(emc_ras) },
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{ "EmcRp", TOKEN(emc_rp) },
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{ "EmcR2w", TOKEN(emc_r2w) },
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{ "EmcW2r", TOKEN(emc_w2r) },
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{ "EmcR2p", TOKEN(emc_r2p) },
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{ "EmcW2p", TOKEN(emc_w2p) },
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{ "EmcRrd", TOKEN(emc_rrd) },
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{ "EmcRdRcd", TOKEN(emc_rd_rcd) },
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{ "EmcWrRcd", TOKEN(emc_wr_rcd) },
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{ "EmcRext", TOKEN(emc_rext) },
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{ "EmcWdv", TOKEN(emc_wdv) },
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{ "EmcQUseExtra", TOKEN(emc_quse_extra) },
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{ "EmcQUse", TOKEN(emc_quse) },
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{ "EmcQRst", TOKEN(emc_qrst) },
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{ "EmcQSafe", TOKEN(emc_qsafe) },
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{ "EmcRdv", TOKEN(emc_rdv) },
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{ "EmcRefresh", TOKEN(emc_refresh) },
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{ "EmcBurstRefreshNum", TOKEN(emc_burst_refresh_num) },
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{ "EmcPdEx2Wr", TOKEN(emc_pdex2wr) },
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{ "EmcPdEx2Rd", TOKEN(emc_pdex2rd) },
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{ "EmcPChg2Pden", TOKEN(emc_pchg2pden) },
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{ "EmcAct2Pden", TOKEN(emc_act2pden) },
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{ "EmcAr2Pden", TOKEN(emc_ar2pden) },
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{ "EmcRw2Pden", TOKEN(emc_rw2pden) },
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{ "EmcTxsr", TOKEN(emc_txsr) },
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{ "EmcTcke", TOKEN(emc_tcke) },
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{ "EmcTfaw", TOKEN(emc_tfaw) },
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{ "EmcTrpab", TOKEN(emc_trpab) },
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{ "EmcTClkStable", TOKEN(emc_tclkstable) },
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{ "EmcTClkStop", TOKEN(emc_tclkstop) },
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{ "EmcTRefBw", TOKEN(emc_trefbw) },
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{ "EmcFbioCfg5", TOKEN(emc_fbio_cfg5) },
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{ "EmcFbioCfg6", TOKEN(emc_fbio_cfg6) },
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{ "EmcFbioSpare", TOKEN(emc_fbio_spare) },
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{ "EmcMrsResetDllWait", TOKEN(emc_mrs_reset_dll_wait) },
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{ "EmcMrsResetDll", TOKEN(emc_mrs_reset_dll) },
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{ "EmcMrsDdr2DllReset", TOKEN(emc_mrs_ddr2_dll_reset) },
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{ "EmcMrs", TOKEN(emc_mrs) },
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{ "EmcEmrsEmr2", TOKEN(emc_emrs_emr2) },
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{ "EmcEmrsEmr3", TOKEN(emc_emrs_emr3) },
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{ "EmcEmrsDdr2DllEnable", TOKEN(emc_emrs_ddr2_dll_enable) },
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{ "EmcEmrsDdr2OcdCalib", TOKEN(emc_emrs_ddr2_ocd_calib) },
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{ "EmcEmrs", TOKEN(emc_emrs) },
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{ "EmcMrw1", TOKEN(emc_mrw1) },
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{ "EmcMrw2", TOKEN(emc_mrw2) },
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{ "EmcMrw3", TOKEN(emc_mrw3) },
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{ "EmcMrwResetCommand", TOKEN(emc_mrw_reset_command) },
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{ "EmcMrwResetNInitWait", TOKEN(emc_mrw_reset_ninit_wait) },
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{ "EmcAdrCfg", TOKEN(emc_adr_cfg) },
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{ "McEmemCfg", TOKEN(mc_emem_cfg) },
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{ "EmcCfg2", TOKEN(emc_cfg2) },
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{ "EmcCfgDigDll", TOKEN(emc_cfg_dig_dll) },
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{ "EmcCfgDigDllPeriod", TOKEN(emc_cfg_dig_dll_period) },
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{ "EmcCfg", TOKEN(emc_cfg) },
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{ "EmcDbg", TOKEN(emc_dbg) },
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{ "WarmBootWait", TOKEN(warm_boot_wait) },
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{ "EmcCttTermCtrl", TOKEN(emc_ctt_term_ctrl) },
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{ "EmcOdtWrite", TOKEN(emc_odt_write) },
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{ "EmcOdtRead", TOKEN(emc_odt_read) },
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{ "EmcZcalWaitCnt", TOKEN(emc_zcal_wait_cnt) },
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{ "EmcZcalMrwCmd", TOKEN(emc_zcal_mrw_cmd) },
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{ "EmcDdr2Wait", TOKEN(emc_ddr2_wait) },
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{ "PmcDdrPwr", TOKEN(pmc_ddr_pwr) },
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{ "EmcClockSource", TOKEN(emc_clock_source) },
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{ "EmcClockUsePllMUD", TOKEN(emc_clock_use_pll_mud) },
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{ "EmcPinExtraWait", TOKEN(emc_pin_extra_wait) },
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{ "EmcTimingControlWait", TOKEN(emc_timing_control_wait) },
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{ "EmcWext", TOKEN(emc_wext) },
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{ "EmcCtt", TOKEN(emc_ctt) },
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{ "EmcCttDuration", TOKEN(emc_ctt_duration) },
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{ "EmcPreRefreshReqCnt", TOKEN(emc_prerefresh_req_cnt) },
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{ "EmcTxsrDll", TOKEN(emc_txsr_dll) },
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{ "EmcCfgRsv", TOKEN(emc_cfg_rsv) },
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{ "EmcMrwExtra", TOKEN(emc_mrw_extra) },
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{ "EmcWarmBootMrw1", TOKEN(emc_warm_boot_mrw1) },
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{ "EmcWarmBootMrw2", TOKEN(emc_warm_boot_mrw2) },
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{ "EmcWarmBootMrw3", TOKEN(emc_warm_boot_mrw3) },
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{ "EmcWarmBootMrwExtra", TOKEN(emc_warm_boot_mrw_extra) },
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{ "EmcWarmBootExtraModeRegWriteEnable",
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TOKEN(emc_warm_boot_extramode_reg_write_enable) },
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{ "EmcExtraModeRegWriteEnable", TOKEN(emc_extramode_reg_write_enable) },
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{ "EmcMrsWaitCnt", TOKEN(emc_mrs_wait_cnt) },
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{ "EmcCmdQ", TOKEN(emc_cmd_q) },
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{ "EmcMc2EmcQ", TOKEN(emc_mc2emc_q) },
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{ "EmcDynSelfRefControl", TOKEN(emc_dyn_self_ref_control) },
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{ "AhbArbitrationXbarCtrlMemInitDone",
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TOKEN(ahb_arbitration_xbar_ctrl_meminit_done) },
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{ "EmcDevSelect", TOKEN(emc_dev_select) },
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{ "EmcSelDpdCtrl", TOKEN(emc_sel_dpd_ctrl) },
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{ "EmcDllXformDqs0", TOKEN(emc_dll_xform_dqs0) },
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{ "EmcDllXformDqs1", TOKEN(emc_dll_xform_dqs1) },
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{ "EmcDllXformDqs2", TOKEN(emc_dll_xform_dqs2) },
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{ "EmcDllXformDqs3", TOKEN(emc_dll_xform_dqs3) },
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{ "EmcDllXformDqs4", TOKEN(emc_dll_xform_dqs4) },
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{ "EmcDllXformDqs5", TOKEN(emc_dll_xform_dqs5) },
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{ "EmcDllXformDqs6", TOKEN(emc_dll_xform_dqs6) },
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{ "EmcDllXformDqs7", TOKEN(emc_dll_xform_dqs7) },
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{ "EmcDllXformQUse0", TOKEN(emc_dll_xform_quse0) },
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{ "EmcDllXformQUse1", TOKEN(emc_dll_xform_quse1) },
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{ "EmcDllXformQUse2", TOKEN(emc_dll_xform_quse2) },
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{ "EmcDllXformQUse3", TOKEN(emc_dll_xform_quse3) },
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{ "EmcDllXformQUse4", TOKEN(emc_dll_xform_quse4) },
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{ "EmcDllXformQUse5", TOKEN(emc_dll_xform_quse5) },
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{ "EmcDllXformQUse6", TOKEN(emc_dll_xform_quse6) },
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{ "EmcDllXformQUse7", TOKEN(emc_dll_xform_quse7) },
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{ "EmcDliTrimTxDqs0", TOKEN(emc_dli_trim_tx_dqs0) },
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{ "EmcDliTrimTxDqs1", TOKEN(emc_dli_trim_tx_dqs1) },
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{ "EmcDliTrimTxDqs2", TOKEN(emc_dli_trim_tx_dqs2) },
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{ "EmcDliTrimTxDqs3", TOKEN(emc_dli_trim_tx_dqs3) },
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{ "EmcDliTrimTxDqs4", TOKEN(emc_dli_trim_tx_dqs4) },
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{ "EmcDliTrimTxDqs5", TOKEN(emc_dli_trim_tx_dqs5) },
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{ "EmcDliTrimTxDqs6", TOKEN(emc_dli_trim_tx_dqs6) },
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{ "EmcDliTrimTxDqs7", TOKEN(emc_dli_trim_tx_dqs7) },
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{ "EmcDllXformDq0", TOKEN(emc_dll_xform_dq0) },
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{ "EmcDllXformDq1", TOKEN(emc_dll_xform_dq1) },
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{ "EmcDllXformDq2", TOKEN(emc_dll_xform_dq2) },
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{ "EmcDllXformDq3", TOKEN(emc_dll_xform_dq3) },
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{ "EmcZcalInterval", TOKEN(emc_zcal_interval) },
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{ "EmcZcalInitDev0", TOKEN(emc_zcal_init_dev0) },
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{ "EmcZcalInitDev1", TOKEN(emc_zcal_init_dev1) },
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{ "EmcZcalInitWait", TOKEN(emc_zcal_init_wait) },
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{ "EmcZcalColdBootEnable", TOKEN(emc_zcal_cold_boot_enable) },
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{ "EmcZcalWarmBootEnable", TOKEN(emc_zcal_warm_boot_enable) },
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{ "EmcMrwLpddr2ZcalWarmBoot", TOKEN(emc_mrw_lpddr2zcal_warm_boot) },
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{ "EmcZqCalDdr3WarmBoot", TOKEN(emc_zqcal_ddr3_warm_boot) },
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{ "EmcZcalWarmBootWait", TOKEN(emc_zcal_warm_boot_wait) },
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{ "EmcMrsWarmBootEnable", TOKEN(emc_mrs_warm_boot_enable) },
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{ "EmcMrsExtra", TOKEN(emc_mrs_extra) },
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{ "EmcWarmBootMrs", TOKEN(emc_warm_boot_mrs) },
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{ "EmcWarmBootEmrs", TOKEN(emc_warm_boot_emrs) },
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{ "EmcWarmBootEmr2", TOKEN(emc_warm_boot_emr2) },
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{ "EmcWarmBootEmr3", TOKEN(emc_warm_boot_emr3) },
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{ "EmcWarmBootMrsExtra", TOKEN(emc_warm_boot_mrs_extra) },
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{ "EmcClkenOverride", TOKEN(emc_clken_override) },
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{ "EmcExtraRefreshNum", TOKEN(emc_extra_refresh_num) },
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{ "EmcClkenOverrideAllWarmBoot",
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TOKEN(emc_clken_override_allwarm_boot) },
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{ "McClkenOverrideAllWarmBoot", TOKEN(mc_clken_override_allwarm_boot) },
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{ "EmcCfgDigDllPeriodWarmBoot",
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TOKEN(emc_cfg_dig_dll_period_warm_boot) },
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{ "PmcVddpSel", TOKEN(pmc_vddp_sel) },
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{ "PmcDdrCfg", TOKEN(pmc_ddr_cfg) },
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{ "PmcIoDpdReq", TOKEN(pmc_io_dpd_req) },
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{ "PmcENoVttGen", TOKEN(pmc_eno_vtt_gen) },
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{ "PmcNoIoPower", TOKEN(pmc_no_io_power) },
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{ "EmcXm2CmdPadCtrl", TOKEN(emc_xm2cmd_pad_ctrl) },
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{ "EmcXm2CmdPadCtrl2", TOKEN(emc_xm2cmd_pad_ctrl2) },
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{ "EmcXm2DqsPadCtrl", TOKEN(emc_xm2dqs_pad_ctrl) },
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{ "EmcXm2DqsPadCtrl2", TOKEN(emc_xm2dqs_pad_ctrl2) },
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{ "EmcXm2DqsPadCtrl3", TOKEN(emc_xm2dqs_pad_ctrl3) },
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{ "EmcXm2DqPadCtrl", TOKEN(emc_xm2dq_pad_ctrl) },
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{ "EmcXm2DqPadCtrl2", TOKEN(emc_xm2dq_pad_ctrl2) },
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{ "EmcXm2ClkPadCtrl", TOKEN(emc_xm2clk_pad_ctrl) },
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{ "EmcXm2CompPadCtrl", TOKEN(emc_xm2comp_pad_ctrl) },
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{ "EmcXm2VttGenPadCtrl", TOKEN(emc_xm2vttgen_pad_ctrl) },
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{ "EmcXm2VttGenPadCtrl2", TOKEN(emc_xm2vttgen_pad_ctrl2) },
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{ "EmcXm2QUsePadCtrl", TOKEN(emc_xm2quse_pad_ctrl) },
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{ "McEmemAdrCfg", TOKEN(mc_emem_adr_cfg) },
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{ "McEmemAdrCfgDev0", TOKEN(mc_emem_adr_cfg_dev0) },
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{ "McEmemAdrCfgDev1", TOKEN(mc_emem_adr_cfg_dev1) },
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{ "McEmemArbCfg", TOKEN(mc_emem_arb_cfg) },
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{ "McEmemArbOutstandingReq", TOKEN(mc_emem_arb_outstanding_req) },
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{ "McEmemArbTimingRcd", TOKEN(mc_emem_arb_timing_rcd) },
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{ "McEmemArbTimingRp", TOKEN(mc_emem_arb_timing_rp) },
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{ "McEmemArbTimingRc", TOKEN(mc_emem_arb_timing_rc) },
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{ "McEmemArbTimingRas", TOKEN(mc_emem_arb_timing_ras) },
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{ "McEmemArbTimingFaw", TOKEN(mc_emem_arb_timing_faw) },
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{ "McEmemArbTimingRrd", TOKEN(mc_emem_arb_timing_rrd) },
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{ "McEmemArbTimingRap2Pre", TOKEN(mc_emem_arb_timing_rap2pre) },
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{ "McEmemArbTimingWap2Pre", TOKEN(mc_emem_arb_timing_wap2pre) },
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{ "McEmemArbTimingR2R", TOKEN(mc_emem_arb_timing_r2r) },
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{ "McEmemArbTimingW2W", TOKEN(mc_emem_arb_timing_w2w) },
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{ "McEmemArbTimingR2W", TOKEN(mc_emem_arb_timing_r2w) },
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{ "McEmemArbTimingW2R", TOKEN(mc_emem_arb_timing_w2r) },
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{ "McEmemArbDaTurns", TOKEN(mc_emem_arb_da_turns) },
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{ "McEmemArbDaCovers", TOKEN(mc_emem_arb_da_covers) },
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{ "McEmemArbMisc0", TOKEN(mc_emem_arb_misc0) },
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{ "McEmemArbMisc1", TOKEN(mc_emem_arb_misc1) },
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{ "McEmemArbRing1Throttle", TOKEN(mc_emem_arb_ring1_throttle) },
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{ "McEmemArbOverride", TOKEN(mc_emem_arb_override) },
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{ "McEmemArbRsv", TOKEN(mc_emem_arb_rsv) },
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{ "McClkenOverride", TOKEN(mc_clken_override) },
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{ NULL, 0, 0, NULL }
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};
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field_item s_nand_table_t30[] = {
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/* Note: NandTiming2 must appear before NandTiming, because NandTiming
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* is a prefix of NandTiming2 and would otherwise match first.
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*/
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{ "ClockDivider", TOKEN(nand_clock_divider) },
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{ "BlockSizeLog2", TOKEN(nand_block_size_log2) },
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{ "PageSizeLog2", TOKEN(nand_page_size_log2) },
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{ "NandAsyncTiming3", TOKEN(nand_async_timing3) },
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{ "NandAsyncTiming2", TOKEN(nand_async_timing2) },
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{ "NandAsyncTiming1", TOKEN(nand_async_timing1) },
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{ "NandAsyncTiming0", TOKEN(nand_async_timing0) },
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{ "DisableSyncDDR", TOKEN(nand_disable_sync_ddr) },
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{ "NandSDDRTiming1", TOKEN(nand_sddr_timing1) },
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{ "NandSDDRTiming0", TOKEN(nand_sddr_timing0) },
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{ "NandTDDRTiming1", TOKEN(nand_tddr_timing1) },
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{ "NandTDDRTiming0", TOKEN(nand_tddr_timing0) },
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{ "NandFbioDqsibDlyByte", TOKEN(nand_fbio_dqsib_dly_byte) },
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{ "NandFbioQuseDlyByte", TOKEN(nand_fbio_quse_dly_byte) },
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{ "NandFbioCfgQuseLate", TOKEN(nand_fbio_cfg_quse_late) },
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{ NULL, 0, 0, NULL }
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};
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|
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field_item s_sdmmc_table_t30[] = {
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{ "ClockDivider", TOKEN(sdmmc_clock_divider) },
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{ "DataWidth",
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token_sdmmc_data_width,
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field_type_enum,
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s_sdmmc_data_width_table_t30 },
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{ "MaxPowerClassSupported", TOKEN(sdmmc_max_power_class_supported) },
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{ "SdController", TOKEN(sdmmc_sd_controller) },
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{ NULL, 0, 0, NULL }
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};
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field_item s_spiflash_table_t30[] = {
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{ "ReadCommandTypeFast", TOKEN(spiflash_read_command_type_fast) },
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{ "ClockDivider", TOKEN(spiflash_clock_divider) },
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{ "ClockSource",
|
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token_spiflash_clock_source,
|
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field_type_enum,
|
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s_spi_clock_source_table_t30 },
|
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{ NULL, 0, 0, NULL }
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};
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|
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parse_subfield_item s_device_type_table_t30[] = {
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{ "NandParams.", token_nand_params,
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s_nand_table_t30, t30_set_dev_param },
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{ "SdmmcParams.", token_sdmmc_params,
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s_sdmmc_table_t30, t30_set_dev_param },
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{ "SpiFlashParams.", token_spiflash_params,
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|
s_spiflash_table_t30, t30_set_dev_param },
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|
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{ NULL, 0, NULL }
|
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};
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