206 lines
7.0 KiB
Ada
206 lines
7.0 KiB
Ada
--
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-- Copyright (C) 2016 Nico Huber <nico.h@gmx.de>
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; version 2 of the License.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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with HW.GFX.DP_Training;
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with HW.GFX.GMA.DP_Aux_Ch;
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with HW.GFX.GMA.DP_Info;
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with HW.GFX.GMA.Registers;
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with HW.Debug;
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with GNAT.Source_Info;
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package body HW.GFX.GMA.PCH.DP is
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type DP_Array is array (PCH_DP_Port) of Registers.Registers_Index;
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DP_CTL : constant DP_Array :=
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(PCH_DP_B => Registers.PCH_DP_B,
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PCH_DP_C => Registers.PCH_DP_C,
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PCH_DP_D => Registers.PCH_DP_D);
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DP_CTL_DISPLAY_PORT_ENABLE : constant := 1 * 2 ** 31;
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DP_CTL_VSWING_LEVEL_SET_SHIFT : constant := 25;
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DP_CTL_VSWING_LEVEL_SET_MASK : constant := 7 * 2 ** 25;
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DP_CTL_PREEMPH_LEVEL_SET_SHIFT : constant := 22;
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DP_CTL_PREEMPH_LEVEL_SET_MASK : constant := 7 * 2 ** 22;
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DP_CTL_PORT_WIDTH_SHIFT : constant := 19;
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DP_CTL_PORT_REVERSAL : constant := 1 * 2 ** 15;
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DP_CTL_LINK_TRAIN_MASK : constant := 7 * 2 ** 8;
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DP_CTL_LINK_TRAIN_PAT1 : constant := 0 * 2 ** 8;
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DP_CTL_LINK_TRAIN_PAT2 : constant := 1 * 2 ** 8;
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DP_CTL_LINK_TRAIN_IDLE : constant := 2 * 2 ** 8;
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DP_CTL_LINK_TRAIN_NORMAL : constant := 3 * 2 ** 8;
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DP_CTL_AUDIO_OUTPUT_ENABLE : constant := 1 * 2 ** 6;
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DP_CTL_PORT_DETECT : constant := 1 * 2 ** 2;
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function DP_CTL_VSWING_LEVEL_SET
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(VS : DP_Info.DP_Voltage_Swing)
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return Word32
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is
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begin
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return Shift_Left
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(Word32 (DP_Info.DP_Voltage_Swing'Pos (VS)),
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DP_CTL_VSWING_LEVEL_SET_SHIFT);
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end DP_CTL_VSWING_LEVEL_SET;
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function DP_CTL_PREEMPH_LEVEL_SET (PE : DP_Info.DP_Pre_Emph) return Word32
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is
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begin
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return Shift_Left
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(Word32 (DP_Info.DP_Pre_Emph'Pos (PE)), DP_CTL_PREEMPH_LEVEL_SET_SHIFT);
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end DP_CTL_PREEMPH_LEVEL_SET;
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function DP_CTL_PORT_WIDTH (Lane_Count : DP_Lane_Count) return Word32
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is
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begin
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return Shift_Left
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(Word32 (Lane_Count_As_Integer (Lane_Count)) - 1,
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DP_CTL_PORT_WIDTH_SHIFT);
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end DP_CTL_PORT_WIDTH;
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type DP_CTL_LINK_TRAIN_Array is array (DP_Info.Training_Pattern) of Word32;
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DP_CTL_LINK_TRAIN : constant DP_CTL_LINK_TRAIN_Array :=
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(DP_Info.TP_1 => DP_CTL_LINK_TRAIN_PAT1,
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DP_Info.TP_2 => DP_CTL_LINK_TRAIN_PAT2,
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DP_Info.TP_3 => DP_CTL_LINK_TRAIN_PAT2,
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DP_Info.TP_Idle => DP_CTL_LINK_TRAIN_IDLE,
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DP_Info.TP_None => DP_CTL_LINK_TRAIN_NORMAL);
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----------------------------------------------------------------------------
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pragma Warnings (GNATprove, Off, "unused variable ""Port""",
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Reason => "Needed for a common interface");
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function Max_V_Swing
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(Port : PCH_DP_Port)
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return DP_Info.DP_Voltage_Swing
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is
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begin
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return DP_Info.VS_Level_3;
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end Max_V_Swing;
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function Max_Pre_Emph
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(Port : PCH_DP_Port;
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Train_Set : DP_Info.Train_Set)
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return DP_Info.DP_Pre_Emph
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is
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begin
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return
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(case Train_Set.Voltage_Swing is
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when DP_Info.VS_Level_0 => DP_Info.Emph_Level_3,
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when DP_Info.VS_Level_1 => DP_Info.Emph_Level_2,
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when DP_Info.VS_Level_2 => DP_Info.Emph_Level_1,
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when DP_Info.VS_Level_3 => DP_Info.Emph_Level_0);
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end Max_Pre_Emph;
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----------------------------------------------------------------------------
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pragma Warnings (GNATprove, Off, "unused variable ""Link""",
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Reason => "Needed for a common interface");
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procedure Set_Training_Pattern
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(Port : PCH_DP_Port;
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Link : DP_Link;
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Pattern : DP_Info.Training_Pattern)
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is
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begin
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Registers.Unset_And_Set_Mask
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(Register => DP_CTL (Port),
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Mask_Unset => DP_CTL_LINK_TRAIN_MASK,
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Mask_Set => DP_CTL_LINK_TRAIN (Pattern));
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end Set_Training_Pattern;
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procedure Set_Signal_Levels
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(Port : PCH_DP_Port;
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Link : DP_Link;
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Train_Set : DP_Info.Train_Set)
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is
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begin
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Registers.Unset_And_Set_Mask
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(Register => DP_CTL (Port),
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Mask_Unset => DP_CTL_VSWING_LEVEL_SET_MASK or
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DP_CTL_PREEMPH_LEVEL_SET_MASK,
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Mask_Set => DP_CTL_VSWING_LEVEL_SET (Train_Set.Voltage_Swing) or
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DP_CTL_PREEMPH_LEVEL_SET (Train_Set.Pre_Emph));
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end Set_Signal_Levels;
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procedure Off (Port : PCH_DP_Port)
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is
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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Registers.Unset_And_Set_Mask
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(Register => DP_CTL (Port),
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Mask_Unset => DP_CTL_LINK_TRAIN_MASK,
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Mask_Set => DP_CTL_LINK_TRAIN_IDLE);
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Registers.Posting_Read (DP_CTL (Port));
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Registers.Write (DP_CTL (Port), 0);
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Registers.Posting_Read (DP_CTL (Port));
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end Off;
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pragma Warnings (GNATprove, On, "unused variable ""Port""");
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pragma Warnings (GNATprove, On, "unused variable ""Link""");
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----------------------------------------------------------------------------
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procedure On
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(Port_Cfg : in Port_Config;
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Success : out Boolean)
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is
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function To_DP (Port : PCH_DP_Port) return DP_Port
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is
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begin
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return
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(case Port is
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when PCH_DP_B => DP_B,
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when PCH_DP_C => DP_C,
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when PCH_DP_D => DP_D);
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end To_DP;
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package Training is new DP_Training
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(TPS3_Supported => False,
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T => PCH_DP_Port,
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Aux_T => DP_Port,
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Aux_Ch => DP_Aux_Ch,
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DP_Info => DP_Info,
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To_Aux => To_DP,
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Max_V_Swing => Max_V_Swing,
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Max_Pre_Emph => Max_Pre_Emph,
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Set_Pattern => Set_Training_Pattern,
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Set_Signal_Levels => Set_Signal_Levels,
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Off => Off);
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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Registers.Write
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(Register => DP_CTL (Port_Cfg.PCH_Port),
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Value => DP_CTL_DISPLAY_PORT_ENABLE or
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DP_CTL_PORT_WIDTH (Port_Cfg.DP.Lane_Count) or
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DP_CTL_LINK_TRAIN_PAT1);
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Training.Train_DP
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(Port => Port_Cfg.PCH_Port,
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Link => Port_Cfg.DP,
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Success => Success);
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end On;
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----------------------------------------------------------------------------
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procedure All_Off
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is
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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for Port in PCH_DP_Port loop
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Off (Port);
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end loop;
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end All_Off;
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end HW.GFX.GMA.PCH.DP;
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