343 lines
12 KiB
Ada
343 lines
12 KiB
Ada
--
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-- Copyright (C) 2016 secunet Security Networks AG
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; version 2 of the License.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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with HW.Time;
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with HW.GFX.GMA.Config;
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with HW.GFX.GMA.PCH.FDI;
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with HW.GFX.GMA.Registers;
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with HW.Debug;
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with GNAT.Source_Info;
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package body HW.GFX.GMA.Connectors.FDI
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is
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PCH_FDI_CHICKEN_B_AND_C : constant := 1 * 2 ** 12;
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type TX_CTL_Regs is array (GPU_FDI_Port) of Registers.Registers_Index;
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TX_CTL : constant TX_CTL_Regs :=
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(DIGI_B => Registers.FDI_TX_CTL_A,
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DIGI_C => Registers.FDI_TX_CTL_B,
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DIGI_D => Registers.FDI_TX_CTL_C);
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FDI_TX_CTL_FDI_TX_ENABLE : constant := 1 * 2 ** 31;
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FDI_TX_CTL_VP_MASK : constant := 16#3f# * 2 ** 22;
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FDI_TX_CTL_PORT_WIDTH_SEL_SHIFT : constant := 19;
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FDI_TX_CTL_ENHANCED_FRAMING_ENABLE : constant := 1 * 2 ** 18;
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FDI_TX_CTL_FDI_PLL_ENABLE : constant := 1 * 2 ** 14;
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FDI_TX_CTL_COMPOSITE_SYNC_SELECT : constant := 1 * 2 ** 11;
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FDI_TX_CTL_AUTO_TRAIN_ENABLE : constant := 1 * 2 ** 10;
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FDI_TX_CTL_AUTO_TRAIN_DONE : constant := 1 * 2 ** 1;
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TP_SHIFT : constant := (if Config.CPU <= Sandybridge then 28 else 8);
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FDI_TX_CTL_TRAINING_PATTERN_MASK : constant := 3 * 2 ** TP_SHIFT;
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FDI_TX_CTL_TRAINING_PATTERN_1 : constant := 0 * 2 ** TP_SHIFT;
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FDI_TX_CTL_TRAINING_PATTERN_2 : constant := 1 * 2 ** TP_SHIFT;
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FDI_TX_CTL_TRAINING_PATTERN_IDLE : constant := 2 * 2 ** TP_SHIFT;
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FDI_TX_CTL_TRAINING_PATTERN_NORMAL : constant := 3 * 2 ** TP_SHIFT;
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subtype FDI_TX_CTL_VP_T is Natural range 0 .. 3;
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type Vswing_Preemph_Values is array (FDI_TX_CTL_VP_T) of Word32;
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FDI_TX_CTL_VSWING_PREEMPH : constant Vswing_Preemph_Values :=
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(0 => 16#00# * 2 ** 22,
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1 => 16#3a# * 2 ** 22,
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2 => 16#39# * 2 ** 22,
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3 => 16#38# * 2 ** 22);
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function FDI_TX_CTL_PORT_WIDTH_SEL (Lane_Count : DP_Lane_Count) return Word32
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is
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begin
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return Shift_Left
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(Word32 (Lane_Count_As_Integer (Lane_Count)) - 1,
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FDI_TX_CTL_PORT_WIDTH_SEL_SHIFT);
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end FDI_TX_CTL_PORT_WIDTH_SEL;
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----------------------------------------------------------------------------
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--
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-- This is usually used with Ivy Bridge.
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--
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procedure Auto_Training
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(Port_Cfg : in Port_Config;
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Success : out Boolean)
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with
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Pre => Port_Cfg.Port in GPU_FDI_Port
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is
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PCH_FDI_Port : constant PCH.FDI_Port_Type := PCH_FDIs (Port_Cfg.Port);
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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-- try each preemph/voltage pair twice
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for VP2 in Natural range 0 .. FDI_TX_CTL_VP_T'Last * 2 + 1
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loop
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Registers.Unset_And_Set_Mask
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(Register => TX_CTL (Port_Cfg.Port),
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Mask_Unset => FDI_TX_CTL_VP_MASK or
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FDI_TX_CTL_TRAINING_PATTERN_MASK,
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Mask_Set => FDI_TX_CTL_FDI_TX_ENABLE or
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FDI_TX_CTL_VSWING_PREEMPH (VP2 / 2) or
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FDI_TX_CTL_AUTO_TRAIN_ENABLE or
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FDI_TX_CTL_TRAINING_PATTERN_1);
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Registers.Posting_Read (TX_CTL (Port_Cfg.Port));
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PCH.FDI.Auto_Train (PCH_FDI_Port);
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-- read at least twice
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for I in 0 .. 3 loop
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Registers.Is_Set_Mask
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(Register => TX_CTL (Port_Cfg.Port),
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Mask => FDI_TX_CTL_AUTO_TRAIN_DONE,
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Result => Success);
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exit when Success or I = 3;
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Time.U_Delay (1);
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end loop;
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exit when Success;
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Registers.Unset_And_Set_Mask
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(Register => TX_CTL (Port_Cfg.Port),
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Mask_Unset => FDI_TX_CTL_FDI_TX_ENABLE or
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FDI_TX_CTL_AUTO_TRAIN_ENABLE or
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FDI_TX_CTL_TRAINING_PATTERN_MASK,
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Mask_Set => FDI_TX_CTL_TRAINING_PATTERN_1);
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PCH.FDI.Off (PCH_FDI_Port, PCH.FDI.Rx_Off);
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end loop;
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if Success then
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PCH.FDI.Enable_EC (PCH_FDI_Port);
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else
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Registers.Unset_Mask
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(Register => TX_CTL (Port_Cfg.Port),
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Mask => FDI_TX_CTL_FDI_PLL_ENABLE);
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PCH.FDI.Off (PCH_FDI_Port, PCH.FDI.Clock_Off);
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end if;
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end Auto_Training;
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----------------------------------------------------------------------------
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--
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-- Used with Sandy Bridge (should work with Ivy Bridge too)
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--
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procedure Full_Training
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(Port_Cfg : in Port_Config;
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Success : out Boolean)
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with
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Pre => Port_Cfg.Port in GPU_FDI_Port
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is
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PCH_FDI_Port : constant PCH.FDI_Port_Type := PCH_FDIs (Port_Cfg.Port);
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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-- try each preemph/voltage pair twice
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for VP2 in Natural range 0 .. FDI_TX_CTL_VP_T'Last * 2 + 1
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loop
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Registers.Unset_And_Set_Mask
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(Register => TX_CTL (Port_Cfg.Port),
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Mask_Unset => FDI_TX_CTL_VP_MASK or
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FDI_TX_CTL_TRAINING_PATTERN_MASK,
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Mask_Set => FDI_TX_CTL_FDI_TX_ENABLE or
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FDI_TX_CTL_VSWING_PREEMPH (VP2 / 2) or
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FDI_TX_CTL_TRAINING_PATTERN_1);
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Registers.Posting_Read (TX_CTL (Port_Cfg.Port));
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PCH.FDI.Train (PCH_FDI_Port, PCH.FDI.TP_1, Success);
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if Success then
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Registers.Unset_And_Set_Mask
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(Register => TX_CTL (Port_Cfg.Port),
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Mask_Unset => FDI_TX_CTL_TRAINING_PATTERN_MASK,
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Mask_Set => FDI_TX_CTL_TRAINING_PATTERN_2);
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Registers.Posting_Read (TX_CTL (Port_Cfg.Port));
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PCH.FDI.Train (PCH_FDI_Port, PCH.FDI.TP_2, Success);
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end if;
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exit when Success;
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Registers.Unset_And_Set_Mask
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(Register => TX_CTL (Port_Cfg.Port),
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Mask_Unset => FDI_TX_CTL_FDI_TX_ENABLE or
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FDI_TX_CTL_TRAINING_PATTERN_MASK,
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Mask_Set => FDI_TX_CTL_TRAINING_PATTERN_1);
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PCH.FDI.Off (PCH_FDI_Port, PCH.FDI.Rx_Off);
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end loop;
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if Success then
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Registers.Unset_And_Set_Mask
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(Register => TX_CTL (Port_Cfg.Port),
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Mask_Unset => FDI_TX_CTL_TRAINING_PATTERN_MASK,
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Mask_Set => FDI_TX_CTL_TRAINING_PATTERN_NORMAL);
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Registers.Posting_Read (TX_CTL (Port_Cfg.Port));
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PCH.FDI.Train (PCH_FDI_Port, PCH.FDI.TP_None, Success);
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else
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Registers.Unset_Mask
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(Register => TX_CTL (Port_Cfg.Port),
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Mask => FDI_TX_CTL_FDI_PLL_ENABLE);
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PCH.FDI.Off (PCH_FDI_Port, PCH.FDI.Clock_Off);
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end if;
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end Full_Training;
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----------------------------------------------------------------------------
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--
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-- Used with original Ironlake (Nehalem CPU)
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--
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-- This is close to what Linux' i915 does. A comment in i915_reg.h
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-- states that it uses only the lowest voltage / pre-emphasis levels
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-- which is why we leave them at zero here and don't try different
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-- values.
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--
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-- It's actually not clear from i915's code if the values really are
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-- at zero or if it's just reusing what the Video BIOS set. Some code
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-- in coreboot sets them to zero explicitly.
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--
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procedure Simple_Training
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(Port_Cfg : in Port_Config;
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Success : out Boolean)
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with
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Pre => Port_Cfg.Port in GPU_FDI_Port
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is
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PCH_FDI_Port : constant PCH.FDI_Port_Type := PCH_FDIs (Port_Cfg.Port);
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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Registers.Unset_And_Set_Mask
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(Register => TX_CTL (Port_Cfg.Port),
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Mask_Unset => FDI_TX_CTL_TRAINING_PATTERN_MASK,
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Mask_Set => FDI_TX_CTL_FDI_TX_ENABLE or
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FDI_TX_CTL_TRAINING_PATTERN_1);
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Registers.Posting_Read (TX_CTL (Port_Cfg.Port));
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PCH.FDI.Train (PCH_FDI_Port, PCH.FDI.TP_1, Success);
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if Success then
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Registers.Unset_And_Set_Mask
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(Register => TX_CTL (Port_Cfg.Port),
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Mask_Unset => FDI_TX_CTL_TRAINING_PATTERN_MASK,
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Mask_Set => FDI_TX_CTL_TRAINING_PATTERN_2);
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Registers.Posting_Read (TX_CTL (Port_Cfg.Port));
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PCH.FDI.Train (PCH_FDI_Port, PCH.FDI.TP_2, Success);
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end if;
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if Success then
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Registers.Unset_And_Set_Mask
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(Register => TX_CTL (Port_Cfg.Port),
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Mask_Unset => FDI_TX_CTL_TRAINING_PATTERN_MASK,
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Mask_Set => FDI_TX_CTL_TRAINING_PATTERN_NORMAL);
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Registers.Posting_Read (TX_CTL (Port_Cfg.Port));
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PCH.FDI.Train (PCH_FDI_Port, PCH.FDI.TP_None, Success);
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else
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Registers.Unset_And_Set_Mask
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(Register => TX_CTL (Port_Cfg.Port),
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Mask_Unset => FDI_TX_CTL_FDI_TX_ENABLE or
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FDI_TX_CTL_TRAINING_PATTERN_MASK,
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Mask_Set => FDI_TX_CTL_TRAINING_PATTERN_1);
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PCH.FDI.Off (PCH_FDI_Port, PCH.FDI.Rx_Off);
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Registers.Unset_Mask
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(Register => TX_CTL (Port_Cfg.Port),
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Mask => FDI_TX_CTL_FDI_PLL_ENABLE);
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PCH.FDI.Off (PCH_FDI_Port, PCH.FDI.Clock_Off);
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end if;
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end Simple_Training;
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----------------------------------------------------------------------------
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procedure Pre_On (Port_Cfg : Port_Config)
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is
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Composite_Sel : constant :=
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(if Config.Has_FDI_Composite_Sel then
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FDI_TX_CTL_COMPOSITE_SYNC_SELECT else 0);
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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-- The PCH_FDI_CHICKEN_B_AND_C bit may not be changed when any of
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-- both ports is active. Bandwidth calculations before calling us
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-- should ensure this.
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if Config.Has_FDI_C then
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if Port_Cfg.Port = DIGI_D or
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(Port_Cfg.Port = DIGI_C and
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Port_Cfg.FDI.Lane_Count <= DP_Lane_Count_2)
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then
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Registers.Set_Mask
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(Register => Registers.PCH_FDI_CHICKEN_B_C,
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Mask => PCH_FDI_CHICKEN_B_AND_C);
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elsif Port_Cfg.Port = DIGI_C then
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Registers.Unset_Mask
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(Register => Registers.PCH_FDI_CHICKEN_B_C,
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Mask => PCH_FDI_CHICKEN_B_AND_C);
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end if;
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end if;
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PCH.FDI.Pre_Train (PCH_FDIs (Port_Cfg.Port), Port_Cfg);
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Registers.Write
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(Register => TX_CTL (Port_Cfg.Port),
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Value => FDI_TX_CTL_PORT_WIDTH_SEL (Port_Cfg.FDI.Lane_Count) or
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FDI_TX_CTL_ENHANCED_FRAMING_ENABLE or
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FDI_TX_CTL_FDI_PLL_ENABLE or
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Composite_Sel or
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FDI_TX_CTL_TRAINING_PATTERN_1);
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Registers.Posting_Read (TX_CTL (Port_Cfg.Port));
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Time.U_Delay (100);
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end Pre_On;
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----------------------------------------------------------------------------
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procedure Post_On
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(Port_Cfg : in Port_Config;
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Success : out Boolean)
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is
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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case Config.FDI_Training is
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when GMA.Simple_Training => Simple_Training (Port_Cfg, Success);
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when GMA.Full_Training => Full_Training (Port_Cfg, Success);
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when GMA.Auto_Training => Auto_Training (Port_Cfg, Success);
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end case;
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end Post_On;
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----------------------------------------------------------------------------
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procedure Off (Port : GPU_FDI_Port; OT : Off_Type)
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is
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PCH_FDI_Port : constant PCH.FDI_Port_Type := PCH_FDIs (Port);
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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Registers.Unset_And_Set_Mask
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(Register => TX_CTL (Port),
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Mask_Unset => FDI_TX_CTL_FDI_TX_ENABLE or
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FDI_TX_CTL_AUTO_TRAIN_ENABLE or
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FDI_TX_CTL_TRAINING_PATTERN_MASK,
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Mask_Set => FDI_TX_CTL_TRAINING_PATTERN_1);
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PCH.FDI.Off (PCH_FDI_Port, PCH.FDI.Rx_Off);
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if OT >= Clock_Off then
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Registers.Unset_Mask
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(Register => TX_CTL (Port),
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Mask => FDI_TX_CTL_FDI_PLL_ENABLE);
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PCH.FDI.Off (PCH_FDI_Port, PCH.FDI.Clock_Off);
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end if;
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end Off;
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end HW.GFX.GMA.Connectors.FDI;
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