298 lines
11 KiB
Ada
298 lines
11 KiB
Ada
--
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-- Copyright (C) 2015-2016 secunet Security Networks AG
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; version 2 of the License.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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with HW.Time;
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with HW.GFX.DP_Training;
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with HW.GFX.GMA.DP_Info;
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with HW.GFX.GMA.DP_Aux_Ch;
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with HW.GFX.GMA.Registers;
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with HW.Debug;
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with GNAT.Source_Info;
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package body HW.GFX.GMA.Connectors.EDP
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is
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DP_CTL_DISPLAYPORT_ENABLE : constant := 1 * 2 ** 31;
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DP_CTL_PIPE_SELECT_MASK : constant := 3 * 2 ** 29;
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DP_CTL_PIPE_SELECT_SHIFT : constant := 29;
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DP_CTL_VSWING_EMPH_SET_MASK : constant := 63 * 2 ** 22;
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DP_CTL_PORT_WIDTH_MASK : constant := 7 * 2 ** 19;
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DP_CTL_PORT_WIDTH_1_LANE : constant := 0 * 2 ** 19;
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DP_CTL_PORT_WIDTH_2_LANES : constant := 1 * 2 ** 19;
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DP_CTL_PORT_WIDTH_4_LANES : constant := 3 * 2 ** 19;
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DP_CTL_ENHANCED_FRAMING_ENABLE : constant := 1 * 2 ** 18;
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DP_CTL_PLL_FREQUENCY_MASK : constant := 3 * 2 ** 16;
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DP_CTL_PLL_FREQUENCY_270 : constant := 0 * 2 ** 16;
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DP_CTL_PLL_FREQUENCY_162 : constant := 1 * 2 ** 16;
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DP_CTL_PORT_REVERSAL : constant := 1 * 2 ** 15;
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DP_CTL_PLL_ENABLE : constant := 1 * 2 ** 14;
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DP_CTL_LINK_TRAIN_MASK : constant := 3 * 2 ** 8;
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DP_CTL_LINK_TRAIN_PAT1 : constant := 0 * 2 ** 8;
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DP_CTL_LINK_TRAIN_PAT2 : constant := 1 * 2 ** 8;
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DP_CTL_LINK_TRAIN_IDLE : constant := 2 * 2 ** 8;
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DP_CTL_LINK_TRAIN_NORMAL : constant := 3 * 2 ** 8;
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DP_CTL_ALT_SCRAMBLER_RESET : constant := 1 * 2 ** 6;
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DP_CTL_VSYNC_ACTIVE_HIGH : constant := 1 * 2 ** 4;
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DP_CTL_HSYNC_ACTIVE_HIGH : constant := 1 * 2 ** 3;
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DP_CTL_PORT_DETECT : constant := 1 * 2 ** 2;
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-- TODO? Values are for Ivy Bridge only
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DP_CTL_VSWING_0_EMPH_0 : constant := 1 * 2 ** 27 + 1 * 2 ** 24 + 0 * 2 ** 22;
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DP_CTL_VSWING_0_EMPH_1 : constant := 1 * 2 ** 27 + 2 * 2 ** 24 + 2 * 2 ** 22;
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DP_CTL_VSWING_0_EMPH_2 : constant := 1 * 2 ** 27 + 3 * 2 ** 24 + 3 * 2 ** 22;
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DP_CTL_VSWING_1_EMPH_0 : constant := 1 * 2 ** 27 + 4 * 2 ** 24 + 0 * 2 ** 22;
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DP_CTL_VSWING_1_EMPH_1 : constant := 1 * 2 ** 27 + 5 * 2 ** 24 + 2 * 2 ** 22;
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DP_CTL_VSWING_2_EMPH_0 : constant := 1 * 2 ** 27 + 6 * 2 ** 24 + 0 * 2 ** 22;
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DP_CTL_VSWING_2_EMPH_1 : constant := 1 * 2 ** 27 + 7 * 2 ** 24 + 2 * 2 ** 22;
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type DP_CTL_PORT_WIDTH_T is array (DP_Lane_Count) of Word32;
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DP_CTL_PORT_WIDTH : constant DP_CTL_PORT_WIDTH_T :=
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DP_CTL_PORT_WIDTH_T'
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(DP_Lane_Count_1 => DP_CTL_PORT_WIDTH_1_LANE,
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DP_Lane_Count_2 => DP_CTL_PORT_WIDTH_2_LANES,
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DP_Lane_Count_4 => DP_CTL_PORT_WIDTH_4_LANES);
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type DP_CTL_LINK_TRAIN_Array is array (DP_Info.Training_Pattern) of Word32;
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DP_CTL_LINK_TRAIN : constant DP_CTL_LINK_TRAIN_Array :=
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DP_CTL_LINK_TRAIN_Array'
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(DP_Info.TP_1 => DP_CTL_LINK_TRAIN_PAT1,
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DP_Info.TP_2 => DP_CTL_LINK_TRAIN_PAT2,
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DP_Info.TP_3 => DP_CTL_LINK_TRAIN_PAT2,
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DP_Info.TP_Idle => DP_CTL_LINK_TRAIN_IDLE,
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DP_Info.TP_None => DP_CTL_LINK_TRAIN_NORMAL);
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----------------------------------------------------------------------------
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procedure Pre_Training is
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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Registers.Unset_And_Set_Mask
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(Register => Registers.DP_CTL_A,
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Mask_Unset => DP_CTL_LINK_TRAIN_MASK,
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Mask_Set => DP_CTL_LINK_TRAIN (DP_Info.TP_1) or
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DP_CTL_DISPLAYPORT_ENABLE);
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end Pre_Training;
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----------------------------------------------------------------------------
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pragma Warnings (GNATprove, Off, "unused variable ""Port""",
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Reason => "Needed for a common interface");
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function Max_V_Swing
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(Port : Digital_Port)
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return DP_Info.DP_Voltage_Swing
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is
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begin
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return DP_Info.VS_Level_2;
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end Max_V_Swing;
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function Max_Pre_Emph
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(Port : Digital_Port;
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Train_Set : DP_Info.Train_Set)
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return DP_Info.DP_Pre_Emph
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is
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begin
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return
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(case Train_Set.Voltage_Swing is
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when DP_Info.VS_Level_0 => DP_Info.Emph_Level_2,
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when DP_Info.VS_Level_1 |
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DP_Info.VS_Level_2 => DP_Info.Emph_Level_1,
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when others => DP_Info.Emph_Level_0);
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end Max_Pre_Emph;
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----------------------------------------------------------------------------
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pragma Warnings (GNATprove, Off, "unused variable ""Link""",
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Reason => "Needed for a common interface");
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procedure Set_Training_Pattern
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(Port : Digital_Port;
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Link : DP_Link;
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Pattern : DP_Info.Training_Pattern)
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is
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use type DP_Info.Training_Pattern;
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begin
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if Pattern < DP_Info.TP_Idle then
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Registers.Unset_And_Set_Mask
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(Register => Registers.DP_CTL_A,
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Mask_Unset => DP_CTL_LINK_TRAIN_MASK,
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Mask_Set => DP_CTL_LINK_TRAIN (Pattern));
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else
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-- send at least 5 idle patterns
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Registers.Unset_And_Set_Mask
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(Register => Registers.DP_CTL_A,
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Mask_Unset => DP_CTL_LINK_TRAIN_MASK,
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Mask_Set => DP_CTL_LINK_TRAIN (DP_Info.TP_Idle));
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-- we switch to normal frame delivery later in Post_On procedure
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end if;
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end Set_Training_Pattern;
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procedure Set_Signal_Levels
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(Port : Digital_Port;
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Link : DP_Link;
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Train_Set : DP_Info.Train_Set)
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is
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VSwing_Emph : Word32;
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begin
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VSwing_Emph :=
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(case Train_Set.Voltage_Swing is
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when DP_Info.VS_Level_0 =>
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(case Train_Set.Pre_Emph is
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when DP_Info.Emph_Level_0 => DP_CTL_VSWING_0_EMPH_0,
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when DP_Info.Emph_Level_1 => DP_CTL_VSWING_0_EMPH_1,
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when DP_Info.Emph_Level_2 => DP_CTL_VSWING_0_EMPH_2,
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when others => DP_CTL_VSWING_0_EMPH_0),
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when DP_Info.VS_Level_1 =>
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(case Train_Set.Pre_Emph is
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when DP_Info.Emph_Level_0 => DP_CTL_VSWING_1_EMPH_0,
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when DP_Info.Emph_Level_1 => DP_CTL_VSWING_1_EMPH_1,
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when others => DP_CTL_VSWING_1_EMPH_0),
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when DP_Info.VS_Level_2 =>
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(case Train_Set.Pre_Emph is
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when DP_Info.Emph_Level_0 => DP_CTL_VSWING_2_EMPH_0,
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when DP_Info.Emph_Level_1 => DP_CTL_VSWING_2_EMPH_1,
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when others => DP_CTL_VSWING_2_EMPH_0),
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when others => DP_CTL_VSWING_0_EMPH_0);
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Registers.Unset_And_Set_Mask
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(Register => Registers.DP_CTL_A,
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Mask_Unset => DP_CTL_VSWING_EMPH_SET_MASK,
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Mask_Set => VSwing_Emph);
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end Set_Signal_Levels;
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pragma Warnings (GNATprove, On, "unused variable ""Port""");
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pragma Warnings (GNATprove, On, "unused variable ""Link""");
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----------------------------------------------------------------------------
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procedure Pre_On
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(Port_Cfg : Port_Config;
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Pipe_Hint : Word32)
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is
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DP_CTL_Set : Word32;
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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DP_CTL_Set :=
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Shift_Left (Pipe_Hint, DP_CTL_PIPE_SELECT_SHIFT) or
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DP_CTL_PORT_WIDTH (Port_Cfg.DP.Lane_Count);
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if Port_Cfg.DP.Enhanced_Framing then
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DP_CTL_Set := DP_CTL_Set or DP_CTL_ENHANCED_FRAMING_ENABLE;
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end if;
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case Port_Cfg.DP.Bandwidth is
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when DP_Bandwidth_1_62 =>
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DP_CTL_Set := DP_CTL_Set or DP_CTL_PLL_FREQUENCY_162;
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when DP_Bandwidth_2_7 =>
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DP_CTL_Set := DP_CTL_Set or DP_CTL_PLL_FREQUENCY_270;
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when others =>
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null;
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end case;
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if Port_Cfg.Mode.V_Sync_Active_High then
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DP_CTL_Set := DP_CTL_Set or DP_CTL_VSYNC_ACTIVE_HIGH;
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end if;
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if Port_Cfg.Mode.H_Sync_Active_High then
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DP_CTL_Set := DP_CTL_Set or DP_CTL_HSYNC_ACTIVE_HIGH;
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end if;
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Registers.Write
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(Register => Registers.DP_CTL_A,
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Value => DP_CTL_Set);
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Registers.Write
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(Register => Registers.DP_CTL_A,
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Value => DP_CTL_PLL_ENABLE or DP_CTL_Set);
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Registers.Posting_Read (Registers.DP_CTL_A);
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Time.U_Delay (20);
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end Pre_On;
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----------------------------------------------------------------------------
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procedure Post_On
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(Link : in DP_Link;
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Success : out Boolean)
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is
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pragma Warnings (GNATprove, Off, "unused variable ""Port""",
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Reason => "Needed for a common interface");
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function To_DP (Port : Digital_Port) return DP_Port
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is
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begin
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return DP_A;
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end To_DP;
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pragma Warnings (GNATprove, On, "unused variable ""Port""");
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package Training is new DP_Training
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(TPS3_Supported => False,
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T => Digital_Port,
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Aux_T => DP_Port,
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Aux_Ch => DP_Aux_Ch,
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DP_Info => DP_Info,
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To_Aux => To_DP,
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Max_V_Swing => Max_V_Swing,
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Max_Pre_Emph => Max_Pre_Emph,
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Set_Pattern => Set_Training_Pattern,
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Set_Signal_Levels => Set_Signal_Levels,
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Off => Off);
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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Training.Train_DP
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(Port => DIGI_A,
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Link => Link,
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Success => Success);
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if Success then
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Registers.Unset_And_Set_Mask
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(Register => Registers.DP_CTL_A,
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Mask_Unset => DP_CTL_LINK_TRAIN_MASK,
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Mask_Set => DP_CTL_LINK_TRAIN_NORMAL);
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end if;
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end Post_On;
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----------------------------------------------------------------------------
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procedure Off (Port : Digital_Port)
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is
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Enabled : Boolean;
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begin
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pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
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Registers.Unset_And_Set_Mask
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(Register => Registers.DP_CTL_A,
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Mask_Unset => DP_CTL_LINK_TRAIN_MASK,
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Mask_Set => DP_CTL_LINK_TRAIN_IDLE);
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Registers.Posting_Read (Registers.DP_CTL_A);
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Registers.Unset_Mask
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(Register => Registers.DP_CTL_A,
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Mask => DP_CTL_DISPLAYPORT_ENABLE);
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-- implicit Posting_Read below
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Registers.Is_Set_Mask
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(Register => Registers.DP_CTL_A,
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Mask => DP_CTL_PLL_ENABLE,
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Result => Enabled);
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Registers.Write
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(Register => Registers.DP_CTL_A,
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Value => 16#0000_0000#);
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Registers.Posting_Read (Registers.DP_CTL_A);
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if Enabled then
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Time.U_Delay (20);
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end if;
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end Off;
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end HW.GFX.GMA.Connectors.EDP;
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