294 lines
11 KiB
Ada
294 lines
11 KiB
Ada
--
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-- Copyright (C) 2015-2016 secunet Security Networks AG
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; version 2 of the License.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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with HW.Time;
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with HW.GFX.GMA.Config;
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with HW.GFX.GMA.Registers;
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package body HW.GFX.GMA.PCH.FDI is
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FDI_RX_CTL_FDI_RX_ENABLE : constant := 1 * 2 ** 31;
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FDI_RX_CTL_FS_ERROR_CORRECTION_ENABLE : constant := 1 * 2 ** 27;
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FDI_RX_CTL_FE_ERROR_CORRECTION_ENABLE : constant := 1 * 2 ** 26;
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FDI_RX_CTL_PORT_WIDTH_SEL_SHIFT : constant := 19;
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FDI_RX_CTL_FDI_PLL_ENABLE : constant := 1 * 2 ** 13;
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FDI_RX_CTL_COMPOSITE_SYNC_SELECT : constant := 1 * 2 ** 11;
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FDI_RX_CTL_FDI_AUTO_TRAIN : constant := 1 * 2 ** 10;
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FDI_RX_CTL_ENHANCED_FRAMING_ENABLE : constant := 1 * 2 ** 6;
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FDI_RX_CTL_RAWCLK_TO_PCDCLK_SEL_MASK : constant := 1 * 2 ** 4;
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FDI_RX_CTL_RAWCLK_TO_PCDCLK_SEL_RAWCLK : constant := 0 * 2 ** 4;
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FDI_RX_CTL_RAWCLK_TO_PCDCLK_SEL_PCDCLK : constant := 1 * 2 ** 4;
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TP_SHIFT : constant := (if Config.CPU = Ironlake then 28 else 8);
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FDI_RX_CTL_TRAINING_PATTERN_MASK : constant := 3 * 2 ** TP_SHIFT;
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type TP_Array is array (Training_Pattern) of Word32;
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FDI_RX_CTL_TRAINING_PATTERN : constant TP_Array :=
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(TP_1 => 0 * 2 ** TP_SHIFT,
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TP_2 => 1 * 2 ** TP_SHIFT,
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TP_Idle => 2 * 2 ** TP_SHIFT,
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TP_None => 3 * 2 ** TP_SHIFT);
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function FDI_RX_CTL_PORT_WIDTH_SEL (Lane_Count : DP_Lane_Count) return Word32
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is
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begin
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return Shift_Left
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(Word32 (Lane_Count_As_Integer (Lane_Count)) - 1,
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FDI_RX_CTL_PORT_WIDTH_SEL_SHIFT);
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end FDI_RX_CTL_PORT_WIDTH_SEL;
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function FDI_RX_CTL_BPC (BPC : BPC_Type) return Word32
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with Pre => True
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is
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begin
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return
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(case BPC is
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when 6 => 2 * 2 ** 16,
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when 10 => 1 * 2 ** 16,
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when 12 => 3 * 2 ** 16,
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when others => 0 * 2 ** 16);
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end FDI_RX_CTL_BPC;
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FDI_RX_MISC_FDI_RX_PWRDN_LANE1_SHIFT : constant := 26;
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FDI_RX_MISC_FDI_RX_PWRDN_LANE1_MASK : constant := 3 * 2 ** 26;
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FDI_RX_MISC_FDI_RX_PWRDN_LANE0_SHIFT : constant := 24;
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FDI_RX_MISC_FDI_RX_PWRDN_LANE0_MASK : constant := 3 * 2 ** 24;
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FDI_RX_MISC_TP1_TO_TP2_TIME_48 : constant := 2 * 2 ** 20;
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FDI_RX_MISC_FDI_DELAY_90 : constant := 16#90# * 2 ** 0;
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function FDI_RX_MISC_FDI_RX_PWRDN_LANE1 (Value : Word32) return Word32
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with Pre => True
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is
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begin
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return Shift_Left (Value, FDI_RX_MISC_FDI_RX_PWRDN_LANE1_SHIFT);
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end FDI_RX_MISC_FDI_RX_PWRDN_LANE1;
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function FDI_RX_MISC_FDI_RX_PWRDN_LANE0 (Value : Word32) return Word32
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with Pre => True
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is
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begin
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return Shift_Left (Value, FDI_RX_MISC_FDI_RX_PWRDN_LANE0_SHIFT);
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end FDI_RX_MISC_FDI_RX_PWRDN_LANE0;
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FDI_RX_TUSIZE_SHIFT : constant := 25;
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function FDI_RX_TUSIZE (Value : Word32) return Word32 is
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begin
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return Shift_Left (Value - 1, FDI_RX_TUSIZE_SHIFT);
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end FDI_RX_TUSIZE;
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FDI_RX_INTERLANE_ALIGNMENT : constant := 1 * 2 ** 10;
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FDI_RX_SYMBOL_LOCK : constant := 1 * 2 ** 9;
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FDI_RX_BIT_LOCK : constant := 1 * 2 ** 8;
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----------------------------------------------------------------------------
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type FDI_Registers is record
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RX_CTL : Registers.Registers_Index;
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RX_MISC : Registers.Registers_Index;
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RX_TUSIZE : Registers.Registers_Index;
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RX_IMR : Registers.Registers_Index;
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RX_IIR : Registers.Registers_Index;
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end record;
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type FDI_Registers_Array is array (PCH.FDI_Port_Type) of FDI_Registers;
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FDI_Regs : constant FDI_Registers_Array := FDI_Registers_Array'
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(PCH.FDI_A => FDI_Registers'
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(RX_CTL => Registers.FDI_RXA_CTL,
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RX_MISC => Registers.FDI_RX_MISC_A,
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RX_TUSIZE => Registers.FDI_RXA_TUSIZE1,
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RX_IMR => Registers.FDI_RXA_IMR,
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RX_IIR => Registers.FDI_RXA_IIR),
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PCH.FDI_B => FDI_Registers'
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(RX_CTL => Registers.FDI_RXB_CTL,
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RX_MISC => Registers.FDI_RX_MISC_B,
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RX_TUSIZE => Registers.FDI_RXB_TUSIZE1,
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RX_IMR => Registers.FDI_RXB_IMR,
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RX_IIR => Registers.FDI_RXB_IIR),
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PCH.FDI_C => FDI_Registers'
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(RX_CTL => Registers.FDI_RXC_CTL,
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RX_MISC => Registers.FDI_RX_MISC_C,
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RX_TUSIZE => Registers.FDI_RXC_TUSIZE1,
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RX_IMR => Registers.FDI_RXC_IMR,
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RX_IIR => Registers.FDI_RXC_IIR));
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----------------------------------------------------------------------------
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procedure Pre_Train (Port : PCH.FDI_Port_Type; Port_Cfg : Port_Config)
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is
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Power_Down_Lane_Bits : constant Word32 :=
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(if Config.Has_FDI_RX_Power_Down then
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FDI_RX_MISC_FDI_RX_PWRDN_LANE1 (2) or
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FDI_RX_MISC_FDI_RX_PWRDN_LANE0 (2)
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else 0);
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RX_CTL_Settings : constant Word32 :=
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FDI_RX_CTL_PORT_WIDTH_SEL (Port_Cfg.FDI.Lane_Count) or
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(if Config.Has_FDI_BPC then
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FDI_RX_CTL_BPC (Port_Cfg.Mode.BPC) else 0) or
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(if Config.Has_FDI_Composite_Sel then
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FDI_RX_CTL_COMPOSITE_SYNC_SELECT else 0) or
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(if Port_Cfg.FDI.Enhanced_Framing then
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FDI_RX_CTL_ENHANCED_FRAMING_ENABLE else 0);
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begin
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-- TODO: HSW: check DISPIO_CR_TX_BMU_CR4, seems Linux doesn't know it
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Registers.Write
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(Register => FDI_Regs (Port).RX_MISC,
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Value => Power_Down_Lane_Bits or
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FDI_RX_MISC_TP1_TO_TP2_TIME_48 or
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FDI_RX_MISC_FDI_DELAY_90);
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Registers.Write
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(Register => FDI_Regs (Port).RX_TUSIZE,
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Value => FDI_RX_TUSIZE (64));
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Registers.Unset_Mask
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(Register => FDI_Regs (Port).RX_IMR,
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Mask => FDI_RX_INTERLANE_ALIGNMENT or
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FDI_RX_SYMBOL_LOCK or
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FDI_RX_BIT_LOCK);
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Registers.Posting_Read (FDI_Regs (Port).RX_IMR);
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-- clear stale lock bits
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Registers.Write
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(Register => FDI_Regs (Port).RX_IIR,
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Value => FDI_RX_INTERLANE_ALIGNMENT or
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FDI_RX_SYMBOL_LOCK or
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FDI_RX_BIT_LOCK);
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Registers.Write
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(Register => FDI_Regs (Port).RX_CTL,
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Value => FDI_RX_CTL_FDI_PLL_ENABLE or
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RX_CTL_Settings);
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Registers.Posting_Read (FDI_Regs (Port).RX_CTL);
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Time.U_Delay (220);
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Registers.Set_Mask
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(Register => FDI_Regs (Port).RX_CTL,
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Mask => FDI_RX_CTL_RAWCLK_TO_PCDCLK_SEL_PCDCLK);
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end Pre_Train;
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procedure Train
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(Port : in PCH.FDI_Port_Type;
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TP : in Training_Pattern;
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Success : out Boolean)
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is
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Lock_Bit : constant Word32 :=
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(if TP = TP_1 then FDI_RX_BIT_LOCK else FDI_RX_SYMBOL_LOCK);
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procedure Check_Lock (Lock_Bit : Word32)
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is
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begin
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for I in 1 .. 5 loop
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Registers.Is_Set_Mask
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(Register => FDI_Regs (Port).RX_IIR,
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Mask => Lock_Bit,
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Result => Success);
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if Success then
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-- clear the lock bit
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Registers.Write
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(Register => FDI_Regs (Port).RX_IIR,
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Value => Lock_Bit);
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end if;
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exit when Success;
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Time.U_Delay (1);
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end loop;
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end Check_Lock;
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begin
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Registers.Unset_And_Set_Mask
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(Register => FDI_Regs (Port).RX_CTL,
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Mask_Unset => FDI_RX_CTL_TRAINING_PATTERN_MASK,
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Mask_Set => FDI_RX_CTL_FDI_RX_ENABLE or
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FDI_RX_CTL_TRAINING_PATTERN (TP));
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Registers.Posting_Read (FDI_Regs (Port).RX_CTL);
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if TP <= TP_2 then
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Time.U_Delay (1);
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if TP = TP_1 then
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Check_Lock (FDI_RX_BIT_LOCK);
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else
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Check_Lock (FDI_RX_SYMBOL_LOCK);
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if Success then
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Check_Lock (FDI_RX_INTERLANE_ALIGNMENT);
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end if;
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end if;
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else
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Time.U_Delay (31);
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Success := True;
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end if;
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end Train;
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procedure Auto_Train (Port : PCH.FDI_Port_Type)
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is
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begin
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Registers.Set_Mask
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(Register => FDI_Regs (Port).RX_CTL,
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Mask => FDI_RX_CTL_FDI_RX_ENABLE or
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FDI_RX_CTL_FDI_AUTO_TRAIN);
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Registers.Posting_Read (FDI_Regs (Port).RX_CTL);
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if Config.Has_FDI_RX_Power_Down then
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Time.U_Delay (30);
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Registers.Unset_And_Set_Mask
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(Register => FDI_Regs (Port).RX_MISC,
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Mask_Unset => FDI_RX_MISC_FDI_RX_PWRDN_LANE1_MASK or
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FDI_RX_MISC_FDI_RX_PWRDN_LANE0_MASK,
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Mask_Set => FDI_RX_MISC_FDI_RX_PWRDN_LANE1 (0) or
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FDI_RX_MISC_FDI_RX_PWRDN_LANE0 (0));
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Registers.Posting_Read (FDI_Regs (Port).RX_MISC);
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end if;
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Time.U_Delay (5);
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end Auto_Train;
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procedure Enable_EC (Port : PCH.FDI_Port_Type)
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is
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begin
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Registers.Set_Mask
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(Register => FDI_Regs (Port).RX_CTL,
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Mask => FDI_RX_CTL_FS_ERROR_CORRECTION_ENABLE or
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FDI_RX_CTL_FE_ERROR_CORRECTION_ENABLE);
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end Enable_EC;
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----------------------------------------------------------------------------
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procedure Off (Port : PCH.FDI_Port_Type; OT : Off_Type)
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is
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begin
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Registers.Unset_Mask
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(Register => FDI_Regs (Port).RX_CTL,
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Mask => FDI_RX_CTL_FDI_RX_ENABLE or
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FDI_RX_CTL_FDI_AUTO_TRAIN);
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if Config.Has_FDI_RX_Power_Down and then OT >= Lanes_Off then
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Registers.Unset_And_Set_Mask
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(Register => FDI_Regs (Port).RX_MISC,
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Mask_Unset => FDI_RX_MISC_FDI_RX_PWRDN_LANE1_MASK or
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FDI_RX_MISC_FDI_RX_PWRDN_LANE0_MASK,
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Mask_Set => FDI_RX_MISC_FDI_RX_PWRDN_LANE1 (2) or
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FDI_RX_MISC_FDI_RX_PWRDN_LANE0 (2));
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Registers.Posting_Read (FDI_Regs (Port).RX_MISC);
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end if;
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if OT >= Clock_Off then
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Registers.Unset_And_Set_Mask
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(Register => FDI_Regs (Port).RX_CTL,
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Mask_Unset => FDI_RX_CTL_RAWCLK_TO_PCDCLK_SEL_MASK,
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Mask_Set => FDI_RX_CTL_RAWCLK_TO_PCDCLK_SEL_RAWCLK);
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Registers.Unset_Mask
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(Register => FDI_Regs (Port).RX_CTL,
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Mask => FDI_RX_CTL_FDI_PLL_ENABLE);
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end if;
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end Off;
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end HW.GFX.GMA.PCH.FDI;
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