352 lines
11 KiB
Ada
352 lines
11 KiB
Ada
--
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-- Copyright (C) 2015 secunet Security Networks AG
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; version 2 of the License.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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with HW.Time;
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with HW.GFX.GMA.Registers;
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package body HW.GFX.GMA.PLLs.WRPLL is
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----------------------------------------------------------------------------
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--
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-- Divider calculation as found in Linux' i915 driver
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--
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-- Copyright (C) 2012 Intel Corporation
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--
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-- Permission is hereby granted, free of charge, to any person obtaining a
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-- copy of this software and associated documentation files (the "Software"),
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-- to deal in the Software without restriction, including without limitation
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-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
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-- and/or sell copies of the Software, and to permit persons to whom the
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-- Software is furnished to do so, subject to the following conditions:
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--
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-- The above copyright notice and this permission notice (including the next
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-- paragraph) shall be included in all copies or substantial portions of the
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-- Software.
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--
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-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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-- THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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-- IN THE SOFTWARE.
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--
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-- Authors:
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-- Eugeni Dodonov <eugeni.dodonov@intel.com>
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--
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LC_FREQ : constant := 2700; -- in MHz
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LC_FREQ_2K : constant := LC_FREQ * 2000; -- in 500Hz
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P_MIN : constant := 2;
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P_MAX : constant := 62; -- i915 says 64, but this would overflow 6-bit
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P_INC : constant := 2;
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-- Constraints for PLL good behavior
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REF_MIN : constant := 48;
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REF_MAX : constant := 400;
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VCO_MIN : constant := 2400;
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VCO_MAX : constant := 4800;
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type R2_Range is new Natural range 0 .. LC_FREQ * 2 / REF_MIN;
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type N2_Range is new Natural range 0 .. VCO_MAX * Natural (R2_Range'Last) / LC_FREQ;
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type P_Range is new Natural range 0 .. P_MAX;
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type RNP is record
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P : P_Range;
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N2 : N2_Range;
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R2 : R2_Range;
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end record;
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Invalid_RNP : constant RNP := RNP'(0, 0, 0);
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function Get_Budget_For_Freq
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(Clock : HW.GFX.Frequency_Type)
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return Word64
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is
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Result : Word64;
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begin
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case Clock is
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when 25175000 |
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25200000 |
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27000000 |
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27027000 |
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37762500 |
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37800000 |
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40500000 |
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40541000 |
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54000000 |
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54054000 |
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59341000 |
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59400000 |
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72000000 |
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74176000 |
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74250000 |
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81000000 |
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81081000 |
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89012000 |
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89100000 |
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108000000 |
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108108000 |
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111264000 |
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111375000 |
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148352000 |
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148500000 |
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162000000 |
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162162000 |
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222525000 |
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222750000 |
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296703000 |
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297000000 =>
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Result := 0;
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when 233500000 |
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245250000 |
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247750000 |
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253250000 |
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298000000 =>
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Result := 1500;
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when 169128000 |
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169500000 |
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179500000 |
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202000000 =>
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Result := 2000;
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when 256250000 |
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262500000 |
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270000000 |
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272500000 |
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273750000 |
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280750000 |
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281250000 |
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286000000 |
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291750000 =>
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Result := 4000;
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when 267250000 |
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268500000 =>
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Result := 5000;
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when others =>
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Result := 1000;
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end case;
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return Result;
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end Get_Budget_For_Freq;
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procedure Update_RNP
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(Freq_2K : in Word64;
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Budget : in Word64;
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R2 : in R2_Range;
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N2 : in N2_Range;
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P : in P_Range;
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Best : in out RNP)
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with
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Depends => (Best =>+ (Freq_2K, Budget, R2, N2, P))
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is
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use type HW.Word64;
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function Abs_Diff (A, B : Word64) return Word64
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is
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Result : Word64;
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begin
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if A > B then
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Result := A - B;
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else
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Result := B - A;
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end if;
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return Result;
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end Abs_Diff;
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A, B, C, D, Diff, Diff_Best : Word64;
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begin
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-- No best (r,n,p) yet */
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if Best.P = 0 then
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Best.P := P;
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Best.N2 := N2;
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Best.R2 := R2;
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else
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-- Config clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
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-- freq2k.
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--
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-- delta = 1e6 *
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-- abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
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-- freq2k;
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--
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-- and we would like delta <= budget.
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--
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-- If the discrepancy is above the PPM-based budget, always prefer to
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-- improve upon the previous solution. However, if you're within the
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-- budget, try to maximize Ref * VCO, that is N / (P * R^2).
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A := Freq_2K * Budget * Word64 (P) * Word64 (R2);
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B := Freq_2K * Budget * Word64 (Best.P) * Word64 (Best.R2);
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Diff := Abs_Diff
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(Freq_2K * Word64 (P) * Word64 (R2),
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LC_FREQ_2K * Word64 (N2));
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Diff_Best := Abs_Diff
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(Freq_2K * Word64 (Best.P) * Word64 (Best.R2),
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LC_FREQ_2K * Word64 (Best.N2));
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C := 1000000 * Diff;
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D := 1000000 * Diff_Best;
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if A < C and B < D then
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-- If both are above the Budget, pick the closer
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if Word64 (Best.P) * Word64 (Best.R2) * Diff
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< Word64 (P) * Word64 (R2) * Diff_Best
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then
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Best.P := P;
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Best.N2 := N2;
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Best.R2 := R2;
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end if;
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elsif A >= C and B < D then
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-- If A is below the threshold but B is above it? Update.
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Best.P := P;
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Best.N2 := N2;
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Best.R2 := R2;
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elsif A >= C and B >= D then
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-- Both are below the limit, so pick the higher N2/(R2*R2)
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if Word64 (N2) * Word64 (Best.R2) * Word64 (Best.R2)
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> Word64 (Best.N2) * Word64 (R2) * Word64 (R2)
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then
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Best.P := P;
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Best.N2 := N2;
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Best.R2 := R2;
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end if;
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end if;
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-- Otherwise A < C && B >= D, do nothing
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end if;
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end Update_RNP;
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procedure Calculate_WRPLL
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(Clock : in HW.GFX.Frequency_Type;
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R2_Out : out R2_Range;
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N2_Out : out N2_Range;
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P_Out : out P_Range)
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with
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Global => null,
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Pre => True,
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Post => True
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is
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use type HW.Word64;
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Freq_2K : Word64;
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Budget : Word64;
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Best : RNP := Invalid_RNP;
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begin
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Freq_2K := Word64 (Clock) / 100; -- PLL output should be 5x
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-- the pixel clock
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Budget := Get_Budget_For_Freq (Clock);
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-- Special case handling for 540MHz pixel clock: bypass WR PLL entirely
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-- and directly pass the LC PLL to it. */
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if Freq_2K = 5400000 then
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N2_Out := 2;
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P_Out := 1;
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R2_Out := 2;
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else
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-- Ref = LC_FREQ / R, where Ref is the actual reference input seen by
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-- the WR PLL.
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--
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-- We want R so that REF_MIN <= Ref <= REF_MAX.
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-- Injecting R2 = 2 * R gives:
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-- REF_MAX * r2 > LC_FREQ * 2 and
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-- REF_MIN * r2 < LC_FREQ * 2
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--
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-- Which means the desired boundaries for r2 are:
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-- LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
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--
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for R2 in R2_Range range
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LC_FREQ * 2 / REF_MAX + 1 .. LC_FREQ * 2 / REF_MIN
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loop
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-- VCO = N * Ref, that is: VCO = N * LC_FREQ / R
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--
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-- Once again we want VCO_MIN <= VCO <= VCO_MAX.
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-- Injecting R2 = 2 * R and N2 = 2 * N, we get:
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-- VCO_MAX * r2 > n2 * LC_FREQ and
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-- VCO_MIN * r2 < n2 * LC_FREQ)
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--
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-- Which means the desired boundaries for n2 are:
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-- VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
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for N2 in N2_Range range
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N2_Range (VCO_MIN * Natural (R2) / LC_FREQ + 1)
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.. N2_Range (VCO_MAX * Natural (R2) / LC_FREQ)
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loop
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for P_Fract in Natural range P_MIN / P_INC .. P_MAX / P_INC
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loop
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Update_RNP
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(Freq_2K, Budget, R2, N2, P_Range (P_Fract * P_INC), Best);
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end loop;
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end loop;
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end loop;
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N2_Out := Best.N2;
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P_Out := Best.P;
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R2_Out := Best.R2;
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end if;
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end Calculate_WRPLL;
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--
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----------------------------------------------------------------------------
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type Regs is array (WRPLLs) of Registers.Registers_Index;
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WRPLL_CTL : constant Regs := Regs'(Registers.WRPLL_CTL_1, Registers.WRPLL_CTL_2);
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WRPLL_CTL_PLL_ENABLE : constant := 1 * 2 ** 31;
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WRPLL_CTL_SELECT_LCPLL : constant := 3 * 2 ** 28;
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function WRPLL_CTL_DIVIDER_FEEDBACK (N2 : N2_Range) return Word32
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is
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begin
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return Word32 (N2) * 2 ** 16;
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end WRPLL_CTL_DIVIDER_FEEDBACK;
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function WRPLL_CTL_DIVIDER_POST (P : P_Range) return Word32
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is
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begin
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return Word32 (P) * 2 ** 8;
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end WRPLL_CTL_DIVIDER_POST;
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function WRPLL_CTL_DIVIDER_REFERENCE (R2 : R2_Range) return Word32
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is
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begin
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return Word32 (R2) * 2 ** 0;
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end WRPLL_CTL_DIVIDER_REFERENCE;
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----------------------------------------------------------------------------
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procedure On
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(PLL : in WRPLLs;
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Target_Clock : in Frequency_Type;
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Success : out Boolean)
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is
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R2 : R2_Range;
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N2 : N2_Range;
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P : P_Range;
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begin
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Calculate_WRPLL (Target_Clock, R2, N2, P);
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Registers.Write
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(Register => WRPLL_CTL (PLL),
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Value => WRPLL_CTL_PLL_ENABLE or
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WRPLL_CTL_SELECT_LCPLL or
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WRPLL_CTL_DIVIDER_FEEDBACK (N2) or
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WRPLL_CTL_DIVIDER_POST (P) or
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WRPLL_CTL_DIVIDER_REFERENCE (R2));
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Registers.Posting_Read (WRPLL_CTL (PLL));
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Time.U_Delay (20);
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Success := True;
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end On;
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procedure Off (PLL : WRPLLs)
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is
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begin
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Registers.Unset_Mask (WRPLL_CTL (PLL), WRPLL_CTL_PLL_ENABLE);
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end Off;
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end HW.GFX.GMA.PLLs.WRPLL;
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